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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_rf.v] - Blame information for rev 10

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1 5 rudi 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
3 
////  WISHBONE DMA Register File                                 ////
4 
////                                                             ////
5 
////                                                             ////
6 
////  Author: Rudolf Usselmann                                   ////
7 
////          rudi@asics.ws                                      ////
8 
////                                                             ////
9 
////                                                             ////
10 
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
11 
////                                                             ////
12 
/////////////////////////////////////////////////////////////////////
13 
////                                                             ////
14 
//// Copyright (C) 2001 Rudolf Usselmann                         ////
15 
////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
18 
//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
20 
//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
37 
 
38 
//  CVS Log
39 
//
40 10 rudi 
//  $Id: wb_dma_rf.v,v 1.3 2001-10-19 04:35:04 rudi Exp $
41 5 rudi 
//
42 10 rudi 
//  $Date: 2001-10-19 04:35:04 $
43 
//  $Revision: 1.3 $
44 5 rudi 
//  $Author: rudi $
45 
//  $Locker:  $
46 
//  $State: Exp $
47 
//
48 
// Change History:
49 
//               $Log: not supported by cvs2svn $
50 10 rudi 
//               Revision 1.2  2001/08/15 05:40:30  rudi
51 
//
52 
//               - Changed IO names to be more clear.
53 
//               - Uniquifyed define names to be core specific.
54 
//               - Added Section 3.10, describing DMA restart.
55 
//
56 8 rudi 
//               Revision 1.1  2001/07/29 08:57:02  rudi
57 
//
58 
//
59 
//               1) Changed Directory Structure
60 
//               2) Added restart signal (REST)
61 
//
62 5 rudi 
//               Revision 1.4  2001/06/14 08:50:46  rudi
63 
//
64 
//               Changed name of channel register file module.
65 
//
66 
//               Revision 1.3  2001/06/13 02:26:48  rudi
67 
//
68 
//
69 
//               Small changes after running lint.
70 
//
71 
//               Revision 1.2  2001/06/05 10:22:37  rudi
72 
//
73 
//
74 
//               - Added Support of up to 31 channels
75 
//               - Added support for 2,4 and 8 priority levels
76 
//               - Now can have up to 31 channels
77 
//               - Added many configuration items
78 
//               - Changed reset to async
79 
//
80 
//               Revision 1.1.1.1  2001/03/19 13:10:11  rudi
81 
//               Initial Release
82 
//
83 
//
84 
//
85 
 
86 
`include "wb_dma_defines.v"
87 
 
88 
module wb_dma_rf(clk, rst,
89 
 
90 
        // WISHBONE Access
91 
        wb_rf_adr, wb_rf_din, wb_rf_dout, wb_rf_re, wb_rf_we,
92 
 
93 
        // WISHBONE Interrupt outputs
94 
        inta_o, intb_o,
95 
 
96 
        // DMA Registers Outputs
97 
        pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1,
98 
        pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1,
99 
        pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1,
100 
        pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1,
101 
        pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1,
102 
        pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1,
103 
        pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1,
104 
        pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1,
105 
        pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1,
106 
        pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1,
107 
        pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1,
108 
        pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1,
109 
        pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1,
110 
        pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1,
111 
        pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1,
112 
        pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1,
113 
        pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1,
114 
        pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1,
115 
        pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1,
116 
        pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1,
117 
        pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1,
118 
        pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1,
119 
        pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1,
120 
        pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1,
121 
        pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1,
122 
        pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1,
123 
        pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1,
124 
        pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1,
125 
        pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1,
126 
        pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1,
127 
        pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1,
128 
 
129 
        // DMA Registers Write Back Channel Select
130 
        ch_sel, ndnr,
131 
 
132 
        // DMA Engine Status
133 
        pause_req, paused, dma_abort, dma_busy, dma_err, dma_done, dma_done_all,
134 
 
135 
        // DMA Engine Reg File Update ctrl signals
136 
        de_csr, de_txsz, de_adr0, de_adr1,
137 
        de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, de_fetch_descr, dma_rest,
138 
        ptr_set
139 
        );
140 
 
141 10 rudi 
////////////////////////////////////////////////////////////////////
142 
//
143 
// Module Parameters
144 
//
145 
 
146 
// chXX_conf = { CBUF, ED, ARS, EN }
147 
parameter       [3:0]    ch0_conf = 4'h1;
148 
parameter       [3:0]    ch1_conf = 4'h0;
149 
parameter       [3:0]    ch2_conf = 4'h0;
150 
parameter       [3:0]    ch3_conf = 4'h0;
151 
parameter       [3:0]    ch4_conf = 4'h0;
152 
parameter       [3:0]    ch5_conf = 4'h0;
153 
parameter       [3:0]    ch6_conf = 4'h0;
154 
parameter       [3:0]    ch7_conf = 4'h0;
155 
parameter       [3:0]    ch8_conf = 4'h0;
156 
parameter       [3:0]    ch9_conf = 4'h0;
157 
parameter       [3:0]    ch10_conf = 4'h0;
158 
parameter       [3:0]    ch11_conf = 4'h0;
159 
parameter       [3:0]    ch12_conf = 4'h0;
160 
parameter       [3:0]    ch13_conf = 4'h0;
161 
parameter       [3:0]    ch14_conf = 4'h0;
162 
parameter       [3:0]    ch15_conf = 4'h0;
163 
parameter       [3:0]    ch16_conf = 4'h0;
164 
parameter       [3:0]    ch17_conf = 4'h0;
165 
parameter       [3:0]    ch18_conf = 4'h0;
166 
parameter       [3:0]    ch19_conf = 4'h0;
167 
parameter       [3:0]    ch20_conf = 4'h0;
168 
parameter       [3:0]    ch21_conf = 4'h0;
169 
parameter       [3:0]    ch22_conf = 4'h0;
170 
parameter       [3:0]    ch23_conf = 4'h0;
171 
parameter       [3:0]    ch24_conf = 4'h0;
172 
parameter       [3:0]    ch25_conf = 4'h0;
173 
parameter       [3:0]    ch26_conf = 4'h0;
174 
parameter       [3:0]    ch27_conf = 4'h0;
175 
parameter       [3:0]    ch28_conf = 4'h0;
176 
parameter       [3:0]    ch29_conf = 4'h0;
177 
parameter       [3:0]    ch30_conf = 4'h0;
178 
 
179 
////////////////////////////////////////////////////////////////////
180 
//
181 
// Module IOs
182 
//
183 
 
184 5 rudi 
input           clk, rst;
185 
 
186 
// WISHBONE Access
187 
input   [7:0]    wb_rf_adr;
188 
input   [31:0]   wb_rf_din;
189 
output  [31:0]   wb_rf_dout;
190 
input           wb_rf_re;
191 
input           wb_rf_we;
192 
 
193 
// WISHBONE Interrupt outputs
194 
output          inta_o, intb_o;
195 
 
196 
// Channel Registers Inputs
197 
output  [31:0]   pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;
198 
output  [31:0]   pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;
199 
output  [31:0]   pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;
200 
output  [31:0]   pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;
201 
output  [31:0]   pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;
202 
output  [31:0]   pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;
203 
output  [31:0]   pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;
204 
output  [31:0]   pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;
205 
output  [31:0]   pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;
206 
output  [31:0]   pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;
207 
output  [31:0]   pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;
208 
output  [31:0]   pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;
209 
output  [31:0]   pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;
210 
output  [31:0]   pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;
211 
output  [31:0]   pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;
212 
output  [31:0]   pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;
213 
output  [31:0]   pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;
214 
output  [31:0]   pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;
215 
output  [31:0]   pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;
216 
output  [31:0]   pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;
217 
output  [31:0]   pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;
218 
output  [31:0]   pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;
219 
output  [31:0]   pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;
220 
output  [31:0]   pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;
221 
output  [31:0]   pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;
222 
output  [31:0]   pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;
223 
output  [31:0]   pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;
224 
output  [31:0]   pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;
225 
output  [31:0]   pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;
226 
output  [31:0]   pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;
227 
output  [31:0]   pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;
228 
 
229 
input   [4:0]    ch_sel;         // Write Back Channel Select
230 
input   [30:0]   ndnr;           // Next Descriptor No Request
231 
 
232 
// DMA Engine Abort
233 
output          dma_abort;
234 
 
235 
// DMA Engine Status
236 
output          pause_req;
237 
input           paused;
238 
input           dma_busy, dma_err, dma_done, dma_done_all;
239 
 
240 
// DMA Engine Reg File Update ctrl signals
241 
input   [31:0]   de_csr;
242 
input   [11:0]   de_txsz;
243 
input   [31:0]   de_adr0;
244 
input   [31:0]   de_adr1;
245 
input           de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
246 
input           de_fetch_descr;
247 
input   [30:0]   dma_rest;
248 
 
249 
////////////////////////////////////////////////////////////////////
250 
//
251 
// Local Wires and Registers
252 
//
253 
 
254 
reg     [31:0]   wb_rf_dout;
255 
reg             inta_o, intb_o;
256 
reg     [30:0]   int_maska_r, int_maskb_r;
257 
wire    [31:0]   int_maska, int_maskb;
258 
wire    [31:0]   int_srca, int_srcb;
259 
wire            int_maska_we, int_maskb_we;
260 
wire    [30:0]   ch_int;
261 
wire            csr_we;
262 
wire    [31:0]   csr;
263 
reg     [7:0]    csr_r;
264 
 
265 
wire    [30:0]   ch_stop;
266 
wire    [30:0]   ch_dis;
267 
 
268 
wire    [31:0]   ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;
269 
wire    [31:0]   ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;
270 
wire    [31:0]   ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;
271 
wire    [31:0]   ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;
272 
wire    [31:0]   ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;
273 
wire    [31:0]   ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;
274 
wire    [31:0]   ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;
275 
wire    [31:0]   ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;
276 
wire    [31:0]   ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;
277 
wire    [31:0]   ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;
278 
wire    [31:0]   ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;
279 
wire    [31:0]   ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;
280 
wire    [31:0]   ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;
281 
wire    [31:0]   ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;
282 
wire    [31:0]   ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;
283 
wire    [31:0]   ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;
284 
wire    [31:0]   ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;
285 
wire    [31:0]   ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;
286 
wire    [31:0]   ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;
287 
wire    [31:0]   ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;
288 
wire    [31:0]   ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;
289 
wire    [31:0]   ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;
290 
wire    [31:0]   ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;
291 
wire    [31:0]   ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;
292 
wire    [31:0]   ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;
293 
wire    [31:0]   ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;
294 
wire    [31:0]   ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;
295 
wire    [31:0]   ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;
296 
wire    [31:0]   ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;
297 
wire    [31:0]   ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;
298 
wire    [31:0]   ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;
299 
 
300 
wire    [31:0]   sw_pointer0, sw_pointer1, sw_pointer2, sw_pointer3;
301 
wire    [31:0]   sw_pointer4, sw_pointer5, sw_pointer6, sw_pointer7;
302 
wire    [31:0]   sw_pointer8, sw_pointer9, sw_pointer10, sw_pointer11;
303 
wire    [31:0]   sw_pointer12, sw_pointer13, sw_pointer14, sw_pointer15;
304 
wire    [31:0]   sw_pointer16, sw_pointer17, sw_pointer18, sw_pointer19;
305 
wire    [31:0]   sw_pointer20, sw_pointer21, sw_pointer22, sw_pointer23;
306 
wire    [31:0]   sw_pointer24, sw_pointer25, sw_pointer26, sw_pointer27;
307 
wire    [31:0]   sw_pointer28, sw_pointer29, sw_pointer30;
308 
 
309 
////////////////////////////////////////////////////////////////////
310 
//
311 
// Aliases
312 
//
313 
 
314 
assign int_maska = {1'h0, int_maska_r};
315 
assign int_maskb = {1'h0, int_maskb_r};
316 
assign csr = {31'h0, paused};
317 
 
318 
////////////////////////////////////////////////////////////////////
319 
//
320 
// Misc Logic
321 
//
322 
 
323 
assign dma_abort = |ch_stop;
324 
assign pause_req = csr_r[0];
325 
 
326 
////////////////////////////////////////////////////////////////////
327 
//
328 
// WISHBONE Register Read Logic
329 
//
330 
 
331 
always @(posedge clk)
332 
        case(wb_rf_adr)         // synopsys parallel_case full_case
333 
           8'h0:        wb_rf_dout <= #1 csr;
334 
           8'h1:        wb_rf_dout <= #1 int_maska;
335 
           8'h2:        wb_rf_dout <= #1 int_maskb;
336 
           8'h3:        wb_rf_dout <= #1 int_srca;
337 
           8'h4:        wb_rf_dout <= #1 int_srcb;
338 
 
339 
           8'h8:        wb_rf_dout <= #1 ch0_csr;
340 
           8'h9:        wb_rf_dout <= #1 ch0_txsz;
341 
           8'ha:        wb_rf_dout <= #1 ch0_adr0;
342 
           8'hb:        wb_rf_dout <= #1 ch0_am0;
343 
           8'hc:        wb_rf_dout <= #1 ch0_adr1;
344 
           8'hd:        wb_rf_dout <= #1 ch0_am1;
345 
           8'he:        wb_rf_dout <= #1 pointer0;
346 
           8'hf:        wb_rf_dout <= #1 sw_pointer0;
347 
 
348 10 rudi 
           8'h10:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_csr    : 32'h0;
349 
           8'h11:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_txsz   : 32'h0;
350 
           8'h12:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr0   : 32'h0;
351 
           8'h13:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_am0    : 32'h0;
352 
           8'h14:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr1   : 32'h0;
353 
           8'h15:       wb_rf_dout <= #1 ch1_conf[0] ? ch1_am1    : 32'h0;
354 
           8'h16:       wb_rf_dout <= #1 ch1_conf[0] ? pointer1   : 32'h0;
355 
           8'h17:       wb_rf_dout <= #1 ch1_conf[0] ? sw_pointer1   : 32'h0;
356 5 rudi 
 
357 10 rudi 
           8'h18:       wb_rf_dout <= #1 ch2_conf[0] ? ch2_csr    : 32'h0;
358 
           8'h19:       wb_rf_dout <= #1 ch2_conf[0] ? ch2_txsz   : 32'h0;
359 
           8'h1a:       wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr0   : 32'h0;
360 
           8'h1b:       wb_rf_dout <= #1 ch2_conf[0] ? ch2_am0    : 32'h0;
361 
           8'h1c:       wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr1   : 32'h0;
362 
           8'h1d:       wb_rf_dout <= #1 ch2_conf[0] ? ch2_am1    : 32'h0;
363 
           8'h1e:       wb_rf_dout <= #1 ch2_conf[0] ? pointer2   : 32'h0;
364 
           8'h1f:       wb_rf_dout <= #1 ch2_conf[0] ? sw_pointer2   : 32'h0;
365 5 rudi 
 
366 10 rudi 
           8'h20:       wb_rf_dout <= #1 ch3_conf[0] ? ch3_csr    : 32'h0;
367 
           8'h21:       wb_rf_dout <= #1 ch3_conf[0] ? ch3_txsz   : 32'h0;
368 
           8'h22:       wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr0   : 32'h0;
369 
           8'h23:       wb_rf_dout <= #1 ch3_conf[0] ? ch3_am0    : 32'h0;
370 
           8'h24:       wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr1   : 32'h0;
371 
           8'h25:       wb_rf_dout <= #1 ch3_conf[0] ? ch3_am1    : 32'h0;
372 
           8'h26:       wb_rf_dout <= #1 ch3_conf[0] ? pointer3   : 32'h0;
373 
           8'h27:       wb_rf_dout <= #1 ch3_conf[0] ? sw_pointer3   : 32'h0;
374 5 rudi 
 
375 10 rudi 
           8'h28:       wb_rf_dout <= #1 ch4_conf[0] ? ch4_csr    : 32'h0;
376 
           8'h29:       wb_rf_dout <= #1 ch4_conf[0] ? ch4_txsz   : 32'h0;
377 
           8'h2a:       wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr0   : 32'h0;
378 
           8'h2b:       wb_rf_dout <= #1 ch4_conf[0] ? ch4_am0    : 32'h0;
379 
           8'h2c:       wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr1   : 32'h0;
380 
           8'h2d:       wb_rf_dout <= #1 ch4_conf[0] ? ch4_am1    : 32'h0;
381 
           8'h2e:       wb_rf_dout <= #1 ch4_conf[0] ? pointer4   : 32'h0;
382 
           8'h2f:       wb_rf_dout <= #1 ch4_conf[0] ? sw_pointer4   : 32'h0;
383 5 rudi 
 
384 10 rudi 
           8'h30:       wb_rf_dout <= #1 ch5_conf[0] ? ch5_csr    : 32'h0;
385 
           8'h31:       wb_rf_dout <= #1 ch5_conf[0] ? ch5_txsz   : 32'h0;
386 
           8'h32:       wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr0   : 32'h0;
387 
           8'h33:       wb_rf_dout <= #1 ch5_conf[0] ? ch5_am0    : 32'h0;
388 
           8'h34:       wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr1   : 32'h0;
389 
           8'h35:       wb_rf_dout <= #1 ch5_conf[0] ? ch5_am1    : 32'h0;
390 
           8'h36:       wb_rf_dout <= #1 ch5_conf[0] ? pointer5   : 32'h0;
391 
           8'h37:       wb_rf_dout <= #1 ch5_conf[0] ? sw_pointer5   : 32'h0;
392 5 rudi 
 
393 10 rudi 
           8'h38:       wb_rf_dout <= #1 ch6_conf[0] ? ch6_csr    : 32'h0;
394 
           8'h39:       wb_rf_dout <= #1 ch6_conf[0] ? ch6_txsz   : 32'h0;
395 
           8'h3a:       wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr0   : 32'h0;
396 
           8'h3b:       wb_rf_dout <= #1 ch6_conf[0] ? ch6_am0    : 32'h0;
397 
           8'h3c:       wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr1   : 32'h0;
398 
           8'h3d:       wb_rf_dout <= #1 ch6_conf[0] ? ch6_am1    : 32'h0;
399 
           8'h3e:       wb_rf_dout <= #1 ch6_conf[0] ? pointer6   : 32'h0;
400 
           8'h3f:       wb_rf_dout <= #1 ch6_conf[0] ? sw_pointer6   : 32'h0;
401 5 rudi 
 
402 10 rudi 
           8'h40:       wb_rf_dout <= #1 ch7_conf[0] ? ch7_csr    : 32'h0;
403 
           8'h41:       wb_rf_dout <= #1 ch7_conf[0] ? ch7_txsz   : 32'h0;
404 
           8'h42:       wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr0   : 32'h0;
405 
           8'h43:       wb_rf_dout <= #1 ch7_conf[0] ? ch7_am0    : 32'h0;
406 
           8'h44:       wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr1   : 32'h0;
407 
           8'h45:       wb_rf_dout <= #1 ch7_conf[0] ? ch7_am1    : 32'h0;
408 
           8'h46:       wb_rf_dout <= #1 ch7_conf[0] ? pointer7   : 32'h0;
409 
           8'h47:       wb_rf_dout <= #1 ch7_conf[0] ? sw_pointer7   : 32'h0;
410 5 rudi 
 
411 10 rudi 
           8'h48:       wb_rf_dout <= #1 ch8_conf[0] ? ch8_csr    : 32'h0;
412 
           8'h49:       wb_rf_dout <= #1 ch8_conf[0] ? ch8_txsz   : 32'h0;
413 
           8'h4a:       wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr0   : 32'h0;
414 
           8'h4b:       wb_rf_dout <= #1 ch8_conf[0] ? ch8_am0    : 32'h0;
415 
           8'h4c:       wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr1   : 32'h0;
416 
           8'h4d:       wb_rf_dout <= #1 ch8_conf[0] ? ch8_am1    : 32'h0;
417 
           8'h4e:       wb_rf_dout <= #1 ch8_conf[0] ? pointer8   : 32'h0;
418 
           8'h4f:       wb_rf_dout <= #1 ch8_conf[0] ? sw_pointer8   : 32'h0;
419 5 rudi 
 
420 10 rudi 
           8'h50:       wb_rf_dout <= #1 ch9_conf[0] ? ch9_csr    : 32'h0;
421 
           8'h51:       wb_rf_dout <= #1 ch9_conf[0] ? ch9_txsz   : 32'h0;
422 
           8'h52:       wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr0   : 32'h0;
423 
           8'h53:       wb_rf_dout <= #1 ch9_conf[0] ? ch9_am0    : 32'h0;
424 
           8'h54:       wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr1   : 32'h0;
425 
           8'h55:       wb_rf_dout <= #1 ch9_conf[0] ? ch9_am1    : 32'h0;
426 
           8'h56:       wb_rf_dout <= #1 ch9_conf[0] ? pointer9   : 32'h0;
427 
           8'h57:       wb_rf_dout <= #1 ch9_conf[0] ? sw_pointer9   : 32'h0;
428 5 rudi 
 
429 10 rudi 
           8'h58:       wb_rf_dout <= #1 ch10_conf[0] ? ch10_csr    : 32'h0;
430 
           8'h59:       wb_rf_dout <= #1 ch10_conf[0] ? ch10_txsz   : 32'h0;
431 
           8'h5a:       wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr0   : 32'h0;
432 
           8'h5b:       wb_rf_dout <= #1 ch10_conf[0] ? ch10_am0    : 32'h0;
433 
           8'h5c:       wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr1   : 32'h0;
434 
           8'h5d:       wb_rf_dout <= #1 ch10_conf[0] ? ch10_am1    : 32'h0;
435 
           8'h5e:       wb_rf_dout <= #1 ch10_conf[0] ? pointer10   : 32'h0;
436 
           8'h5f:       wb_rf_dout <= #1 ch10_conf[0] ? sw_pointer10   : 32'h0;
437 5 rudi 
 
438 10 rudi 
           8'h60:       wb_rf_dout <= #1 ch11_conf[0] ? ch11_csr    : 32'h0;
439 
           8'h61:       wb_rf_dout <= #1 ch11_conf[0] ? ch11_txsz   : 32'h0;
440 
           8'h62:       wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr0   : 32'h0;
441 
           8'h63:       wb_rf_dout <= #1 ch11_conf[0] ? ch11_am0    : 32'h0;
442 
           8'h64:       wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr1   : 32'h0;
443 
           8'h65:       wb_rf_dout <= #1 ch11_conf[0] ? ch11_am1    : 32'h0;
444 
           8'h66:       wb_rf_dout <= #1 ch11_conf[0] ? pointer11   : 32'h0;
445 
           8'h67:       wb_rf_dout <= #1 ch11_conf[0] ? sw_pointer11   : 32'h0;
446 5 rudi 
 
447 10 rudi 
           8'h68:       wb_rf_dout <= #1 ch12_conf[0] ? ch12_csr    : 32'h0;
448 
           8'h69:       wb_rf_dout <= #1 ch12_conf[0] ? ch12_txsz   : 32'h0;
449 
           8'h6a:       wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr0   : 32'h0;
450 
           8'h6b:       wb_rf_dout <= #1 ch12_conf[0] ? ch12_am0    : 32'h0;
451 
           8'h6c:       wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr1   : 32'h0;
452 
           8'h6d:       wb_rf_dout <= #1 ch12_conf[0] ? ch12_am1    : 32'h0;
453 
           8'h6e:       wb_rf_dout <= #1 ch12_conf[0] ? pointer12   : 32'h0;
454 
           8'h6f:       wb_rf_dout <= #1 ch12_conf[0] ? sw_pointer12   : 32'h0;
455 5 rudi 
 
456 10 rudi 
           8'h70:       wb_rf_dout <= #1 ch13_conf[0] ? ch13_csr    : 32'h0;
457 
           8'h71:       wb_rf_dout <= #1 ch13_conf[0] ? ch13_txsz   : 32'h0;
458 
           8'h72:       wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr0   : 32'h0;
459 
           8'h73:       wb_rf_dout <= #1 ch13_conf[0] ? ch13_am0    : 32'h0;
460 
           8'h74:       wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr1   : 32'h0;
461 
           8'h75:       wb_rf_dout <= #1 ch13_conf[0] ? ch13_am1    : 32'h0;
462 
           8'h76:       wb_rf_dout <= #1 ch13_conf[0] ? pointer13   : 32'h0;
463 
           8'h77:       wb_rf_dout <= #1 ch13_conf[0] ? sw_pointer13   : 32'h0;
464 5 rudi 
 
465 10 rudi 
           8'h78:       wb_rf_dout <= #1 ch14_conf[0] ? ch14_csr    : 32'h0;
466 
           8'h79:       wb_rf_dout <= #1 ch14_conf[0] ? ch14_txsz   : 32'h0;
467 
           8'h7a:       wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr0   : 32'h0;
468 
           8'h7b:       wb_rf_dout <= #1 ch14_conf[0] ? ch14_am0    : 32'h0;
469 
           8'h7c:       wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr1   : 32'h0;
470 
           8'h7d:       wb_rf_dout <= #1 ch14_conf[0] ? ch14_am1    : 32'h0;
471 
           8'h7e:       wb_rf_dout <= #1 ch14_conf[0] ? pointer14   : 32'h0;
472 
           8'h7f:       wb_rf_dout <= #1 ch14_conf[0] ? sw_pointer14   : 32'h0;
473 5 rudi 
 
474 10 rudi 
           8'h80:       wb_rf_dout <= #1 ch15_conf[0] ? ch15_csr    : 32'h0;
475 
           8'h81:       wb_rf_dout <= #1 ch15_conf[0] ? ch15_txsz   : 32'h0;
476 
           8'h82:       wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr0   : 32'h0;
477 
           8'h83:       wb_rf_dout <= #1 ch15_conf[0] ? ch15_am0    : 32'h0;
478 
           8'h84:       wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr1   : 32'h0;
479 
           8'h85:       wb_rf_dout <= #1 ch15_conf[0] ? ch15_am1    : 32'h0;
480 
           8'h86:       wb_rf_dout <= #1 ch15_conf[0] ? pointer15   : 32'h0;
481 
           8'h87:       wb_rf_dout <= #1 ch15_conf[0] ? sw_pointer15   : 32'h0;
482 5 rudi 
 
483 10 rudi 
           8'h88:       wb_rf_dout <= #1 ch16_conf[0] ? ch16_csr    : 32'h0;
484 
           8'h89:       wb_rf_dout <= #1 ch16_conf[0] ? ch16_txsz   : 32'h0;
485 
           8'h8a:       wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr0   : 32'h0;
486 
           8'h8b:       wb_rf_dout <= #1 ch16_conf[0] ? ch16_am0    : 32'h0;
487 
           8'h8c:       wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr1   : 32'h0;
488 
           8'h8d:       wb_rf_dout <= #1 ch16_conf[0] ? ch16_am1    : 32'h0;
489 
           8'h8e:       wb_rf_dout <= #1 ch16_conf[0] ? pointer16   : 32'h0;
490 
           8'h8f:       wb_rf_dout <= #1 ch16_conf[0] ? sw_pointer16   : 32'h0;
491 5 rudi 
 
492 10 rudi 
           8'h90:       wb_rf_dout <= #1 ch17_conf[0] ? ch17_csr    : 32'h0;
493 
           8'h91:       wb_rf_dout <= #1 ch17_conf[0] ? ch17_txsz   : 32'h0;
494 
           8'h92:       wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr0   : 32'h0;
495 
           8'h93:       wb_rf_dout <= #1 ch17_conf[0] ? ch17_am0    : 32'h0;
496 
           8'h94:       wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr1   : 32'h0;
497 
           8'h95:       wb_rf_dout <= #1 ch17_conf[0] ? ch17_am1    : 32'h0;
498 
           8'h96:       wb_rf_dout <= #1 ch17_conf[0] ? pointer17   : 32'h0;
499 
           8'h97:       wb_rf_dout <= #1 ch17_conf[0] ? sw_pointer17   : 32'h0;
500 5 rudi 
 
501 10 rudi 
           8'h98:       wb_rf_dout <= #1 ch18_conf[0] ? ch18_csr    : 32'h0;
502 
           8'h99:       wb_rf_dout <= #1 ch18_conf[0] ? ch18_txsz   : 32'h0;
503 
           8'h9a:       wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr0   : 32'h0;
504 
           8'h9b:       wb_rf_dout <= #1 ch18_conf[0] ? ch18_am0    : 32'h0;
505 
           8'h9c:       wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr1   : 32'h0;
506 
           8'h9d:       wb_rf_dout <= #1 ch18_conf[0] ? ch18_am1    : 32'h0;
507 
           8'h9e:       wb_rf_dout <= #1 ch18_conf[0] ? pointer18   : 32'h0;
508 
           8'h9f:       wb_rf_dout <= #1 ch18_conf[0] ? sw_pointer18   : 32'h0;
509 5 rudi 
 
510 10 rudi 
           8'ha0:       wb_rf_dout <= #1 ch19_conf[0] ? ch19_csr    : 32'h0;
511 
           8'ha1:       wb_rf_dout <= #1 ch19_conf[0] ? ch19_txsz   : 32'h0;
512 
           8'ha2:       wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr0   : 32'h0;
513 
           8'ha3:       wb_rf_dout <= #1 ch19_conf[0] ? ch19_am0    : 32'h0;
514 
           8'ha4:       wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr1   : 32'h0;
515 
           8'ha5:       wb_rf_dout <= #1 ch19_conf[0] ? ch19_am1    : 32'h0;
516 
           8'ha6:       wb_rf_dout <= #1 ch19_conf[0] ? pointer19   : 32'h0;
517 
           8'ha7:       wb_rf_dout <= #1 ch19_conf[0] ? sw_pointer19   : 32'h0;
518 5 rudi 
 
519 10 rudi 
           8'ha8:       wb_rf_dout <= #1 ch20_conf[0] ? ch20_csr    : 32'h0;
520 
           8'ha9:       wb_rf_dout <= #1 ch20_conf[0] ? ch20_txsz   : 32'h0;
521 
           8'haa:       wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr0   : 32'h0;
522 
           8'hab:       wb_rf_dout <= #1 ch20_conf[0] ? ch20_am0    : 32'h0;
523 
           8'hac:       wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr1   : 32'h0;
524 
           8'had:       wb_rf_dout <= #1 ch20_conf[0] ? ch20_am1    : 32'h0;
525 
           8'hae:       wb_rf_dout <= #1 ch20_conf[0] ? pointer20   : 32'h0;
526 
           8'haf:       wb_rf_dout <= #1 ch20_conf[0] ? sw_pointer20   : 32'h0;
527 5 rudi 
 
528 10 rudi 
           8'hb0:       wb_rf_dout <= #1 ch21_conf[0] ? ch21_csr    : 32'h0;
529 
           8'hb1:       wb_rf_dout <= #1 ch21_conf[0] ? ch21_txsz   : 32'h0;
530 
           8'hb2:       wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr0   : 32'h0;
531 
           8'hb3:       wb_rf_dout <= #1 ch21_conf[0] ? ch21_am0    : 32'h0;
532 
           8'hb4:       wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr1   : 32'h0;
533 
           8'hb5:       wb_rf_dout <= #1 ch21_conf[0] ? ch21_am1    : 32'h0;
534 
           8'hb6:       wb_rf_dout <= #1 ch21_conf[0] ? pointer21   : 32'h0;
535 
           8'hb7:       wb_rf_dout <= #1 ch21_conf[0] ? sw_pointer21   : 32'h0;
536 5 rudi 
 
537 10 rudi 
           8'hb8:       wb_rf_dout <= #1 ch22_conf[0] ? ch22_csr    : 32'h0;
538 
           8'hb9:       wb_rf_dout <= #1 ch22_conf[0] ? ch22_txsz   : 32'h0;
539 
           8'hba:       wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr0   : 32'h0;
540 
           8'hbb:       wb_rf_dout <= #1 ch22_conf[0] ? ch22_am0    : 32'h0;
541 
           8'hbc:       wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr1   : 32'h0;
542 
           8'hbd:       wb_rf_dout <= #1 ch22_conf[0] ? ch22_am1    : 32'h0;
543 
           8'hbe:       wb_rf_dout <= #1 ch22_conf[0] ? pointer22   : 32'h0;
544 
           8'hbf:       wb_rf_dout <= #1 ch22_conf[0] ? sw_pointer22   : 32'h0;
545 5 rudi 
 
546 10 rudi 
           8'hc0:       wb_rf_dout <= #1 ch23_conf[0] ? ch23_csr    : 32'h0;
547 
           8'hc1:       wb_rf_dout <= #1 ch23_conf[0] ? ch23_txsz   : 32'h0;
548 
           8'hc2:       wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr0   : 32'h0;
549 
           8'hc3:       wb_rf_dout <= #1 ch23_conf[0] ? ch23_am0    : 32'h0;
550 
           8'hc4:       wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr1   : 32'h0;
551 
           8'hc5:       wb_rf_dout <= #1 ch23_conf[0] ? ch23_am1    : 32'h0;
552 
           8'hc6:       wb_rf_dout <= #1 ch23_conf[0] ? pointer23   : 32'h0;
553 
           8'hc7:       wb_rf_dout <= #1 ch23_conf[0] ? sw_pointer23   : 32'h0;
554 5 rudi 
 
555 10 rudi 
           8'hc8:       wb_rf_dout <= #1 ch24_conf[0] ? ch24_csr    : 32'h0;
556 
           8'hc9:       wb_rf_dout <= #1 ch24_conf[0] ? ch24_txsz   : 32'h0;
557 
           8'hca:       wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr0   : 32'h0;
558 
           8'hcb:       wb_rf_dout <= #1 ch24_conf[0] ? ch24_am0    : 32'h0;
559 
           8'hcc:       wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr1   : 32'h0;
560 
           8'hcd:       wb_rf_dout <= #1 ch24_conf[0] ? ch24_am1    : 32'h0;
561 
           8'hce:       wb_rf_dout <= #1 ch24_conf[0] ? pointer24   : 32'h0;
562 
           8'hcf:       wb_rf_dout <= #1 ch24_conf[0] ? sw_pointer24   : 32'h0;
563 5 rudi 
 
564 10 rudi 
           8'hd0:       wb_rf_dout <= #1 ch25_conf[0] ? ch25_csr    : 32'h0;
565 
           8'hd1:       wb_rf_dout <= #1 ch25_conf[0] ? ch25_txsz   : 32'h0;
566 
           8'hd2:       wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr0   : 32'h0;
567 
           8'hd3:       wb_rf_dout <= #1 ch25_conf[0] ? ch25_am0    : 32'h0;
568 
           8'hd4:       wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr1   : 32'h0;
569 
           8'hd5:       wb_rf_dout <= #1 ch25_conf[0] ? ch25_am1    : 32'h0;
570 
           8'hd6:       wb_rf_dout <= #1 ch25_conf[0] ? pointer25   : 32'h0;
571 
           8'hd7:       wb_rf_dout <= #1 ch25_conf[0] ? sw_pointer25   : 32'h0;
572 5 rudi 
 
573 10 rudi 
           8'hd8:       wb_rf_dout <= #1 ch26_conf[0] ? ch26_csr    : 32'h0;
574 
           8'hd9:       wb_rf_dout <= #1 ch26_conf[0] ? ch26_txsz   : 32'h0;
575 
           8'hda:       wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr0   : 32'h0;
576 
           8'hdb:       wb_rf_dout <= #1 ch26_conf[0] ? ch26_am0    : 32'h0;
577 
           8'hdc:       wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr1   : 32'h0;
578 
           8'hdd:       wb_rf_dout <= #1 ch26_conf[0] ? ch26_am1    : 32'h0;
579 
           8'hde:       wb_rf_dout <= #1 ch26_conf[0] ? pointer26   : 32'h0;
580 
           8'hdf:       wb_rf_dout <= #1 ch26_conf[0] ? sw_pointer26   : 32'h0;
581 5 rudi 
 
582 10 rudi 
           8'he0:       wb_rf_dout <= #1 ch27_conf[0] ? ch27_csr    : 32'h0;
583 
           8'he1:       wb_rf_dout <= #1 ch27_conf[0] ? ch27_txsz   : 32'h0;
584 
           8'he2:       wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr0   : 32'h0;
585 
           8'he3:       wb_rf_dout <= #1 ch27_conf[0] ? ch27_am0    : 32'h0;
586 
           8'he4:       wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr1   : 32'h0;
587 
           8'he5:       wb_rf_dout <= #1 ch27_conf[0] ? ch27_am1    : 32'h0;
588 
           8'he6:       wb_rf_dout <= #1 ch27_conf[0] ? pointer27   : 32'h0;
589 
           8'he7:       wb_rf_dout <= #1 ch27_conf[0] ? sw_pointer27   : 32'h0;
590 5 rudi 
 
591 10 rudi 
           8'he8:       wb_rf_dout <= #1 ch28_conf[0] ? ch28_csr    : 32'h0;
592 
           8'he9:       wb_rf_dout <= #1 ch28_conf[0] ? ch28_txsz   : 32'h0;
593 
           8'hea:       wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr0   : 32'h0;
594 
           8'heb:       wb_rf_dout <= #1 ch28_conf[0] ? ch28_am0    : 32'h0;
595 
           8'hec:       wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr1   : 32'h0;
596 
           8'hed:       wb_rf_dout <= #1 ch28_conf[0] ? ch28_am1    : 32'h0;
597 
           8'hee:       wb_rf_dout <= #1 ch28_conf[0] ? pointer28   : 32'h0;
598 
           8'hef:       wb_rf_dout <= #1 ch28_conf[0] ? sw_pointer28   : 32'h0;
599 5 rudi 
 
600 10 rudi 
           8'hf0:       wb_rf_dout <= #1 ch29_conf[0] ? ch29_csr    : 32'h0;
601 
           8'hf1:       wb_rf_dout <= #1 ch29_conf[0] ? ch29_txsz   : 32'h0;
602 
           8'hf2:       wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr0   : 32'h0;
603 
           8'hf3:       wb_rf_dout <= #1 ch29_conf[0] ? ch29_am0    : 32'h0;
604 
           8'hf4:       wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr1   : 32'h0;
605 
           8'hf5:       wb_rf_dout <= #1 ch29_conf[0] ? ch29_am1    : 32'h0;
606 
           8'hf6:       wb_rf_dout <= #1 ch29_conf[0] ? pointer29   : 32'h0;
607 
           8'hf7:       wb_rf_dout <= #1 ch29_conf[0] ? sw_pointer29   : 32'h0;
608 5 rudi 
 
609 10 rudi 
           8'hf8:       wb_rf_dout <= #1 ch30_conf[0] ? ch30_csr    : 32'h0;
610 
           8'hf9:       wb_rf_dout <= #1 ch30_conf[0] ? ch30_txsz   : 32'h0;
611 
           8'hfa:       wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr0   : 32'h0;
612 
           8'hfb:       wb_rf_dout <= #1 ch30_conf[0] ? ch30_am0    : 32'h0;
613 
           8'hfc:       wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr1   : 32'h0;
614 
           8'hfd:       wb_rf_dout <= #1 ch30_conf[0] ? ch30_am1    : 32'h0;
615 
           8'hfe:       wb_rf_dout <= #1 ch30_conf[0] ? pointer30   : 32'h0;
616 
           8'hff:       wb_rf_dout <= #1 ch30_conf[0] ? sw_pointer30   : 32'h0;
617 5 rudi 
 
618 
        endcase
619 
 
620 
 
621 
////////////////////////////////////////////////////////////////////
622 
//
623 
// WISHBONE Register Write Logic
624 
// And DMA Engine register Update Logic
625 
//
626 
 
627 
// Global Registers
628 
assign csr_we           = wb_rf_we & (wb_rf_adr == 8'h0);
629 
assign int_maska_we     = wb_rf_we & (wb_rf_adr == 8'h1);
630 
assign int_maskb_we     = wb_rf_we & (wb_rf_adr == 8'h2);
631 
 
632 
// ---------------------------------------------------
633 
 
634 
always @(posedge clk or negedge rst)
635 8 rudi 
        if(!rst)                csr_r <= #1 8'h0;
636 5 rudi 
        else
637 
        if(csr_we)              csr_r <= #1 wb_rf_din[7:0];
638 
 
639 
// ---------------------------------------------------
640 
// INT_MASK
641 
always @(posedge clk or negedge rst)
642 8 rudi 
        if(!rst)                int_maska_r <= #1 31'h0;
643 5 rudi 
        else
644 
        if(int_maska_we)        int_maska_r <= #1 wb_rf_din[30:0];
645 
 
646 
always @(posedge clk or negedge rst)
647 8 rudi 
        if(!rst)                int_maskb_r <= #1 31'h0;
648 5 rudi 
        else
649 
        if(int_maskb_we)        int_maskb_r <= #1 wb_rf_din[30:0];
650 
 
651 
////////////////////////////////////////////////////////////////////
652 
//
653 
// Interrupts
654 
//
655 
 
656 
assign int_srca = {1'b0, (int_maska_r & ch_int) };
657 
assign int_srcb = {1'b0, (int_maskb_r & ch_int) };
658 
 
659 
// Interrupt Outputs
660 
always @(posedge clk)
661 
        inta_o <= #1 |int_srca;
662 
 
663 
always @(posedge clk)
664 
        intb_o <= #1 |int_srcb;
665 
 
666 
////////////////////////////////////////////////////////////////////
667 
//
668 
// Channel Register File
669 
//
670 
 
671 10 rudi 
// chXX_conf = { CBUF, ED, ARS, EN }
672 
 
673 
wb_dma_ch_rf #(0, ch0_conf[0], ch0_conf[1], ch0_conf[2], ch0_conf[3]) u0(
674 5 rudi 
                .clk(           clk             ),
675 
                .rst(           rst             ),
676 
                .pointer(       pointer0        ),
677 
                .pointer_s(     pointer0_s      ),
678 
                .ch_csr(        ch0_csr         ),
679 
                .ch_txsz(       ch0_txsz        ),
680 
                .ch_adr0(       ch0_adr0        ),
681 
                .ch_adr1(       ch0_adr1        ),
682 
                .ch_am0(        ch0_am0         ),
683 
                .ch_am1(        ch0_am1         ),
684 
                .sw_pointer(    sw_pointer0     ),
685 
                .ch_stop(       ch_stop[0]       ),
686 
                .ch_dis(        ch_dis[0]        ),
687 
                .int(           ch_int[0]        ),
688 
                .wb_rf_din(     wb_rf_din       ),
689 
                .wb_rf_adr(     wb_rf_adr       ),
690 
                .wb_rf_we(      wb_rf_we        ),
691 
                .wb_rf_re(      wb_rf_re        ),
692 
                .ch_sel(        ch_sel          ),
693 
                .ndnr(          ndnr[0]          ),
694 
                .dma_busy(      dma_busy        ),
695 
                .dma_err(       dma_err         ),
696 
                .dma_done(      dma_done        ),
697 
                .dma_done_all(  dma_done_all    ),
698 
                .de_csr(        de_csr          ),
699 
                .de_txsz(       de_txsz         ),
700 
                .de_adr0(       de_adr0         ),
701 
                .de_adr1(       de_adr1         ),
702 
                .de_csr_we(     de_csr_we       ),
703 
                .de_txsz_we(    de_txsz_we      ),
704 
                .de_adr0_we(    de_adr0_we      ),
705 
                .de_adr1_we(    de_adr1_we      ),
706 
                .de_fetch_descr(de_fetch_descr  ),
707 
                .dma_rest(      dma_rest[0]      ),
708 
                .ptr_set(       ptr_set         )
709 
                );
710 
 
711 10 rudi 
wb_dma_ch_rf #(1, ch1_conf[0], ch1_conf[1], ch1_conf[2], ch1_conf[3]) u1(
712 5 rudi 
                .clk(           clk             ),
713 
                .rst(           rst             ),
714 
                .pointer(       pointer1        ),
715 
                .pointer_s(     pointer1_s      ),
716 
                .ch_csr(        ch1_csr         ),
717 
                .ch_txsz(       ch1_txsz        ),
718 
                .ch_adr0(       ch1_adr0        ),
719 
                .ch_adr1(       ch1_adr1        ),
720 
                .ch_am0(        ch1_am0         ),
721 
                .ch_am1(        ch1_am1         ),
722 
                .sw_pointer(    sw_pointer1     ),
723 
                .ch_stop(       ch_stop[1]      ),
724 
                .ch_dis(        ch_dis[1]       ),
725 
                .int(           ch_int[1]       ),
726 
                .wb_rf_din(     wb_rf_din       ),
727 
                .wb_rf_adr(     wb_rf_adr       ),
728 
                .wb_rf_we(      wb_rf_we        ),
729 
                .wb_rf_re(      wb_rf_re        ),
730 
                .ch_sel(        ch_sel          ),
731 
                .ndnr(          ndnr[1]         ),
732 
                .dma_busy(      dma_busy        ),
733 
                .dma_err(       dma_err         ),
734 
                .dma_done(      dma_done        ),
735 
                .dma_done_all(  dma_done_all    ),
736 
                .de_csr(        de_csr          ),
737 
                .de_txsz(       de_txsz         ),
738 
                .de_adr0(       de_adr0         ),
739 
                .de_adr1(       de_adr1         ),
740 
                .de_csr_we(     de_csr_we       ),
741 
                .de_txsz_we(    de_txsz_we      ),
742 
                .de_adr0_we(    de_adr0_we      ),
743 
                .de_adr1_we(    de_adr1_we      ),
744 
                .de_fetch_descr(de_fetch_descr  ),
745 
                .dma_rest(      dma_rest[1]     ),
746 
                .ptr_set(       ptr_set         )
747 
                );
748 
 
749 10 rudi 
wb_dma_ch_rf #(2, ch2_conf[0], ch2_conf[1], ch2_conf[2], ch2_conf[3]) u2(
750 5 rudi 
                .clk(           clk             ),
751 
                .rst(           rst             ),
752 
                .pointer(       pointer2        ),
753 
                .pointer_s(     pointer2_s      ),
754 
                .ch_csr(        ch2_csr         ),
755 
                .ch_txsz(       ch2_txsz        ),
756 
                .ch_adr0(       ch2_adr0        ),
757 
                .ch_adr1(       ch2_adr1        ),
758 
                .ch_am0(        ch2_am0         ),
759 
                .ch_am1(        ch2_am1         ),
760 
                .sw_pointer(    sw_pointer2     ),
761 
                .ch_stop(       ch_stop[2]      ),
762 
                .ch_dis(        ch_dis[2]       ),
763 
                .int(           ch_int[2]       ),
764 
                .wb_rf_din(     wb_rf_din       ),
765 
                .wb_rf_adr(     wb_rf_adr       ),
766 
                .wb_rf_we(      wb_rf_we        ),
767 
                .wb_rf_re(      wb_rf_re        ),
768 
                .ch_sel(        ch_sel          ),
769 
                .ndnr(          ndnr[2]         ),
770 
                .dma_busy(      dma_busy        ),
771 
                .dma_err(       dma_err         ),
772 
                .dma_done(      dma_done        ),
773 
                .dma_done_all(  dma_done_all    ),
774 
                .de_csr(        de_csr          ),
775 
                .de_txsz(       de_txsz         ),
776 
                .de_adr0(       de_adr0         ),
777 
                .de_adr1(       de_adr1         ),
778 
                .de_csr_we(     de_csr_we       ),
779 
                .de_txsz_we(    de_txsz_we      ),
780 
                .de_adr0_we(    de_adr0_we      ),
781 
                .de_adr1_we(    de_adr1_we      ),
782 
                .de_fetch_descr(de_fetch_descr  ),
783 
                .dma_rest(      dma_rest[2]     ),
784 
                .ptr_set(       ptr_set         )
785 
                );
786 
 
787 10 rudi 
wb_dma_ch_rf #(3, ch3_conf[0], ch3_conf[1], ch3_conf[2], ch3_conf[3]) u3(
788 5 rudi 
                .clk(           clk             ),
789 
                .rst(           rst             ),
790 
                .pointer(       pointer3        ),
791 
                .pointer_s(     pointer3_s      ),
792 
                .ch_csr(        ch3_csr         ),
793 
                .ch_txsz(       ch3_txsz        ),
794 
                .ch_adr0(       ch3_adr0        ),
795 
                .ch_adr1(       ch3_adr1        ),
796 
                .ch_am0(        ch3_am0         ),
797 
                .ch_am1(        ch3_am1         ),
798 
                .sw_pointer(    sw_pointer3     ),
799 
                .ch_stop(       ch_stop[3]      ),
800 
                .ch_dis(        ch_dis[3]       ),
801 
                .int(           ch_int[3]       ),
802 
                .wb_rf_din(     wb_rf_din       ),
803 
                .wb_rf_adr(     wb_rf_adr       ),
804 
                .wb_rf_we(      wb_rf_we        ),
805 
                .wb_rf_re(      wb_rf_re        ),
806 
                .ch_sel(        ch_sel          ),
807 
                .ndnr(          ndnr[3]         ),
808 
                .dma_busy(      dma_busy        ),
809 
                .dma_err(       dma_err         ),
810 
                .dma_done(      dma_done        ),
811 
                .dma_done_all(  dma_done_all    ),
812 
                .de_csr(        de_csr          ),
813 
                .de_txsz(       de_txsz         ),
814 
                .de_adr0(       de_adr0         ),
815 
                .de_adr1(       de_adr1         ),
816 
                .de_csr_we(     de_csr_we       ),
817 
                .de_txsz_we(    de_txsz_we      ),
818 
                .de_adr0_we(    de_adr0_we      ),
819 
                .de_adr1_we(    de_adr1_we      ),
820 
                .de_fetch_descr(de_fetch_descr  ),
821 
                .dma_rest(      dma_rest[3]     ),
822 
                .ptr_set(       ptr_set         )
823 
                );
824 
 
825 10 rudi 
wb_dma_ch_rf #(4, ch4_conf[0], ch4_conf[1], ch4_conf[2], ch4_conf[3]) u4(
826 5 rudi 
                .clk(           clk             ),
827 
                .rst(           rst             ),
828 
                .pointer(       pointer4        ),
829 
                .pointer_s(     pointer4_s      ),
830 
                .ch_csr(        ch4_csr         ),
831 
                .ch_txsz(       ch4_txsz        ),
832 
                .ch_adr0(       ch4_adr0        ),
833 
                .ch_adr1(       ch4_adr1        ),
834 
                .ch_am0(        ch4_am0         ),
835 
                .ch_am1(        ch4_am1         ),
836 
                .sw_pointer(    sw_pointer4     ),
837 
                .ch_stop(       ch_stop[4]      ),
838 
                .ch_dis(        ch_dis[4]       ),
839 
                .int(           ch_int[4]       ),
840 
                .wb_rf_din(     wb_rf_din       ),
841 
                .wb_rf_adr(     wb_rf_adr       ),
842 
                .wb_rf_we(      wb_rf_we        ),
843 
                .wb_rf_re(      wb_rf_re        ),
844 
                .ch_sel(        ch_sel          ),
845 
                .ndnr(          ndnr[4]         ),
846 
                .dma_busy(      dma_busy        ),
847 
                .dma_err(       dma_err         ),
848 
                .dma_done(      dma_done        ),
849 
                .dma_done_all(  dma_done_all    ),
850 
                .de_csr(        de_csr          ),
851 
                .de_txsz(       de_txsz         ),
852 
                .de_adr0(       de_adr0         ),
853 
                .de_adr1(       de_adr1         ),
854 
                .de_csr_we(     de_csr_we       ),
855 
                .de_txsz_we(    de_txsz_we      ),
856 
                .de_adr0_we(    de_adr0_we      ),
857 
                .de_adr1_we(    de_adr1_we      ),
858 
                .de_fetch_descr(de_fetch_descr  ),
859 
                .dma_rest(      dma_rest[4]     ),
860 
                .ptr_set(       ptr_set         )
861 
                );
862 
 
863 10 rudi 
wb_dma_ch_rf #(5, ch5_conf[0], ch5_conf[1], ch5_conf[2], ch5_conf[3]) u5(
864 5 rudi 
                .clk(           clk             ),
865 
                .rst(           rst             ),
866 
                .pointer(       pointer5        ),
867 
                .pointer_s(     pointer5_s      ),
868 
                .ch_csr(        ch5_csr         ),
869 
                .ch_txsz(       ch5_txsz        ),
870 
                .ch_adr0(       ch5_adr0        ),
871 
                .ch_adr1(       ch5_adr1        ),
872 
                .ch_am0(        ch5_am0         ),
873 
                .ch_am1(        ch5_am1         ),
874 
                .sw_pointer(    sw_pointer5     ),
875 
                .ch_stop(       ch_stop[5]      ),
876 
                .ch_dis(        ch_dis[5]       ),
877 
                .int(           ch_int[5]       ),
878 
                .wb_rf_din(     wb_rf_din       ),
879 
                .wb_rf_adr(     wb_rf_adr       ),
880 
                .wb_rf_we(      wb_rf_we        ),
881 
                .wb_rf_re(      wb_rf_re        ),
882 
                .ch_sel(        ch_sel          ),
883 
                .ndnr(          ndnr[5]         ),
884 
                .dma_busy(      dma_busy        ),
885 
                .dma_err(       dma_err         ),
886 
                .dma_done(      dma_done        ),
887 
                .dma_done_all(  dma_done_all    ),
888 
                .de_csr(        de_csr          ),
889 
                .de_txsz(       de_txsz         ),
890 
                .de_adr0(       de_adr0         ),
891 
                .de_adr1(       de_adr1         ),
892 
                .de_csr_we(     de_csr_we       ),
893 
                .de_txsz_we(    de_txsz_we      ),
894 
                .de_adr0_we(    de_adr0_we      ),
895 
                .de_adr1_we(    de_adr1_we      ),
896 
                .de_fetch_descr(de_fetch_descr  ),
897 
                .dma_rest(      dma_rest[5]     ),
898 
                .ptr_set(       ptr_set         )
899 
                );
900 
 
901 10 rudi 
wb_dma_ch_rf #(6, ch6_conf[0], ch6_conf[1], ch6_conf[2], ch6_conf[3]) u6(
902 5 rudi 
                .clk(           clk             ),
903 
                .rst(           rst             ),
904 
                .pointer(       pointer6        ),
905 
                .pointer_s(     pointer6_s      ),
906 
                .ch_csr(        ch6_csr         ),
907 
                .ch_txsz(       ch6_txsz        ),
908 
                .ch_adr0(       ch6_adr0        ),
909 
                .ch_adr1(       ch6_adr1        ),
910 
                .ch_am0(        ch6_am0         ),
911 
                .ch_am1(        ch6_am1         ),
912 
                .sw_pointer(    sw_pointer6     ),
913 
                .ch_stop(       ch_stop[6]      ),
914 
                .ch_dis(        ch_dis[6]       ),
915 
                .int(           ch_int[6]       ),
916 
                .wb_rf_din(     wb_rf_din       ),
917 
                .wb_rf_adr(     wb_rf_adr       ),
918 
                .wb_rf_we(      wb_rf_we        ),
919 
                .wb_rf_re(      wb_rf_re        ),
920 
                .ch_sel(        ch_sel          ),
921 
                .ndnr(          ndnr[6]         ),
922 
                .dma_busy(      dma_busy        ),
923 
                .dma_err(       dma_err         ),
924 
                .dma_done(      dma_done        ),
925 
                .dma_done_all(  dma_done_all    ),
926 
                .de_csr(        de_csr          ),
927 
                .de_txsz(       de_txsz         ),
928 
                .de_adr0(       de_adr0         ),
929 
                .de_adr1(       de_adr1         ),
930 
                .de_csr_we(     de_csr_we       ),
931 
                .de_txsz_we(    de_txsz_we      ),
932 
                .de_adr0_we(    de_adr0_we      ),
933 
                .de_adr1_we(    de_adr1_we      ),
934 
                .de_fetch_descr(de_fetch_descr  ),
935 
                .dma_rest(      dma_rest[6]     ),
936 
                .ptr_set(       ptr_set         )
937 
                );
938 
 
939 10 rudi 
wb_dma_ch_rf #(7, ch7_conf[0], ch7_conf[1], ch7_conf[2], ch7_conf[3]) u7(
940 5 rudi 
                .clk(           clk             ),
941 
                .rst(           rst             ),
942 
                .pointer(       pointer7        ),
943 
                .pointer_s(     pointer7_s      ),
944 
                .ch_csr(        ch7_csr         ),
945 
                .ch_txsz(       ch7_txsz        ),
946 
                .ch_adr0(       ch7_adr0        ),
947 
                .ch_adr1(       ch7_adr1        ),
948 
                .ch_am0(        ch7_am0         ),
949 
                .ch_am1(        ch7_am1         ),
950 
                .sw_pointer(    sw_pointer7     ),
951 
                .ch_stop(       ch_stop[7]      ),
952 
                .ch_dis(        ch_dis[7]       ),
953 
                .int(           ch_int[7]       ),
954 
                .wb_rf_din(     wb_rf_din       ),
955 
                .wb_rf_adr(     wb_rf_adr       ),
956 
                .wb_rf_we(      wb_rf_we        ),
957 
                .wb_rf_re(      wb_rf_re        ),
958 
                .ch_sel(        ch_sel          ),
959 
                .ndnr(          ndnr[7]         ),
960 
                .dma_busy(      dma_busy        ),
961 
                .dma_err(       dma_err         ),
962 
                .dma_done(      dma_done        ),
963 
                .dma_done_all(  dma_done_all    ),
964 
                .de_csr(        de_csr          ),
965 
                .de_txsz(       de_txsz         ),
966 
                .de_adr0(       de_adr0         ),
967 
                .de_adr1(       de_adr1         ),
968 
                .de_csr_we(     de_csr_we       ),
969 
                .de_txsz_we(    de_txsz_we      ),
970 
                .de_adr0_we(    de_adr0_we      ),
971 
                .de_adr1_we(    de_adr1_we      ),
972 
                .de_fetch_descr(de_fetch_descr  ),
973 
                .dma_rest(      dma_rest[7]     ),
974 
                .ptr_set(       ptr_set         )
975 
                );
976 
 
977 10 rudi 
wb_dma_ch_rf #(8, ch8_conf[0], ch8_conf[1], ch8_conf[2], ch8_conf[3]) u8(
978 5 rudi 
                .clk(           clk             ),
979 
                .rst(           rst             ),
980 
                .pointer(       pointer8        ),
981 
                .pointer_s(     pointer8_s      ),
982 
                .ch_csr(        ch8_csr         ),
983 
                .ch_txsz(       ch8_txsz        ),
984 
                .ch_adr0(       ch8_adr0        ),
985 
                .ch_adr1(       ch8_adr1        ),
986 
                .ch_am0(        ch8_am0         ),
987 
                .ch_am1(        ch8_am1         ),
988 
                .sw_pointer(    sw_pointer8     ),
989 
                .ch_stop(       ch_stop[8]      ),
990 
                .ch_dis(        ch_dis[8]       ),
991 
                .int(           ch_int[8]       ),
992 
                .wb_rf_din(     wb_rf_din       ),
993 
                .wb_rf_adr(     wb_rf_adr       ),
994 
                .wb_rf_we(      wb_rf_we        ),
995 
                .wb_rf_re(      wb_rf_re        ),
996 
                .ch_sel(        ch_sel          ),
997 
                .ndnr(          ndnr[8]         ),
998 
                .dma_busy(      dma_busy        ),
999 
                .dma_err(       dma_err         ),
1000 
                .dma_done(      dma_done        ),
1001 
                .dma_done_all(  dma_done_all    ),
1002 
                .de_csr(        de_csr          ),
1003 
                .de_txsz(       de_txsz         ),
1004 
                .de_adr0(       de_adr0         ),
1005 
                .de_adr1(       de_adr1         ),
1006 
                .de_csr_we(     de_csr_we       ),
1007 
                .de_txsz_we(    de_txsz_we      ),
1008 
                .de_adr0_we(    de_adr0_we      ),
1009 
                .de_adr1_we(    de_adr1_we      ),
1010 
                .de_fetch_descr(de_fetch_descr  ),
1011 
                .dma_rest(      dma_rest[8]     ),
1012 
                .ptr_set(       ptr_set         )
1013 
                );
1014 
 
1015 10 rudi 
wb_dma_ch_rf #(9, ch9_conf[0], ch9_conf[1], ch9_conf[2], ch9_conf[3]) u9(
1016 5 rudi 
                .clk(           clk             ),
1017 
                .rst(           rst             ),
1018 
                .pointer(       pointer9        ),
1019 
                .pointer_s(     pointer9_s      ),
1020 
                .ch_csr(        ch9_csr         ),
1021 
                .ch_txsz(       ch9_txsz        ),
1022 
                .ch_adr0(       ch9_adr0        ),
1023 
                .ch_adr1(       ch9_adr1        ),
1024 
                .ch_am0(        ch9_am0         ),
1025 
                .ch_am1(        ch9_am1         ),
1026 
                .sw_pointer(    sw_pointer9     ),
1027 
                .ch_stop(       ch_stop[9]      ),
1028 
                .ch_dis(        ch_dis[9]       ),
1029 
                .int(           ch_int[9]       ),
1030 
                .wb_rf_din(     wb_rf_din       ),
1031 
                .wb_rf_adr(     wb_rf_adr       ),
1032 
                .wb_rf_we(      wb_rf_we        ),
1033 
                .wb_rf_re(      wb_rf_re        ),
1034 
                .ch_sel(        ch_sel          ),
1035 
                .ndnr(          ndnr[9]         ),
1036 
                .dma_busy(      dma_busy        ),
1037 
                .dma_err(       dma_err         ),
1038 
                .dma_done(      dma_done        ),
1039 
                .dma_done_all(  dma_done_all    ),
1040 
                .de_csr(        de_csr          ),
1041 
                .de_txsz(       de_txsz         ),
1042 
                .de_adr0(       de_adr0         ),
1043 
                .de_adr1(       de_adr1         ),
1044 
                .de_csr_we(     de_csr_we       ),
1045 
                .de_txsz_we(    de_txsz_we      ),
1046 
                .de_adr0_we(    de_adr0_we      ),
1047 
                .de_adr1_we(    de_adr1_we      ),
1048 
                .de_fetch_descr(de_fetch_descr  ),
1049 
                .dma_rest(      dma_rest[9]     ),
1050 
                .ptr_set(       ptr_set         )
1051 
                );
1052 
 
1053 10 rudi 
wb_dma_ch_rf #(10, ch10_conf[0], ch10_conf[1], ch10_conf[2], ch10_conf[3]) u10(
1054 5 rudi 
                .clk(           clk             ),
1055 
                .rst(           rst             ),
1056 
                .pointer(       pointer10       ),
1057 
                .pointer_s(     pointer10_s     ),
1058 
                .ch_csr(        ch10_csr                ),
1059 
                .ch_txsz(       ch10_txsz       ),
1060 
                .ch_adr0(       ch10_adr0       ),
1061 
                .ch_adr1(       ch10_adr1       ),
1062 
                .ch_am0(        ch10_am0                ),
1063 
                .ch_am1(        ch10_am1                ),
1064 
                .sw_pointer(    sw_pointer10    ),
1065 
                .ch_stop(       ch_stop[10]     ),
1066 
                .ch_dis(        ch_dis[10]      ),
1067 
                .int(           ch_int[10]      ),
1068 
                .wb_rf_din(     wb_rf_din       ),
1069 
                .wb_rf_adr(     wb_rf_adr       ),
1070 
                .wb_rf_we(      wb_rf_we        ),
1071 
                .wb_rf_re(      wb_rf_re        ),
1072 
                .ch_sel(        ch_sel          ),
1073 
                .ndnr(          ndnr[10]                ),
1074 
                .dma_busy(      dma_busy        ),
1075 
                .dma_err(       dma_err         ),
1076 
                .dma_done(      dma_done        ),
1077 
                .dma_done_all(  dma_done_all    ),
1078 
                .de_csr(        de_csr          ),
1079 
                .de_txsz(       de_txsz         ),
1080 
                .de_adr0(       de_adr0         ),
1081 
                .de_adr1(       de_adr1         ),
1082 
                .de_csr_we(     de_csr_we       ),
1083 
                .de_txsz_we(    de_txsz_we      ),
1084 
                .de_adr0_we(    de_adr0_we      ),
1085 
                .de_adr1_we(    de_adr1_we      ),
1086 
                .de_fetch_descr(de_fetch_descr  ),
1087 
                .dma_rest(      dma_rest[10]    ),
1088 
                .ptr_set(       ptr_set         )
1089 
                );
1090 
 
1091 10 rudi 
wb_dma_ch_rf #(11, ch11_conf[0], ch11_conf[1], ch11_conf[2], ch11_conf[3]) u11(
1092 5 rudi 
                .clk(           clk             ),
1093 
                .rst(           rst             ),
1094 
                .pointer(       pointer11       ),
1095 
                .pointer_s(     pointer11_s     ),
1096 
                .ch_csr(        ch11_csr                ),
1097 
                .ch_txsz(       ch11_txsz       ),
1098 
                .ch_adr0(       ch11_adr0       ),
1099 
                .ch_adr1(       ch11_adr1       ),
1100 
                .ch_am0(        ch11_am0                ),
1101 
                .ch_am1(        ch11_am1                ),
1102 
                .sw_pointer(    sw_pointer11    ),
1103 
                .ch_stop(       ch_stop[11]     ),
1104 
                .ch_dis(        ch_dis[11]      ),
1105 
                .int(           ch_int[11]      ),
1106 
                .wb_rf_din(     wb_rf_din       ),
1107 
                .wb_rf_adr(     wb_rf_adr       ),
1108 
                .wb_rf_we(      wb_rf_we        ),
1109 
                .wb_rf_re(      wb_rf_re        ),
1110 
                .ch_sel(        ch_sel          ),
1111 
                .ndnr(          ndnr[11]                ),
1112 
                .dma_busy(      dma_busy        ),
1113 
                .dma_err(       dma_err         ),
1114 
                .dma_done(      dma_done        ),
1115 
                .dma_done_all(  dma_done_all    ),
1116 
                .de_csr(        de_csr          ),
1117 
                .de_txsz(       de_txsz         ),
1118 
                .de_adr0(       de_adr0         ),
1119 
                .de_adr1(       de_adr1         ),
1120 
                .de_csr_we(     de_csr_we       ),
1121 
                .de_txsz_we(    de_txsz_we      ),
1122 
                .de_adr0_we(    de_adr0_we      ),
1123 
                .de_adr1_we(    de_adr1_we      ),
1124 
                .de_fetch_descr(de_fetch_descr  ),
1125 
                .dma_rest(      dma_rest[11]    ),
1126 
                .ptr_set(       ptr_set         )
1127 
                );
1128 
 
1129 10 rudi 
wb_dma_ch_rf #(12, ch12_conf[0], ch12_conf[1], ch12_conf[2], ch12_conf[3]) u12(
1130 5 rudi 
                .clk(           clk             ),
1131 
                .rst(           rst             ),
1132 
                .pointer(       pointer12       ),
1133 
                .pointer_s(     pointer12_s     ),
1134 
                .ch_csr(        ch12_csr                ),
1135 
                .ch_txsz(       ch12_txsz       ),
1136 
                .ch_adr0(       ch12_adr0       ),
1137 
                .ch_adr1(       ch12_adr1       ),
1138 
                .ch_am0(        ch12_am0                ),
1139 
                .ch_am1(        ch12_am1                ),
1140 
                .sw_pointer(    sw_pointer12    ),
1141 
                .ch_stop(       ch_stop[12]     ),
1142 
                .ch_dis(        ch_dis[12]      ),
1143 
                .int(           ch_int[12]      ),
1144 
                .wb_rf_din(     wb_rf_din       ),
1145 
                .wb_rf_adr(     wb_rf_adr       ),
1146 
                .wb_rf_we(      wb_rf_we        ),
1147 
                .wb_rf_re(      wb_rf_re        ),
1148 
                .ch_sel(        ch_sel          ),
1149 
                .ndnr(          ndnr[12]                ),
1150 
                .dma_busy(      dma_busy        ),
1151 
                .dma_err(       dma_err         ),
1152 
                .dma_done(      dma_done        ),
1153 
                .dma_done_all(  dma_done_all    ),
1154 
                .de_csr(        de_csr          ),
1155 
                .de_txsz(       de_txsz         ),
1156 
                .de_adr0(       de_adr0         ),
1157 
                .de_adr1(       de_adr1         ),
1158 
                .de_csr_we(     de_csr_we       ),
1159 
                .de_txsz_we(    de_txsz_we      ),
1160 
                .de_adr0_we(    de_adr0_we      ),
1161 
                .de_adr1_we(    de_adr1_we      ),
1162 
                .de_fetch_descr(de_fetch_descr  ),
1163 
                .dma_rest(      dma_rest[12]    ),
1164 
                .ptr_set(       ptr_set         )
1165 
                );
1166 
 
1167 10 rudi 
wb_dma_ch_rf #(13, ch13_conf[0], ch13_conf[1], ch13_conf[2], ch13_conf[3]) u13(
1168 5 rudi 
                .clk(           clk             ),
1169 
                .rst(           rst             ),
1170 
                .pointer(       pointer13       ),
1171 
                .pointer_s(     pointer13_s     ),
1172 
                .ch_csr(        ch13_csr                ),
1173 
                .ch_txsz(       ch13_txsz       ),
1174 
                .ch_adr0(       ch13_adr0       ),
1175 
                .ch_adr1(       ch13_adr1       ),
1176 
                .ch_am0(        ch13_am0                ),
1177 
                .ch_am1(        ch13_am1                ),
1178 
                .sw_pointer(    sw_pointer13    ),
1179 
                .ch_stop(       ch_stop[13]     ),
1180 
                .ch_dis(        ch_dis[13]      ),
1181 
                .int(           ch_int[13]      ),
1182 
                .wb_rf_din(     wb_rf_din       ),
1183 
                .wb_rf_adr(     wb_rf_adr       ),
1184 
                .wb_rf_we(      wb_rf_we        ),
1185 
                .wb_rf_re(      wb_rf_re        ),
1186 
                .ch_sel(        ch_sel          ),
1187 
                .ndnr(          ndnr[13]                ),
1188 
                .dma_busy(      dma_busy        ),
1189 
                .dma_err(       dma_err         ),
1190 
                .dma_done(      dma_done        ),
1191 
                .dma_done_all(  dma_done_all    ),
1192 
                .de_csr(        de_csr          ),
1193 
                .de_txsz(       de_txsz         ),
1194 
                .de_adr0(       de_adr0         ),
1195 
                .de_adr1(       de_adr1         ),
1196 
                .de_csr_we(     de_csr_we       ),
1197 
                .de_txsz_we(    de_txsz_we      ),
1198 
                .de_adr0_we(    de_adr0_we      ),
1199 
                .de_adr1_we(    de_adr1_we      ),
1200 
                .de_fetch_descr(de_fetch_descr  ),
1201 
                .dma_rest(      dma_rest[13]    ),
1202 
                .ptr_set(       ptr_set         )
1203 
                );
1204 
 
1205 10 rudi 
wb_dma_ch_rf #(14, ch14_conf[0], ch14_conf[1], ch14_conf[2], ch14_conf[3]) u14(
1206 5 rudi 
                .clk(           clk             ),
1207 
                .rst(           rst             ),
1208 
                .pointer(       pointer14       ),
1209 
                .pointer_s(     pointer14_s     ),
1210 
                .ch_csr(        ch14_csr                ),
1211 
                .ch_txsz(       ch14_txsz       ),
1212 
                .ch_adr0(       ch14_adr0       ),
1213 
                .ch_adr1(       ch14_adr1       ),
1214 
                .ch_am0(        ch14_am0                ),
1215 
                .ch_am1(        ch14_am1                ),
1216 
                .sw_pointer(    sw_pointer14    ),
1217 
                .ch_stop(       ch_stop[14]     ),
1218 
                .ch_dis(        ch_dis[14]      ),
1219 
                .int(           ch_int[14]      ),
1220 
                .wb_rf_din(     wb_rf_din       ),
1221 
                .wb_rf_adr(     wb_rf_adr       ),
1222 
                .wb_rf_we(      wb_rf_we        ),
1223 
                .wb_rf_re(      wb_rf_re        ),
1224 
                .ch_sel(        ch_sel          ),
1225 
                .ndnr(          ndnr[14]                ),
1226 
                .dma_busy(      dma_busy        ),
1227 
                .dma_err(       dma_err         ),
1228 
                .dma_done(      dma_done        ),
1229 
                .dma_done_all(  dma_done_all    ),
1230 
                .de_csr(        de_csr          ),
1231 
                .de_txsz(       de_txsz         ),
1232 
                .de_adr0(       de_adr0         ),
1233 
                .de_adr1(       de_adr1         ),
1234 
                .de_csr_we(     de_csr_we       ),
1235 
                .de_txsz_we(    de_txsz_we      ),
1236 
                .de_adr0_we(    de_adr0_we      ),
1237 
                .de_adr1_we(    de_adr1_we      ),
1238 
                .de_fetch_descr(de_fetch_descr  ),
1239 
                .dma_rest(      dma_rest[14]    ),
1240 
                .ptr_set(       ptr_set         )
1241 
                );
1242 
 
1243 10 rudi 
wb_dma_ch_rf #(15, ch15_conf[0], ch15_conf[1], ch15_conf[2], ch15_conf[3]) u15(
1244 5 rudi 
                .clk(           clk             ),
1245 
                .rst(           rst             ),
1246 
                .pointer(       pointer15       ),
1247 
                .pointer_s(     pointer15_s     ),
1248 
                .ch_csr(        ch15_csr                ),
1249 
                .ch_txsz(       ch15_txsz       ),
1250 
                .ch_adr0(       ch15_adr0       ),
1251 
                .ch_adr1(       ch15_adr1       ),
1252 
                .ch_am0(        ch15_am0                ),
1253 
                .ch_am1(        ch15_am1                ),
1254 
                .sw_pointer(    sw_pointer15    ),
1255 
                .ch_stop(       ch_stop[15]     ),
1256 
                .ch_dis(        ch_dis[15]      ),
1257 
                .int(           ch_int[15]      ),
1258 
                .wb_rf_din(     wb_rf_din       ),
1259 
                .wb_rf_adr(     wb_rf_adr       ),
1260 
                .wb_rf_we(      wb_rf_we        ),
1261 
                .wb_rf_re(      wb_rf_re        ),
1262 
                .ch_sel(        ch_sel          ),
1263 
                .ndnr(          ndnr[15]                ),
1264 
                .dma_busy(      dma_busy        ),
1265 
                .dma_err(       dma_err         ),
1266 
                .dma_done(      dma_done        ),
1267 
                .dma_done_all(  dma_done_all    ),
1268 
                .de_csr(        de_csr          ),
1269 
                .de_txsz(       de_txsz         ),
1270 
                .de_adr0(       de_adr0         ),
1271 
                .de_adr1(       de_adr1         ),
1272 
                .de_csr_we(     de_csr_we       ),
1273 
                .de_txsz_we(    de_txsz_we      ),
1274 
                .de_adr0_we(    de_adr0_we      ),
1275 
                .de_adr1_we(    de_adr1_we      ),
1276 
                .de_fetch_descr(de_fetch_descr  ),
1277 
                .dma_rest(      dma_rest[15]    ),
1278 
                .ptr_set(       ptr_set         )
1279 
                );
1280 
 
1281 10 rudi 
wb_dma_ch_rf #(16, ch16_conf[0], ch16_conf[1], ch16_conf[2], ch16_conf[3]) u16(
1282 5 rudi 
                .clk(           clk             ),
1283 
                .rst(           rst             ),
1284 
                .pointer(       pointer16       ),
1285 
                .pointer_s(     pointer16_s     ),
1286 
                .ch_csr(        ch16_csr                ),
1287 
                .ch_txsz(       ch16_txsz       ),
1288 
                .ch_adr0(       ch16_adr0       ),
1289 
                .ch_adr1(       ch16_adr1       ),
1290 
                .ch_am0(        ch16_am0                ),
1291 
                .ch_am1(        ch16_am1                ),
1292 
                .sw_pointer(    sw_pointer16    ),
1293 
                .ch_stop(       ch_stop[16]     ),
1294 
                .ch_dis(        ch_dis[16]      ),
1295 
                .int(           ch_int[16]      ),
1296 
                .wb_rf_din(     wb_rf_din       ),
1297 
                .wb_rf_adr(     wb_rf_adr       ),
1298 
                .wb_rf_we(      wb_rf_we        ),
1299 
                .wb_rf_re(      wb_rf_re        ),
1300 
                .ch_sel(        ch_sel          ),
1301 
                .ndnr(          ndnr[16]                ),
1302 
                .dma_busy(      dma_busy        ),
1303 
                .dma_err(       dma_err         ),
1304 
                .dma_done(      dma_done        ),
1305 
                .dma_done_all(  dma_done_all    ),
1306 
                .de_csr(        de_csr          ),
1307 
                .de_txsz(       de_txsz         ),
1308 
                .de_adr0(       de_adr0         ),
1309 
                .de_adr1(       de_adr1         ),
1310 
                .de_csr_we(     de_csr_we       ),
1311 
                .de_txsz_we(    de_txsz_we      ),
1312 
                .de_adr0_we(    de_adr0_we      ),
1313 
                .de_adr1_we(    de_adr1_we      ),
1314 
                .de_fetch_descr(de_fetch_descr  ),
1315 
                .dma_rest(      dma_rest[16]    ),
1316 
                .ptr_set(       ptr_set         )
1317 
                );
1318 
 
1319 10 rudi 
wb_dma_ch_rf #(17, ch17_conf[0], ch17_conf[1], ch17_conf[2], ch17_conf[3]) u17(
1320 5 rudi 
                .clk(           clk             ),
1321 
                .rst(           rst             ),
1322 
                .pointer(       pointer17       ),
1323 
                .pointer_s(     pointer17_s     ),
1324 
                .ch_csr(        ch17_csr                ),
1325 
                .ch_txsz(       ch17_txsz       ),
1326 
                .ch_adr0(       ch17_adr0       ),
1327 
                .ch_adr1(       ch17_adr1       ),
1328 
                .ch_am0(        ch17_am0                ),
1329 
                .ch_am1(        ch17_am1                ),
1330 
                .sw_pointer(    sw_pointer17    ),
1331 
                .ch_stop(       ch_stop[17]     ),
1332 
                .ch_dis(        ch_dis[17]      ),
1333 
                .int(           ch_int[17]      ),
1334 
                .wb_rf_din(     wb_rf_din       ),
1335 
                .wb_rf_adr(     wb_rf_adr       ),
1336 
                .wb_rf_we(      wb_rf_we        ),
1337 
                .wb_rf_re(      wb_rf_re        ),
1338 
                .ch_sel(        ch_sel          ),
1339 
                .ndnr(          ndnr[17]                ),
1340 
                .dma_busy(      dma_busy        ),
1341 
                .dma_err(       dma_err         ),
1342 
                .dma_done(      dma_done        ),
1343 
                .dma_done_all(  dma_done_all    ),
1344 
                .de_csr(        de_csr          ),
1345 
                .de_txsz(       de_txsz         ),
1346 
                .de_adr0(       de_adr0         ),
1347 
                .de_adr1(       de_adr1         ),
1348 
                .de_csr_we(     de_csr_we       ),
1349 
                .de_txsz_we(    de_txsz_we      ),
1350 
                .de_adr0_we(    de_adr0_we      ),
1351 
                .de_adr1_we(    de_adr1_we      ),
1352 
                .de_fetch_descr(de_fetch_descr  ),
1353 
                .dma_rest(      dma_rest[17]    ),
1354 
                .ptr_set(       ptr_set         )
1355 
                );
1356 
 
1357 10 rudi 
wb_dma_ch_rf #(18, ch18_conf[0], ch18_conf[1], ch18_conf[2], ch18_conf[3]) u18(
1358 5 rudi 
                .clk(           clk             ),
1359 
                .rst(           rst             ),
1360 
                .pointer(       pointer18       ),
1361 
                .pointer_s(     pointer18_s     ),
1362 
                .ch_csr(        ch18_csr                ),
1363 
                .ch_txsz(       ch18_txsz       ),
1364 
                .ch_adr0(       ch18_adr0       ),
1365 
                .ch_adr1(       ch18_adr1       ),
1366 
                .ch_am0(        ch18_am0                ),
1367 
                .ch_am1(        ch18_am1                ),
1368 
                .sw_pointer(    sw_pointer18    ),
1369 
                .ch_stop(       ch_stop[18]     ),
1370 
                .ch_dis(        ch_dis[18]      ),
1371 
                .int(           ch_int[18]      ),
1372 
                .wb_rf_din(     wb_rf_din       ),
1373 
                .wb_rf_adr(     wb_rf_adr       ),
1374 
                .wb_rf_we(      wb_rf_we        ),
1375 
                .wb_rf_re(      wb_rf_re        ),
1376 
                .ch_sel(        ch_sel          ),
1377 
                .ndnr(          ndnr[18]                ),
1378 
                .dma_busy(      dma_busy        ),
1379 
                .dma_err(       dma_err         ),
1380 
                .dma_done(      dma_done        ),
1381 
                .dma_done_all(  dma_done_all    ),
1382 
                .de_csr(        de_csr          ),
1383 
                .de_txsz(       de_txsz         ),
1384 
                .de_adr0(       de_adr0         ),
1385 
                .de_adr1(       de_adr1         ),
1386 
                .de_csr_we(     de_csr_we       ),
1387 
                .de_txsz_we(    de_txsz_we      ),
1388 
                .de_adr0_we(    de_adr0_we      ),
1389 
                .de_adr1_we(    de_adr1_we      ),
1390 
                .de_fetch_descr(de_fetch_descr  ),
1391 
                .dma_rest(      dma_rest[18]    ),
1392 
                .ptr_set(       ptr_set         )
1393 
                );
1394 
 
1395 10 rudi 
wb_dma_ch_rf #(19, ch19_conf[0], ch19_conf[1], ch19_conf[2], ch19_conf[3]) u19(
1396 5 rudi 
                .clk(           clk             ),
1397 
                .rst(           rst             ),
1398 
                .pointer(       pointer19       ),
1399 
                .pointer_s(     pointer19_s     ),
1400 
                .ch_csr(        ch19_csr                ),
1401 
                .ch_txsz(       ch19_txsz       ),
1402 
                .ch_adr0(       ch19_adr0       ),
1403 
                .ch_adr1(       ch19_adr1       ),
1404 
                .ch_am0(        ch19_am0                ),
1405 
                .ch_am1(        ch19_am1                ),
1406 
                .sw_pointer(    sw_pointer19    ),
1407 
                .ch_stop(       ch_stop[19]     ),
1408 
                .ch_dis(        ch_dis[19]      ),
1409 
                .int(           ch_int[19]      ),
1410 
                .wb_rf_din(     wb_rf_din       ),
1411 
                .wb_rf_adr(     wb_rf_adr       ),
1412 
                .wb_rf_we(      wb_rf_we        ),
1413 
                .wb_rf_re(      wb_rf_re        ),
1414 
                .ch_sel(        ch_sel          ),
1415 
                .ndnr(          ndnr[19]                ),
1416 
                .dma_busy(      dma_busy        ),
1417 
                .dma_err(       dma_err         ),
1418 
                .dma_done(      dma_done        ),
1419 
                .dma_done_all(  dma_done_all    ),
1420 
                .de_csr(        de_csr          ),
1421 
                .de_txsz(       de_txsz         ),
1422 
                .de_adr0(       de_adr0         ),
1423 
                .de_adr1(       de_adr1         ),
1424 
                .de_csr_we(     de_csr_we       ),
1425 
                .de_txsz_we(    de_txsz_we      ),
1426 
                .de_adr0_we(    de_adr0_we      ),
1427 
                .de_adr1_we(    de_adr1_we      ),
1428 
                .de_fetch_descr(de_fetch_descr  ),
1429 
                .dma_rest(      dma_rest[19]    ),
1430 
                .ptr_set(       ptr_set         )
1431 
                );
1432 
 
1433 10 rudi 
wb_dma_ch_rf #(20, ch20_conf[0], ch20_conf[1], ch20_conf[2], ch20_conf[3]) u20(
1434 5 rudi 
                .clk(           clk             ),
1435 
                .rst(           rst             ),
1436 
                .pointer(       pointer20       ),
1437 
                .pointer_s(     pointer20_s     ),
1438 
                .ch_csr(        ch20_csr                ),
1439 
                .ch_txsz(       ch20_txsz       ),
1440 
                .ch_adr0(       ch20_adr0       ),
1441 
                .ch_adr1(       ch20_adr1       ),
1442 
                .ch_am0(        ch20_am0                ),
1443 
                .ch_am1(        ch20_am1                ),
1444 
                .sw_pointer(    sw_pointer20    ),
1445 
                .ch_stop(       ch_stop[20]     ),
1446 
                .ch_dis(        ch_dis[20]      ),
1447 
                .int(           ch_int[20]      ),
1448 
                .wb_rf_din(     wb_rf_din       ),
1449 
                .wb_rf_adr(     wb_rf_adr       ),
1450 
                .wb_rf_we(      wb_rf_we        ),
1451 
                .wb_rf_re(      wb_rf_re        ),
1452 
                .ch_sel(        ch_sel          ),
1453 
                .ndnr(          ndnr[20]                ),
1454 
                .dma_busy(      dma_busy        ),
1455 
                .dma_err(       dma_err         ),
1456 
                .dma_done(      dma_done        ),
1457 
                .dma_done_all(  dma_done_all    ),
1458 
                .de_csr(        de_csr          ),
1459 
                .de_txsz(       de_txsz         ),
1460 
                .de_adr0(       de_adr0         ),
1461 
                .de_adr1(       de_adr1         ),
1462 
                .de_csr_we(     de_csr_we       ),
1463 
                .de_txsz_we(    de_txsz_we      ),
1464 
                .de_adr0_we(    de_adr0_we      ),
1465 
                .de_adr1_we(    de_adr1_we      ),
1466 
                .de_fetch_descr(de_fetch_descr  ),
1467 
                .dma_rest(      dma_rest[20]    ),
1468 
                .ptr_set(       ptr_set         )
1469 
                );
1470 
 
1471 10 rudi 
wb_dma_ch_rf #(21, ch21_conf[0], ch21_conf[1], ch21_conf[2], ch21_conf[3]) u21(
1472 5 rudi 
                .clk(           clk             ),
1473 
                .rst(           rst             ),
1474 
                .pointer(       pointer21       ),
1475 
                .pointer_s(     pointer21_s     ),
1476 
                .ch_csr(        ch21_csr                ),
1477 
                .ch_txsz(       ch21_txsz       ),
1478 
                .ch_adr0(       ch21_adr0       ),
1479 
                .ch_adr1(       ch21_adr1       ),
1480 
                .ch_am0(        ch21_am0                ),
1481 
                .ch_am1(        ch21_am1                ),
1482 
                .sw_pointer(    sw_pointer21    ),
1483 
                .ch_stop(       ch_stop[21]     ),
1484 
                .ch_dis(        ch_dis[21]      ),
1485 
                .int(           ch_int[21]      ),
1486 
                .wb_rf_din(     wb_rf_din       ),
1487 
                .wb_rf_adr(     wb_rf_adr       ),
1488 
                .wb_rf_we(      wb_rf_we        ),
1489 
                .wb_rf_re(      wb_rf_re        ),
1490 
                .ch_sel(        ch_sel          ),
1491 
                .ndnr(          ndnr[21]                ),
1492 
                .dma_busy(      dma_busy        ),
1493 
                .dma_err(       dma_err         ),
1494 
                .dma_done(      dma_done        ),
1495 
                .dma_done_all(  dma_done_all    ),
1496 
                .de_csr(        de_csr          ),
1497 
                .de_txsz(       de_txsz         ),
1498 
                .de_adr0(       de_adr0         ),
1499 
                .de_adr1(       de_adr1         ),
1500 
                .de_csr_we(     de_csr_we       ),
1501 
                .de_txsz_we(    de_txsz_we      ),
1502 
                .de_adr0_we(    de_adr0_we      ),
1503 
                .de_adr1_we(    de_adr1_we      ),
1504 
                .de_fetch_descr(de_fetch_descr  ),
1505 
                .dma_rest(      dma_rest[21]    ),
1506 
                .ptr_set(       ptr_set         )
1507 
                );
1508 
 
1509 10 rudi 
wb_dma_ch_rf #(22, ch22_conf[0], ch22_conf[1], ch22_conf[2], ch22_conf[3]) u22(
1510 5 rudi 
                .clk(           clk             ),
1511 
                .rst(           rst             ),
1512 
                .pointer(       pointer22       ),
1513 
                .pointer_s(     pointer22_s     ),
1514 
                .ch_csr(        ch22_csr                ),
1515 
                .ch_txsz(       ch22_txsz       ),
1516 
                .ch_adr0(       ch22_adr0       ),
1517 
                .ch_adr1(       ch22_adr1       ),
1518 
                .ch_am0(        ch22_am0                ),
1519 
                .ch_am1(        ch22_am1                ),
1520 
                .sw_pointer(    sw_pointer22    ),
1521 
                .ch_stop(       ch_stop[22]     ),
1522 
                .ch_dis(        ch_dis[22]      ),
1523 
                .int(           ch_int[22]      ),
1524 
                .wb_rf_din(     wb_rf_din       ),
1525 
                .wb_rf_adr(     wb_rf_adr       ),
1526 
                .wb_rf_we(      wb_rf_we        ),
1527 
                .wb_rf_re(      wb_rf_re        ),
1528 
                .ch_sel(        ch_sel          ),
1529 
                .ndnr(          ndnr[22]                ),
1530 
                .dma_busy(      dma_busy        ),
1531 
                .dma_err(       dma_err         ),
1532 
                .dma_done(      dma_done        ),
1533 
                .dma_done_all(  dma_done_all    ),
1534 
                .de_csr(        de_csr          ),
1535 
                .de_txsz(       de_txsz         ),
1536 
                .de_adr0(       de_adr0         ),
1537 
                .de_adr1(       de_adr1         ),
1538 
                .de_csr_we(     de_csr_we       ),
1539 
                .de_txsz_we(    de_txsz_we      ),
1540 
                .de_adr0_we(    de_adr0_we      ),
1541 
                .de_adr1_we(    de_adr1_we      ),
1542 
                .de_fetch_descr(de_fetch_descr  ),
1543 
                .dma_rest(      dma_rest[22]    ),
1544 
                .ptr_set(       ptr_set         )
1545 
                );
1546 
 
1547 10 rudi 
wb_dma_ch_rf #(23, ch23_conf[0], ch23_conf[1], ch23_conf[2], ch23_conf[3]) u23(
1548 5 rudi 
                .clk(           clk             ),
1549 
                .rst(           rst             ),
1550 
                .pointer(       pointer23       ),
1551 
                .pointer_s(     pointer23_s     ),
1552 
                .ch_csr(        ch23_csr                ),
1553 
                .ch_txsz(       ch23_txsz       ),
1554 
                .ch_adr0(       ch23_adr0       ),
1555 
                .ch_adr1(       ch23_adr1       ),
1556 
                .ch_am0(        ch23_am0                ),
1557 
                .ch_am1(        ch23_am1                ),
1558 
                .sw_pointer(    sw_pointer23    ),
1559 
                .ch_stop(       ch_stop[23]     ),
1560 
                .ch_dis(        ch_dis[23]      ),
1561 
                .int(           ch_int[23]      ),
1562 
                .wb_rf_din(     wb_rf_din       ),
1563 
                .wb_rf_adr(     wb_rf_adr       ),
1564 
                .wb_rf_we(      wb_rf_we        ),
1565 
                .wb_rf_re(      wb_rf_re        ),
1566 
                .ch_sel(        ch_sel          ),
1567 
                .ndnr(          ndnr[23]                ),
1568 
                .dma_busy(      dma_busy        ),
1569 
                .dma_err(       dma_err         ),
1570 
                .dma_done(      dma_done        ),
1571 
                .dma_done_all(  dma_done_all    ),
1572 
                .de_csr(        de_csr          ),
1573 
                .de_txsz(       de_txsz         ),
1574 
                .de_adr0(       de_adr0         ),
1575 
                .de_adr1(       de_adr1         ),
1576 
                .de_csr_we(     de_csr_we       ),
1577 
                .de_txsz_we(    de_txsz_we      ),
1578 
                .de_adr0_we(    de_adr0_we      ),
1579 
                .de_adr1_we(    de_adr1_we      ),
1580 
                .de_fetch_descr(de_fetch_descr  ),
1581 
                .dma_rest(      dma_rest[23]    ),
1582 
                .ptr_set(       ptr_set         )
1583 
                );
1584 
 
1585 10 rudi 
wb_dma_ch_rf #(24, ch24_conf[0], ch24_conf[1], ch24_conf[2], ch24_conf[3]) u24(
1586 5 rudi 
                .clk(           clk             ),
1587 
                .rst(           rst             ),
1588 
                .pointer(       pointer24       ),
1589 
                .pointer_s(     pointer24_s     ),
1590 
                .ch_csr(        ch24_csr                ),
1591 
                .ch_txsz(       ch24_txsz       ),
1592 
                .ch_adr0(       ch24_adr0       ),
1593 
                .ch_adr1(       ch24_adr1       ),
1594 
                .ch_am0(        ch24_am0                ),
1595 
                .ch_am1(        ch24_am1                ),
1596 
                .sw_pointer(    sw_pointer24    ),
1597 
                .ch_stop(       ch_stop[24]     ),
1598 
                .ch_dis(        ch_dis[24]      ),
1599 
                .int(           ch_int[24]      ),
1600 
                .wb_rf_din(     wb_rf_din       ),
1601 
                .wb_rf_adr(     wb_rf_adr       ),
1602 
                .wb_rf_we(      wb_rf_we        ),
1603 
                .wb_rf_re(      wb_rf_re        ),
1604 
                .ch_sel(        ch_sel          ),
1605 
                .ndnr(          ndnr[24]                ),
1606 
                .dma_busy(      dma_busy        ),
1607 
                .dma_err(       dma_err         ),
1608 
                .dma_done(      dma_done        ),
1609 
                .dma_done_all(  dma_done_all    ),
1610 
                .de_csr(        de_csr          ),
1611 
                .de_txsz(       de_txsz         ),
1612 
                .de_adr0(       de_adr0         ),
1613 
                .de_adr1(       de_adr1         ),
1614 
                .de_csr_we(     de_csr_we       ),
1615 
                .de_txsz_we(    de_txsz_we      ),
1616 
                .de_adr0_we(    de_adr0_we      ),
1617 
                .de_adr1_we(    de_adr1_we      ),
1618 
                .de_fetch_descr(de_fetch_descr  ),
1619 
                .dma_rest(      dma_rest[24]    ),
1620 
                .ptr_set(       ptr_set         )
1621 
                );
1622 
 
1623 10 rudi 
wb_dma_ch_rf #(25, ch25_conf[0], ch25_conf[1], ch25_conf[2], ch25_conf[3]) u25(
1624 5 rudi 
                .clk(           clk             ),
1625 
                .rst(           rst             ),
1626 
                .pointer(       pointer25       ),
1627 
                .pointer_s(     pointer25_s     ),
1628 
                .ch_csr(        ch25_csr                ),
1629 
                .ch_txsz(       ch25_txsz       ),
1630 
                .ch_adr0(       ch25_adr0       ),
1631 
                .ch_adr1(       ch25_adr1       ),
1632 
                .ch_am0(        ch25_am0                ),
1633 
                .ch_am1(        ch25_am1                ),
1634 
                .sw_pointer(    sw_pointer25    ),
1635 
                .ch_stop(       ch_stop[25]     ),
1636 
                .ch_dis(        ch_dis[25]      ),
1637 
                .int(           ch_int[25]      ),
1638 
                .wb_rf_din(     wb_rf_din       ),
1639 
                .wb_rf_adr(     wb_rf_adr       ),
1640 
                .wb_rf_we(      wb_rf_we        ),
1641 
                .wb_rf_re(      wb_rf_re        ),
1642 
                .ch_sel(        ch_sel          ),
1643 
                .ndnr(          ndnr[25]                ),
1644 
                .dma_busy(      dma_busy        ),
1645 
                .dma_err(       dma_err         ),
1646 
                .dma_done(      dma_done        ),
1647 
                .dma_done_all(  dma_done_all    ),
1648 
                .de_csr(        de_csr          ),
1649 
                .de_txsz(       de_txsz         ),
1650 
                .de_adr0(       de_adr0         ),
1651 
                .de_adr1(       de_adr1         ),
1652 
                .de_csr_we(     de_csr_we       ),
1653 
                .de_txsz_we(    de_txsz_we      ),
1654 
                .de_adr0_we(    de_adr0_we      ),
1655 
                .de_adr1_we(    de_adr1_we      ),
1656 
                .de_fetch_descr(de_fetch_descr  ),
1657 
                .dma_rest(      dma_rest[25]    ),
1658 
                .ptr_set(       ptr_set         )
1659 
                );
1660 
 
1661 10 rudi 
wb_dma_ch_rf #(26, ch26_conf[0], ch26_conf[1], ch26_conf[2], ch26_conf[3]) u26(
1662 5 rudi 
                .clk(           clk             ),
1663 
                .rst(           rst             ),
1664 
                .pointer(       pointer26       ),
1665 
                .pointer_s(     pointer26_s     ),
1666 
                .ch_csr(        ch26_csr                ),
1667 
                .ch_txsz(       ch26_txsz       ),
1668 
                .ch_adr0(       ch26_adr0       ),
1669 
                .ch_adr1(       ch26_adr1       ),
1670 
                .ch_am0(        ch26_am0                ),
1671 
                .ch_am1(        ch26_am1                ),
1672 
                .sw_pointer(    sw_pointer26    ),
1673 
                .ch_stop(       ch_stop[26]     ),
1674 
                .ch_dis(        ch_dis[26]      ),
1675 
                .int(           ch_int[26]      ),
1676 
                .wb_rf_din(     wb_rf_din       ),
1677 
                .wb_rf_adr(     wb_rf_adr       ),
1678 
                .wb_rf_we(      wb_rf_we        ),
1679 
                .wb_rf_re(      wb_rf_re        ),
1680 
                .ch_sel(        ch_sel          ),
1681 
                .ndnr(          ndnr[26]                ),
1682 
                .dma_busy(      dma_busy        ),
1683 
                .dma_err(       dma_err         ),
1684 
                .dma_done(      dma_done        ),
1685 
                .dma_done_all(  dma_done_all    ),
1686 
                .de_csr(        de_csr          ),
1687 
                .de_txsz(       de_txsz         ),
1688 
                .de_adr0(       de_adr0         ),
1689 
                .de_adr1(       de_adr1         ),
1690 
                .de_csr_we(     de_csr_we       ),
1691 
                .de_txsz_we(    de_txsz_we      ),
1692 
                .de_adr0_we(    de_adr0_we      ),
1693 
                .de_adr1_we(    de_adr1_we      ),
1694 
                .de_fetch_descr(de_fetch_descr  ),
1695 
                .dma_rest(      dma_rest[26]    ),
1696 
                .ptr_set(       ptr_set         )
1697 
                );
1698 
 
1699 10 rudi 
wb_dma_ch_rf #(27, ch27_conf[0], ch27_conf[1], ch27_conf[2], ch27_conf[3]) u27(
1700 5 rudi 
                .clk(           clk             ),
1701 
                .rst(           rst             ),
1702 
                .pointer(       pointer27       ),
1703 
                .pointer_s(     pointer27_s     ),
1704 
                .ch_csr(        ch27_csr                ),
1705 
                .ch_txsz(       ch27_txsz       ),
1706 
                .ch_adr0(       ch27_adr0       ),
1707 
                .ch_adr1(       ch27_adr1       ),
1708 
                .ch_am0(        ch27_am0                ),
1709 
                .ch_am1(        ch27_am1                ),
1710 
                .sw_pointer(    sw_pointer27    ),
1711 
                .ch_stop(       ch_stop[27]     ),
1712 
                .ch_dis(        ch_dis[27]      ),
1713 
                .int(           ch_int[27]      ),
1714 
                .wb_rf_din(     wb_rf_din       ),
1715 
                .wb_rf_adr(     wb_rf_adr       ),
1716 
                .wb_rf_we(      wb_rf_we        ),
1717 
                .wb_rf_re(      wb_rf_re        ),
1718 
                .ch_sel(        ch_sel          ),
1719 
                .ndnr(          ndnr[27]                ),
1720 
                .dma_busy(      dma_busy        ),
1721 
                .dma_err(       dma_err         ),
1722 
                .dma_done(      dma_done        ),
1723 
                .dma_done_all(  dma_done_all    ),
1724 
                .de_csr(        de_csr          ),
1725 
                .de_txsz(       de_txsz         ),
1726 
                .de_adr0(       de_adr0         ),
1727 
                .de_adr1(       de_adr1         ),
1728 
                .de_csr_we(     de_csr_we       ),
1729 
                .de_txsz_we(    de_txsz_we      ),
1730 
                .de_adr0_we(    de_adr0_we      ),
1731 
                .de_adr1_we(    de_adr1_we      ),
1732 
                .de_fetch_descr(de_fetch_descr  ),
1733 
                .dma_rest(      dma_rest[27]    ),
1734 
                .ptr_set(       ptr_set         )
1735 
                );
1736 
 
1737 10 rudi 
wb_dma_ch_rf #(28, ch28_conf[0], ch28_conf[1], ch28_conf[2], ch28_conf[3]) u28(
1738 5 rudi 
                .clk(           clk             ),
1739 
                .rst(           rst             ),
1740 
                .pointer(       pointer28       ),
1741 
                .pointer_s(     pointer28_s     ),
1742 
                .ch_csr(        ch28_csr                ),
1743 
                .ch_txsz(       ch28_txsz       ),
1744 
                .ch_adr0(       ch28_adr0       ),
1745 
                .ch_adr1(       ch28_adr1       ),
1746 
                .ch_am0(        ch28_am0                ),
1747 
                .ch_am1(        ch28_am1                ),
1748 
                .sw_pointer(    sw_pointer28    ),
1749 
                .ch_stop(       ch_stop[28]     ),
1750 
                .ch_dis(        ch_dis[28]      ),
1751 
                .int(           ch_int[28]      ),
1752 
                .wb_rf_din(     wb_rf_din       ),
1753 
                .wb_rf_adr(     wb_rf_adr       ),
1754 
                .wb_rf_we(      wb_rf_we        ),
1755 
                .wb_rf_re(      wb_rf_re        ),
1756 
                .ch_sel(        ch_sel          ),
1757 
                .ndnr(          ndnr[28]                ),
1758 
                .dma_busy(      dma_busy        ),
1759 
                .dma_err(       dma_err         ),
1760 
                .dma_done(      dma_done        ),
1761 
                .dma_done_all(  dma_done_all    ),
1762 
                .de_csr(        de_csr          ),
1763 
                .de_txsz(       de_txsz         ),
1764 
                .de_adr0(       de_adr0         ),
1765 
                .de_adr1(       de_adr1         ),
1766 
                .de_csr_we(     de_csr_we       ),
1767 
                .de_txsz_we(    de_txsz_we      ),
1768 
                .de_adr0_we(    de_adr0_we      ),
1769 
                .de_adr1_we(    de_adr1_we      ),
1770 
                .de_fetch_descr(de_fetch_descr  ),
1771 
                .dma_rest(      dma_rest[28]    ),
1772 
                .ptr_set(       ptr_set         )
1773 
                );
1774 
 
1775 10 rudi 
wb_dma_ch_rf #(29, ch29_conf[0], ch29_conf[1], ch29_conf[2], ch29_conf[3]) u29(
1776 5 rudi 
                .clk(           clk             ),
1777 
                .rst(           rst             ),
1778 
                .pointer(       pointer29       ),
1779 
                .pointer_s(     pointer29_s     ),
1780 
                .ch_csr(        ch29_csr                ),
1781 
                .ch_txsz(       ch29_txsz       ),
1782 
                .ch_adr0(       ch29_adr0       ),
1783 
                .ch_adr1(       ch29_adr1       ),
1784 
                .ch_am0(        ch29_am0                ),
1785 
                .ch_am1(        ch29_am1                ),
1786 
                .sw_pointer(    sw_pointer29    ),
1787 
                .ch_stop(       ch_stop[29]     ),
1788 
                .ch_dis(        ch_dis[29]      ),
1789 
                .int(           ch_int[29]      ),
1790 
                .wb_rf_din(     wb_rf_din       ),
1791 
                .wb_rf_adr(     wb_rf_adr       ),
1792 
                .wb_rf_we(      wb_rf_we        ),
1793 
                .wb_rf_re(      wb_rf_re        ),
1794 
                .ch_sel(        ch_sel          ),
1795 
                .ndnr(          ndnr[29]                ),
1796 
                .dma_busy(      dma_busy        ),
1797 
                .dma_err(       dma_err         ),
1798 
                .dma_done(      dma_done        ),
1799 
                .dma_done_all(  dma_done_all    ),
1800 
                .de_csr(        de_csr          ),
1801 
                .de_txsz(       de_txsz         ),
1802 
                .de_adr0(       de_adr0         ),
1803 
                .de_adr1(       de_adr1         ),
1804 
                .de_csr_we(     de_csr_we       ),
1805 
                .de_txsz_we(    de_txsz_we      ),
1806 
                .de_adr0_we(    de_adr0_we      ),
1807 
                .de_adr1_we(    de_adr1_we      ),
1808 
                .de_fetch_descr(de_fetch_descr  ),
1809 
                .dma_rest(      dma_rest[29]    ),
1810 
                .ptr_set(       ptr_set         )
1811 
                );
1812 
 
1813 10 rudi 
wb_dma_ch_rf #(30, ch30_conf[0], ch30_conf[1], ch30_conf[2], ch30_conf[3]) u30(
1814 5 rudi 
                .clk(           clk             ),
1815 
                .rst(           rst             ),
1816 
                .pointer(       pointer30       ),
1817 
                .pointer_s(     pointer30_s     ),
1818 
                .ch_csr(        ch30_csr                ),
1819 
                .ch_txsz(       ch30_txsz       ),
1820 
                .ch_adr0(       ch30_adr0       ),
1821 
                .ch_adr1(       ch30_adr1       ),
1822 
                .ch_am0(        ch30_am0                ),
1823 
                .ch_am1(        ch30_am1                ),
1824 
                .sw_pointer(    sw_pointer30    ),
1825 
                .ch_stop(       ch_stop[30]     ),
1826 
                .ch_dis(        ch_dis[30]      ),
1827 
                .int(           ch_int[30]      ),
1828 
                .wb_rf_din(     wb_rf_din       ),
1829 
                .wb_rf_adr(     wb_rf_adr       ),
1830 
                .wb_rf_we(      wb_rf_we        ),
1831 
                .wb_rf_re(      wb_rf_re        ),
1832 
                .ch_sel(        ch_sel          ),
1833 
                .ndnr(          ndnr[30]                ),
1834 
                .dma_busy(      dma_busy        ),
1835 
                .dma_err(       dma_err         ),
1836 
                .dma_done(      dma_done        ),
1837 
                .dma_done_all(  dma_done_all    ),
1838 
                .de_csr(        de_csr          ),
1839 
                .de_txsz(       de_txsz         ),
1840 
                .de_adr0(       de_adr0         ),
1841 
                .de_adr1(       de_adr1         ),
1842 
                .de_csr_we(     de_csr_we       ),
1843 
                .de_txsz_we(    de_txsz_we      ),
1844 
                .de_adr0_we(    de_adr0_we      ),
1845 
                .de_adr1_we(    de_adr1_we      ),
1846 
                .de_fetch_descr(de_fetch_descr  ),
1847 
                .dma_rest(      dma_rest[30]    ),
1848 
                .ptr_set(       ptr_set         )
1849 
                );
1850 
 
1851 
endmodule

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