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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE DMA Top Level ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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rudi |
// $Id: wb_dma_top.v,v 1.3 2001-09-07 15:34:38 rudi Exp $
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//
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// $Date: 2001-09-07 15:34:38 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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//
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// Revision 1.3 2001/06/13 02:26:50 rudi
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//
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//
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// Small changes after running lint.
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//
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// Revision 1.2 2001/06/05 10:22:37 rudi
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//
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//
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// - Added Support of up to 31 channels
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// - Added support for 2,4 and 8 priority levels
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// - Now can have up to 31 channels
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// - Added many configuration items
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// - Changed reset to async
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//
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// Revision 1.1.1.1 2001/03/19 13:10:23 rudi
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// Initial Release
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//
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//
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//
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`include "wb_dma_defines.v"
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module wb_dma_top(clk_i, rst_i,
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wb0s_data_i, wb0s_data_o, wb0_addr_i, wb0_sel_i, wb0_we_i, wb0_cyc_i,
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wb0_stb_i, wb0_ack_o, wb0_err_o, wb0_rty_o,
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wb0m_data_i, wb0m_data_o, wb0_addr_o, wb0_sel_o, wb0_we_o, wb0_cyc_o,
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wb0_stb_o, wb0_ack_i, wb0_err_i, wb0_rty_i,
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wb1s_data_i, wb1s_data_o, wb1_addr_i, wb1_sel_i, wb1_we_i, wb1_cyc_i,
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wb1_stb_i, wb1_ack_o, wb1_err_o, wb1_rty_o,
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wb1m_data_i, wb1m_data_o, wb1_addr_o, wb1_sel_o, wb1_we_o, wb1_cyc_o,
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wb1_stb_o, wb1_ack_i, wb1_err_i, wb1_rty_i,
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dma_req_i, dma_ack_o, dma_nd_i, dma_rest_i,
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inta_o, intb_o
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);
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input clk_i, rst_i;
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// --------------------------------------
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// WISHBONE INTERFACE 0
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// Slave Interface
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input [31:0] wb0s_data_i;
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output [31:0] wb0s_data_o;
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input [31:0] wb0_addr_i;
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input [3:0] wb0_sel_i;
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input wb0_we_i;
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input wb0_cyc_i;
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input wb0_stb_i;
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output wb0_ack_o;
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output wb0_err_o;
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output wb0_rty_o;
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// Master Interface
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input [31:0] wb0m_data_i;
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output [31:0] wb0m_data_o;
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output [31:0] wb0_addr_o;
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output [3:0] wb0_sel_o;
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output wb0_we_o;
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output wb0_cyc_o;
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output wb0_stb_o;
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input wb0_ack_i;
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input wb0_err_i;
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input wb0_rty_i;
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// --------------------------------------
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// WISHBONE INTERFACE 1
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// Slave Interface
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input [31:0] wb1s_data_i;
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output [31:0] wb1s_data_o;
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input [31:0] wb1_addr_i;
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input [3:0] wb1_sel_i;
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input wb1_we_i;
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input wb1_cyc_i;
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input wb1_stb_i;
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output wb1_ack_o;
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output wb1_err_o;
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output wb1_rty_o;
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// Master Interface
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input [31:0] wb1m_data_i;
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output [31:0] wb1m_data_o;
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output [31:0] wb1_addr_o;
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output [3:0] wb1_sel_o;
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output wb1_we_o;
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output wb1_cyc_o;
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output wb1_stb_o;
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input wb1_ack_i;
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input wb1_err_i;
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input wb1_rty_i;
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// --------------------------------------
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// Misc Signals
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input [`WDMA_CH_COUNT-1:0] dma_req_i;
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input [`WDMA_CH_COUNT-1:0] dma_nd_i;
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output [`WDMA_CH_COUNT-1:0] dma_ack_o;
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input [`WDMA_CH_COUNT-1:0] dma_rest_i;
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output inta_o;
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output intb_o;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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wire [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;
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wire [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;
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wire [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;
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wire [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;
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wire [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;
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wire [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;
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wire [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;
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wire [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;
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wire [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;
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wire [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;
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wire [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;
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wire [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;
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wire [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;
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wire [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;
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wire [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;
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wire [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;
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wire [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;
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wire [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;
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wire [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;
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wire [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;
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wire [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;
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wire [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;
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wire [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;
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wire [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;
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wire [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;
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wire [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;
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wire [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;
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wire [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;
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wire [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;
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wire [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;
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wire [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;
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wire [4:0] ch_sel; // Write Back Channel Select
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wire [30:0] ndnr; // Next Descriptor No Request
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wire de_start; // Start DMA Engine
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wire ndr; // Next Descriptor With Request
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wire [31:0] csr; // Selected Channel CSR
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wire [31:0] pointer;
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wire [31:0] pointer_s;
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wire [31:0] txsz; // Selected Channel Transfer Size
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wire [31:0] adr0, adr1; // Selected Channel Addresses
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wire [31:0] am0, am1; // Selected Channel Address Masks
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wire next_ch; // Indicates the DMA Engine is done
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wire inta_o, intb_o;
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wire dma_abort;
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wire dma_busy, dma_err, dma_done, dma_done_all;
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wire [31:0] de_csr;
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wire [11:0] de_txsz;
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wire [31:0] de_adr0;
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wire [31:0] de_adr1;
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wire de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we;
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wire de_fetch_descr;
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wire ptr_set;
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wire de_ack;
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wire pause_req;
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wire paused;
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wire mast0_go; // Perform a Master Cycle (as long as this
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wire mast0_we; // Read/Write
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wire [31:0] mast0_adr; // Address for the transfer
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wire [31:0] mast0_din; // Internal Input Data
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wire [31:0] mast0_dout; // Internal Output Data
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wire mast0_err; // Indicates an error has occurred
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wire mast0_drdy; // Indicated that either data is available
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wire mast0_wait; // Tells the master to insert wait cycles
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wire [31:0] slv0_adr; // Slave Address
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wire [31:0] slv0_din; // Slave Input Data
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wire [31:0] slv0_dout; // Slave Output Data
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wire slv0_re; // Slave Read Enable
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wire slv0_we; // Slave Write Enable
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wire pt0_sel_i; // Pass Through Mode Selected
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wire [70:0] mast0_pt_in; // Grouped WISHBONE inputs
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wire [34:0] mast0_pt_out; // Grouped WISHBONE outputs
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wire pt0_sel_o; // Pass Through Mode Active
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wire [70:0] slv0_pt_out; // Grouped WISHBONE out signals
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wire [34:0] slv0_pt_in; // Grouped WISHBONE in signals
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wire mast1_go; // Perform a Master Cycle (as long as this
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wire mast1_we; // Read/Write
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wire [31:0] mast1_adr; // Address for the transfer
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wire [31:0] mast1_din; // Internal Input Data
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256 |
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wire [31:0] mast1_dout; // Internal Output Data
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wire mast1_err; // Indicates an error has occurred
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wire mast1_drdy; // Indicated that either data is available
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wire mast1_wait; // Tells the master to insert wait cycles
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260 |
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wire [31:0] slv1_adr; // Slave Address
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wire [31:0] slv1_dout; // Slave Output Data
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wire slv1_re; // Slave Read Enable
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264 |
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wire slv1_we; // Slave Write Enable
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265 |
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wire pt1_sel_i; // Pass Through Mode Selected
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wire [70:0] mast1_pt_in; // Grouped WISHBONE inputs
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wire [34:0] mast1_pt_out; // Grouped WISHBONE outputs
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269 |
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wire pt1_sel_o; // Pass Through Mode Active
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wire [70:0] slv1_pt_out; // Grouped WISHBONE out signals
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wire [34:0] slv1_pt_in; // Grouped WISHBONE in signals
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273 |
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274 |
|
|
wire [30:0] dma_req;
|
275 |
|
|
wire [30:0] dma_nd;
|
276 |
|
|
wire [30:0] dma_ack;
|
277 |
|
|
wire [30:0] dma_rest;
|
278 |
|
|
|
279 |
|
|
////////////////////////////////////////////////////////////////////
|
280 |
|
|
//
|
281 |
|
|
// Misc Logic
|
282 |
|
|
//
|
283 |
|
|
|
284 |
8 |
rudi |
assign dma_req[`WDMA_CH_COUNT-1:0] = dma_req_i;
|
285 |
|
|
assign dma_nd[`WDMA_CH_COUNT-1:0] = dma_nd_i;
|
286 |
|
|
assign dma_rest[`WDMA_CH_COUNT-1:0] = dma_rest_i;
|
287 |
|
|
assign dma_ack_o = dma_ack[`WDMA_CH_COUNT-1:0];
|
288 |
5 |
rudi |
|
289 |
|
|
// --------------------------------------------------
|
290 |
|
|
// This should go in to a separate Pass Through Block
|
291 |
|
|
assign pt1_sel_i = pt0_sel_o;
|
292 |
|
|
assign pt0_sel_i = pt1_sel_o;
|
293 |
|
|
assign mast1_pt_in = slv0_pt_out;
|
294 |
|
|
assign slv0_pt_in = mast1_pt_out;
|
295 |
|
|
assign mast0_pt_in = slv1_pt_out;
|
296 |
|
|
assign slv1_pt_in = mast0_pt_out;
|
297 |
|
|
// --------------------------------------------------
|
298 |
|
|
|
299 |
|
|
////////////////////////////////////////////////////////////////////
|
300 |
|
|
//
|
301 |
|
|
// Modules
|
302 |
|
|
//
|
303 |
|
|
|
304 |
|
|
|
305 |
|
|
// DMA Register File
|
306 |
|
|
|
307 |
|
|
wb_dma_rf u0(
|
308 |
8 |
rudi |
.clk( clk_i ),
|
309 |
9 |
rudi |
.rst( ~rst_i ),
|
310 |
5 |
rudi |
.wb_rf_adr( slv0_adr[9:2] ),
|
311 |
|
|
.wb_rf_din( slv0_dout ),
|
312 |
|
|
.wb_rf_dout( slv0_din ),
|
313 |
|
|
.wb_rf_re( slv0_re ),
|
314 |
|
|
.wb_rf_we( slv0_we ),
|
315 |
|
|
.inta_o( inta_o ),
|
316 |
|
|
.intb_o( intb_o ),
|
317 |
|
|
.pointer0( pointer0 ),
|
318 |
|
|
.pointer0_s( pointer0_s ),
|
319 |
|
|
.ch0_csr( ch0_csr ),
|
320 |
|
|
.ch0_txsz( ch0_txsz ),
|
321 |
|
|
.ch0_adr0( ch0_adr0 ),
|
322 |
|
|
.ch0_adr1( ch0_adr1 ),
|
323 |
|
|
.ch0_am0( ch0_am0 ),
|
324 |
|
|
.ch0_am1( ch0_am1 ),
|
325 |
|
|
.pointer1( pointer1 ),
|
326 |
|
|
.pointer1_s( pointer1_s ),
|
327 |
|
|
.ch1_csr( ch1_csr ),
|
328 |
|
|
.ch1_txsz( ch1_txsz ),
|
329 |
|
|
.ch1_adr0( ch1_adr0 ),
|
330 |
|
|
.ch1_adr1( ch1_adr1 ),
|
331 |
|
|
.ch1_am0( ch1_am0 ),
|
332 |
|
|
.ch1_am1( ch1_am1 ),
|
333 |
|
|
.pointer2( pointer2 ),
|
334 |
|
|
.pointer2_s( pointer2_s ),
|
335 |
|
|
.ch2_csr( ch2_csr ),
|
336 |
|
|
.ch2_txsz( ch2_txsz ),
|
337 |
|
|
.ch2_adr0( ch2_adr0 ),
|
338 |
|
|
.ch2_adr1( ch2_adr1 ),
|
339 |
|
|
.ch2_am0( ch2_am0 ),
|
340 |
|
|
.ch2_am1( ch2_am1 ),
|
341 |
|
|
.pointer3( pointer3 ),
|
342 |
|
|
.pointer3_s( pointer3_s ),
|
343 |
|
|
.ch3_csr( ch3_csr ),
|
344 |
|
|
.ch3_txsz( ch3_txsz ),
|
345 |
|
|
.ch3_adr0( ch3_adr0 ),
|
346 |
|
|
.ch3_adr1( ch3_adr1 ),
|
347 |
|
|
.ch3_am0( ch3_am0 ),
|
348 |
|
|
.ch3_am1( ch3_am1 ),
|
349 |
|
|
.pointer4( pointer4 ),
|
350 |
|
|
.pointer4_s( pointer4_s ),
|
351 |
|
|
.ch4_csr( ch4_csr ),
|
352 |
|
|
.ch4_txsz( ch4_txsz ),
|
353 |
|
|
.ch4_adr0( ch4_adr0 ),
|
354 |
|
|
.ch4_adr1( ch4_adr1 ),
|
355 |
|
|
.ch4_am0( ch4_am0 ),
|
356 |
|
|
.ch4_am1( ch4_am1 ),
|
357 |
|
|
.pointer5( pointer5 ),
|
358 |
|
|
.pointer5_s( pointer5_s ),
|
359 |
|
|
.ch5_csr( ch5_csr ),
|
360 |
|
|
.ch5_txsz( ch5_txsz ),
|
361 |
|
|
.ch5_adr0( ch5_adr0 ),
|
362 |
|
|
.ch5_adr1( ch5_adr1 ),
|
363 |
|
|
.ch5_am0( ch5_am0 ),
|
364 |
|
|
.ch5_am1( ch5_am1 ),
|
365 |
|
|
.pointer6( pointer6 ),
|
366 |
|
|
.pointer6_s( pointer6_s ),
|
367 |
|
|
.ch6_csr( ch6_csr ),
|
368 |
|
|
.ch6_txsz( ch6_txsz ),
|
369 |
|
|
.ch6_adr0( ch6_adr0 ),
|
370 |
|
|
.ch6_adr1( ch6_adr1 ),
|
371 |
|
|
.ch6_am0( ch6_am0 ),
|
372 |
|
|
.ch6_am1( ch6_am1 ),
|
373 |
|
|
.pointer7( pointer7 ),
|
374 |
|
|
.pointer7_s( pointer7_s ),
|
375 |
|
|
.ch7_csr( ch7_csr ),
|
376 |
|
|
.ch7_txsz( ch7_txsz ),
|
377 |
|
|
.ch7_adr0( ch7_adr0 ),
|
378 |
|
|
.ch7_adr1( ch7_adr1 ),
|
379 |
|
|
.ch7_am0( ch7_am0 ),
|
380 |
|
|
.ch7_am1( ch7_am1 ),
|
381 |
|
|
.pointer8( pointer8 ),
|
382 |
|
|
.pointer8_s( pointer8_s ),
|
383 |
|
|
.ch8_csr( ch8_csr ),
|
384 |
|
|
.ch8_txsz( ch8_txsz ),
|
385 |
|
|
.ch8_adr0( ch8_adr0 ),
|
386 |
|
|
.ch8_adr1( ch8_adr1 ),
|
387 |
|
|
.ch8_am0( ch8_am0 ),
|
388 |
|
|
.ch8_am1( ch8_am1 ),
|
389 |
|
|
.pointer9( pointer9 ),
|
390 |
|
|
.pointer9_s( pointer9_s ),
|
391 |
|
|
.ch9_csr( ch9_csr ),
|
392 |
|
|
.ch9_txsz( ch9_txsz ),
|
393 |
|
|
.ch9_adr0( ch9_adr0 ),
|
394 |
|
|
.ch9_adr1( ch9_adr1 ),
|
395 |
|
|
.ch9_am0( ch9_am0 ),
|
396 |
|
|
.ch9_am1( ch9_am1 ),
|
397 |
|
|
.pointer10( pointer10 ),
|
398 |
|
|
.pointer10_s( pointer10_s ),
|
399 |
|
|
.ch10_csr( ch10_csr ),
|
400 |
|
|
.ch10_txsz( ch10_txsz ),
|
401 |
|
|
.ch10_adr0( ch10_adr0 ),
|
402 |
|
|
.ch10_adr1( ch10_adr1 ),
|
403 |
|
|
.ch10_am0( ch10_am0 ),
|
404 |
|
|
.ch10_am1( ch10_am1 ),
|
405 |
|
|
.pointer11( pointer11 ),
|
406 |
|
|
.pointer11_s( pointer11_s ),
|
407 |
|
|
.ch11_csr( ch11_csr ),
|
408 |
|
|
.ch11_txsz( ch11_txsz ),
|
409 |
|
|
.ch11_adr0( ch11_adr0 ),
|
410 |
|
|
.ch11_adr1( ch11_adr1 ),
|
411 |
|
|
.ch11_am0( ch11_am0 ),
|
412 |
|
|
.ch11_am1( ch11_am1 ),
|
413 |
|
|
.pointer12( pointer12 ),
|
414 |
|
|
.pointer12_s( pointer12_s ),
|
415 |
|
|
.ch12_csr( ch12_csr ),
|
416 |
|
|
.ch12_txsz( ch12_txsz ),
|
417 |
|
|
.ch12_adr0( ch12_adr0 ),
|
418 |
|
|
.ch12_adr1( ch12_adr1 ),
|
419 |
|
|
.ch12_am0( ch12_am0 ),
|
420 |
|
|
.ch12_am1( ch12_am1 ),
|
421 |
|
|
.pointer13( pointer13 ),
|
422 |
|
|
.pointer13_s( pointer13_s ),
|
423 |
|
|
.ch13_csr( ch13_csr ),
|
424 |
|
|
.ch13_txsz( ch13_txsz ),
|
425 |
|
|
.ch13_adr0( ch13_adr0 ),
|
426 |
|
|
.ch13_adr1( ch13_adr1 ),
|
427 |
|
|
.ch13_am0( ch13_am0 ),
|
428 |
|
|
.ch13_am1( ch13_am1 ),
|
429 |
|
|
.pointer14( pointer14 ),
|
430 |
|
|
.pointer14_s( pointer14_s ),
|
431 |
|
|
.ch14_csr( ch14_csr ),
|
432 |
|
|
.ch14_txsz( ch14_txsz ),
|
433 |
|
|
.ch14_adr0( ch14_adr0 ),
|
434 |
|
|
.ch14_adr1( ch14_adr1 ),
|
435 |
|
|
.ch14_am0( ch14_am0 ),
|
436 |
|
|
.ch14_am1( ch14_am1 ),
|
437 |
|
|
.pointer15( pointer15 ),
|
438 |
|
|
.pointer15_s( pointer15_s ),
|
439 |
|
|
.ch15_csr( ch15_csr ),
|
440 |
|
|
.ch15_txsz( ch15_txsz ),
|
441 |
|
|
.ch15_adr0( ch15_adr0 ),
|
442 |
|
|
.ch15_adr1( ch15_adr1 ),
|
443 |
|
|
.ch15_am0( ch15_am0 ),
|
444 |
|
|
.ch15_am1( ch15_am1 ),
|
445 |
|
|
.pointer16( pointer16 ),
|
446 |
|
|
.pointer16_s( pointer16_s ),
|
447 |
|
|
.ch16_csr( ch16_csr ),
|
448 |
|
|
.ch16_txsz( ch16_txsz ),
|
449 |
|
|
.ch16_adr0( ch16_adr0 ),
|
450 |
|
|
.ch16_adr1( ch16_adr1 ),
|
451 |
|
|
.ch16_am0( ch16_am0 ),
|
452 |
|
|
.ch16_am1( ch16_am1 ),
|
453 |
|
|
.pointer17( pointer17 ),
|
454 |
|
|
.pointer17_s( pointer17_s ),
|
455 |
|
|
.ch17_csr( ch17_csr ),
|
456 |
|
|
.ch17_txsz( ch17_txsz ),
|
457 |
|
|
.ch17_adr0( ch17_adr0 ),
|
458 |
|
|
.ch17_adr1( ch17_adr1 ),
|
459 |
|
|
.ch17_am0( ch17_am0 ),
|
460 |
|
|
.ch17_am1( ch17_am1 ),
|
461 |
|
|
.pointer18( pointer18 ),
|
462 |
|
|
.pointer18_s( pointer18_s ),
|
463 |
|
|
.ch18_csr( ch18_csr ),
|
464 |
|
|
.ch18_txsz( ch18_txsz ),
|
465 |
|
|
.ch18_adr0( ch18_adr0 ),
|
466 |
|
|
.ch18_adr1( ch18_adr1 ),
|
467 |
|
|
.ch18_am0( ch18_am0 ),
|
468 |
|
|
.ch18_am1( ch18_am1 ),
|
469 |
|
|
.pointer19( pointer19 ),
|
470 |
|
|
.pointer19_s( pointer19_s ),
|
471 |
|
|
.ch19_csr( ch19_csr ),
|
472 |
|
|
.ch19_txsz( ch19_txsz ),
|
473 |
|
|
.ch19_adr0( ch19_adr0 ),
|
474 |
|
|
.ch19_adr1( ch19_adr1 ),
|
475 |
|
|
.ch19_am0( ch19_am0 ),
|
476 |
|
|
.ch19_am1( ch19_am1 ),
|
477 |
|
|
.pointer20( pointer20 ),
|
478 |
|
|
.pointer20_s( pointer20_s ),
|
479 |
|
|
.ch20_csr( ch20_csr ),
|
480 |
|
|
.ch20_txsz( ch20_txsz ),
|
481 |
|
|
.ch20_adr0( ch20_adr0 ),
|
482 |
|
|
.ch20_adr1( ch20_adr1 ),
|
483 |
|
|
.ch20_am0( ch20_am0 ),
|
484 |
|
|
.ch20_am1( ch20_am1 ),
|
485 |
|
|
.pointer21( pointer21 ),
|
486 |
|
|
.pointer21_s( pointer21_s ),
|
487 |
|
|
.ch21_csr( ch21_csr ),
|
488 |
|
|
.ch21_txsz( ch21_txsz ),
|
489 |
|
|
.ch21_adr0( ch21_adr0 ),
|
490 |
|
|
.ch21_adr1( ch21_adr1 ),
|
491 |
|
|
.ch21_am0( ch21_am0 ),
|
492 |
|
|
.ch21_am1( ch21_am1 ),
|
493 |
|
|
.pointer22( pointer22 ),
|
494 |
|
|
.pointer22_s( pointer22_s ),
|
495 |
|
|
.ch22_csr( ch22_csr ),
|
496 |
|
|
.ch22_txsz( ch22_txsz ),
|
497 |
|
|
.ch22_adr0( ch22_adr0 ),
|
498 |
|
|
.ch22_adr1( ch22_adr1 ),
|
499 |
|
|
.ch22_am0( ch22_am0 ),
|
500 |
|
|
.ch22_am1( ch22_am1 ),
|
501 |
|
|
.pointer23( pointer23 ),
|
502 |
|
|
.pointer23_s( pointer23_s ),
|
503 |
|
|
.ch23_csr( ch23_csr ),
|
504 |
|
|
.ch23_txsz( ch23_txsz ),
|
505 |
|
|
.ch23_adr0( ch23_adr0 ),
|
506 |
|
|
.ch23_adr1( ch23_adr1 ),
|
507 |
|
|
.ch23_am0( ch23_am0 ),
|
508 |
|
|
.ch23_am1( ch23_am1 ),
|
509 |
|
|
.pointer24( pointer24 ),
|
510 |
|
|
.pointer24_s( pointer24_s ),
|
511 |
|
|
.ch24_csr( ch24_csr ),
|
512 |
|
|
.ch24_txsz( ch24_txsz ),
|
513 |
|
|
.ch24_adr0( ch24_adr0 ),
|
514 |
|
|
.ch24_adr1( ch24_adr1 ),
|
515 |
|
|
.ch24_am0( ch24_am0 ),
|
516 |
|
|
.ch24_am1( ch24_am1 ),
|
517 |
|
|
.pointer25( pointer25 ),
|
518 |
|
|
.pointer25_s( pointer25_s ),
|
519 |
|
|
.ch25_csr( ch25_csr ),
|
520 |
|
|
.ch25_txsz( ch25_txsz ),
|
521 |
|
|
.ch25_adr0( ch25_adr0 ),
|
522 |
|
|
.ch25_adr1( ch25_adr1 ),
|
523 |
|
|
.ch25_am0( ch25_am0 ),
|
524 |
|
|
.ch25_am1( ch25_am1 ),
|
525 |
|
|
.pointer26( pointer26 ),
|
526 |
|
|
.pointer26_s( pointer26_s ),
|
527 |
|
|
.ch26_csr( ch26_csr ),
|
528 |
|
|
.ch26_txsz( ch26_txsz ),
|
529 |
|
|
.ch26_adr0( ch26_adr0 ),
|
530 |
|
|
.ch26_adr1( ch26_adr1 ),
|
531 |
|
|
.ch26_am0( ch26_am0 ),
|
532 |
|
|
.ch26_am1( ch26_am1 ),
|
533 |
|
|
.pointer27( pointer27 ),
|
534 |
|
|
.pointer27_s( pointer27_s ),
|
535 |
|
|
.ch27_csr( ch27_csr ),
|
536 |
|
|
.ch27_txsz( ch27_txsz ),
|
537 |
|
|
.ch27_adr0( ch27_adr0 ),
|
538 |
|
|
.ch27_adr1( ch27_adr1 ),
|
539 |
|
|
.ch27_am0( ch27_am0 ),
|
540 |
|
|
.ch27_am1( ch27_am1 ),
|
541 |
|
|
.pointer28( pointer28 ),
|
542 |
|
|
.pointer28_s( pointer28_s ),
|
543 |
|
|
.ch28_csr( ch28_csr ),
|
544 |
|
|
.ch28_txsz( ch28_txsz ),
|
545 |
|
|
.ch28_adr0( ch28_adr0 ),
|
546 |
|
|
.ch28_adr1( ch28_adr1 ),
|
547 |
|
|
.ch28_am0( ch28_am0 ),
|
548 |
|
|
.ch28_am1( ch28_am1 ),
|
549 |
|
|
.pointer29( pointer29 ),
|
550 |
|
|
.pointer29_s( pointer29_s ),
|
551 |
|
|
.ch29_csr( ch29_csr ),
|
552 |
|
|
.ch29_txsz( ch29_txsz ),
|
553 |
|
|
.ch29_adr0( ch29_adr0 ),
|
554 |
|
|
.ch29_adr1( ch29_adr1 ),
|
555 |
|
|
.ch29_am0( ch29_am0 ),
|
556 |
|
|
.ch29_am1( ch29_am1 ),
|
557 |
|
|
.pointer30( pointer30 ),
|
558 |
|
|
.pointer30_s( pointer30_s ),
|
559 |
|
|
.ch30_csr( ch30_csr ),
|
560 |
|
|
.ch30_txsz( ch30_txsz ),
|
561 |
|
|
.ch30_adr0( ch30_adr0 ),
|
562 |
|
|
.ch30_adr1( ch30_adr1 ),
|
563 |
|
|
.ch30_am0( ch30_am0 ),
|
564 |
|
|
.ch30_am1( ch30_am1 ),
|
565 |
|
|
.ch_sel( ch_sel ),
|
566 |
|
|
.ndnr( ndnr ),
|
567 |
|
|
.pause_req( pause_req ),
|
568 |
|
|
.paused( paused ),
|
569 |
|
|
.dma_abort( dma_abort ),
|
570 |
|
|
.dma_busy( dma_busy ),
|
571 |
|
|
.dma_err( dma_err ),
|
572 |
|
|
.dma_done( dma_done ),
|
573 |
|
|
.dma_done_all( dma_done_all ),
|
574 |
|
|
.de_csr( de_csr ),
|
575 |
|
|
.de_txsz( de_txsz ),
|
576 |
|
|
.de_adr0( de_adr0 ),
|
577 |
|
|
.de_adr1( de_adr1 ),
|
578 |
|
|
.de_csr_we( de_csr_we ),
|
579 |
|
|
.de_txsz_we( de_txsz_we ),
|
580 |
|
|
.de_adr0_we( de_adr0_we ),
|
581 |
|
|
.de_adr1_we( de_adr1_we ),
|
582 |
|
|
.de_fetch_descr(de_fetch_descr ),
|
583 |
|
|
.dma_rest( dma_rest ),
|
584 |
|
|
.ptr_set( ptr_set )
|
585 |
|
|
);
|
586 |
|
|
|
587 |
|
|
// Channel Select
|
588 |
|
|
wb_dma_ch_sel u1(
|
589 |
8 |
rudi |
.clk( clk_i ),
|
590 |
9 |
rudi |
.rst( ~rst_i ),
|
591 |
5 |
rudi |
.req_i( dma_req ),
|
592 |
|
|
.ack_o( dma_ack ),
|
593 |
|
|
.nd_i( dma_nd ),
|
594 |
|
|
|
595 |
|
|
.pointer0( pointer0 ),
|
596 |
|
|
.pointer0_s( pointer0_s ),
|
597 |
|
|
.ch0_csr( ch0_csr ),
|
598 |
|
|
.ch0_txsz( ch0_txsz ),
|
599 |
|
|
.ch0_adr0( ch0_adr0 ),
|
600 |
|
|
.ch0_adr1( ch0_adr1 ),
|
601 |
|
|
.ch0_am0( ch0_am0 ),
|
602 |
|
|
.ch0_am1( ch0_am1 ),
|
603 |
|
|
.pointer1( pointer1 ),
|
604 |
|
|
.pointer1_s( pointer1_s ),
|
605 |
|
|
.ch1_csr( ch1_csr ),
|
606 |
|
|
.ch1_txsz( ch1_txsz ),
|
607 |
|
|
.ch1_adr0( ch1_adr0 ),
|
608 |
|
|
.ch1_adr1( ch1_adr1 ),
|
609 |
|
|
.ch1_am0( ch1_am0 ),
|
610 |
|
|
.ch1_am1( ch1_am1 ),
|
611 |
|
|
.pointer2( pointer2 ),
|
612 |
|
|
.pointer2_s( pointer2_s ),
|
613 |
|
|
.ch2_csr( ch2_csr ),
|
614 |
|
|
.ch2_txsz( ch2_txsz ),
|
615 |
|
|
.ch2_adr0( ch2_adr0 ),
|
616 |
|
|
.ch2_adr1( ch2_adr1 ),
|
617 |
|
|
.ch2_am0( ch2_am0 ),
|
618 |
|
|
.ch2_am1( ch2_am1 ),
|
619 |
|
|
.pointer3( pointer3 ),
|
620 |
|
|
.pointer3_s( pointer3_s ),
|
621 |
|
|
.ch3_csr( ch3_csr ),
|
622 |
|
|
.ch3_txsz( ch3_txsz ),
|
623 |
|
|
.ch3_adr0( ch3_adr0 ),
|
624 |
|
|
.ch3_adr1( ch3_adr1 ),
|
625 |
|
|
.ch3_am0( ch3_am0 ),
|
626 |
|
|
.ch3_am1( ch3_am1 ),
|
627 |
|
|
.pointer4( pointer4 ),
|
628 |
|
|
.pointer4_s( pointer4_s ),
|
629 |
|
|
.ch4_csr( ch4_csr ),
|
630 |
|
|
.ch4_txsz( ch4_txsz ),
|
631 |
|
|
.ch4_adr0( ch4_adr0 ),
|
632 |
|
|
.ch4_adr1( ch4_adr1 ),
|
633 |
|
|
.ch4_am0( ch4_am0 ),
|
634 |
|
|
.ch4_am1( ch4_am1 ),
|
635 |
|
|
.pointer5( pointer5 ),
|
636 |
|
|
.pointer5_s( pointer5_s ),
|
637 |
|
|
.ch5_csr( ch5_csr ),
|
638 |
|
|
.ch5_txsz( ch5_txsz ),
|
639 |
|
|
.ch5_adr0( ch5_adr0 ),
|
640 |
|
|
.ch5_adr1( ch5_adr1 ),
|
641 |
|
|
.ch5_am0( ch5_am0 ),
|
642 |
|
|
.ch5_am1( ch5_am1 ),
|
643 |
|
|
.pointer6( pointer6 ),
|
644 |
|
|
.pointer6_s( pointer6_s ),
|
645 |
|
|
.ch6_csr( ch6_csr ),
|
646 |
|
|
.ch6_txsz( ch6_txsz ),
|
647 |
|
|
.ch6_adr0( ch6_adr0 ),
|
648 |
|
|
.ch6_adr1( ch6_adr1 ),
|
649 |
|
|
.ch6_am0( ch6_am0 ),
|
650 |
|
|
.ch6_am1( ch6_am1 ),
|
651 |
|
|
.pointer7( pointer7 ),
|
652 |
|
|
.pointer7_s( pointer7_s ),
|
653 |
|
|
.ch7_csr( ch7_csr ),
|
654 |
|
|
.ch7_txsz( ch7_txsz ),
|
655 |
|
|
.ch7_adr0( ch7_adr0 ),
|
656 |
|
|
.ch7_adr1( ch7_adr1 ),
|
657 |
|
|
.ch7_am0( ch7_am0 ),
|
658 |
|
|
.ch7_am1( ch7_am1 ),
|
659 |
|
|
.pointer8( pointer8 ),
|
660 |
|
|
.pointer8_s( pointer8_s ),
|
661 |
|
|
.ch8_csr( ch8_csr ),
|
662 |
|
|
.ch8_txsz( ch8_txsz ),
|
663 |
|
|
.ch8_adr0( ch8_adr0 ),
|
664 |
|
|
.ch8_adr1( ch8_adr1 ),
|
665 |
|
|
.ch8_am0( ch8_am0 ),
|
666 |
|
|
.ch8_am1( ch8_am1 ),
|
667 |
|
|
.pointer9( pointer9 ),
|
668 |
|
|
.pointer9_s( pointer9_s ),
|
669 |
|
|
.ch9_csr( ch9_csr ),
|
670 |
|
|
.ch9_txsz( ch9_txsz ),
|
671 |
|
|
.ch9_adr0( ch9_adr0 ),
|
672 |
|
|
.ch9_adr1( ch9_adr1 ),
|
673 |
|
|
.ch9_am0( ch9_am0 ),
|
674 |
|
|
.ch9_am1( ch9_am1 ),
|
675 |
|
|
.pointer10( pointer10 ),
|
676 |
|
|
.pointer10_s( pointer10_s ),
|
677 |
|
|
.ch10_csr( ch10_csr ),
|
678 |
|
|
.ch10_txsz( ch10_txsz ),
|
679 |
|
|
.ch10_adr0( ch10_adr0 ),
|
680 |
|
|
.ch10_adr1( ch10_adr1 ),
|
681 |
|
|
.ch10_am0( ch10_am0 ),
|
682 |
|
|
.ch10_am1( ch10_am1 ),
|
683 |
|
|
.pointer11( pointer11 ),
|
684 |
|
|
.pointer11_s( pointer11_s ),
|
685 |
|
|
.ch11_csr( ch11_csr ),
|
686 |
|
|
.ch11_txsz( ch11_txsz ),
|
687 |
|
|
.ch11_adr0( ch11_adr0 ),
|
688 |
|
|
.ch11_adr1( ch11_adr1 ),
|
689 |
|
|
.ch11_am0( ch11_am0 ),
|
690 |
|
|
.ch11_am1( ch11_am1 ),
|
691 |
|
|
.pointer12( pointer12 ),
|
692 |
|
|
.pointer12_s( pointer12_s ),
|
693 |
|
|
.ch12_csr( ch12_csr ),
|
694 |
|
|
.ch12_txsz( ch12_txsz ),
|
695 |
|
|
.ch12_adr0( ch12_adr0 ),
|
696 |
|
|
.ch12_adr1( ch12_adr1 ),
|
697 |
|
|
.ch12_am0( ch12_am0 ),
|
698 |
|
|
.ch12_am1( ch12_am1 ),
|
699 |
|
|
.pointer13( pointer13 ),
|
700 |
|
|
.pointer13_s( pointer13_s ),
|
701 |
|
|
.ch13_csr( ch13_csr ),
|
702 |
|
|
.ch13_txsz( ch13_txsz ),
|
703 |
|
|
.ch13_adr0( ch13_adr0 ),
|
704 |
|
|
.ch13_adr1( ch13_adr1 ),
|
705 |
|
|
.ch13_am0( ch13_am0 ),
|
706 |
|
|
.ch13_am1( ch13_am1 ),
|
707 |
|
|
.pointer14( pointer14 ),
|
708 |
|
|
.pointer14_s( pointer14_s ),
|
709 |
|
|
.ch14_csr( ch14_csr ),
|
710 |
|
|
.ch14_txsz( ch14_txsz ),
|
711 |
|
|
.ch14_adr0( ch14_adr0 ),
|
712 |
|
|
.ch14_adr1( ch14_adr1 ),
|
713 |
|
|
.ch14_am0( ch14_am0 ),
|
714 |
|
|
.ch14_am1( ch14_am1 ),
|
715 |
|
|
.pointer15( pointer15 ),
|
716 |
|
|
.pointer15_s( pointer15_s ),
|
717 |
|
|
.ch15_csr( ch15_csr ),
|
718 |
|
|
.ch15_txsz( ch15_txsz ),
|
719 |
|
|
.ch15_adr0( ch15_adr0 ),
|
720 |
|
|
.ch15_adr1( ch15_adr1 ),
|
721 |
|
|
.ch15_am0( ch15_am0 ),
|
722 |
|
|
.ch15_am1( ch15_am1 ),
|
723 |
|
|
.pointer16( pointer16 ),
|
724 |
|
|
.pointer16_s( pointer16_s ),
|
725 |
|
|
.ch16_csr( ch16_csr ),
|
726 |
|
|
.ch16_txsz( ch16_txsz ),
|
727 |
|
|
.ch16_adr0( ch16_adr0 ),
|
728 |
|
|
.ch16_adr1( ch16_adr1 ),
|
729 |
|
|
.ch16_am0( ch16_am0 ),
|
730 |
|
|
.ch16_am1( ch16_am1 ),
|
731 |
|
|
.pointer17( pointer17 ),
|
732 |
|
|
.pointer17_s( pointer17_s ),
|
733 |
|
|
.ch17_csr( ch17_csr ),
|
734 |
|
|
.ch17_txsz( ch17_txsz ),
|
735 |
|
|
.ch17_adr0( ch17_adr0 ),
|
736 |
|
|
.ch17_adr1( ch17_adr1 ),
|
737 |
|
|
.ch17_am0( ch17_am0 ),
|
738 |
|
|
.ch17_am1( ch17_am1 ),
|
739 |
|
|
.pointer18( pointer18 ),
|
740 |
|
|
.pointer18_s( pointer18_s ),
|
741 |
|
|
.ch18_csr( ch18_csr ),
|
742 |
|
|
.ch18_txsz( ch18_txsz ),
|
743 |
|
|
.ch18_adr0( ch18_adr0 ),
|
744 |
|
|
.ch18_adr1( ch18_adr1 ),
|
745 |
|
|
.ch18_am0( ch18_am0 ),
|
746 |
|
|
.ch18_am1( ch18_am1 ),
|
747 |
|
|
.pointer19( pointer19 ),
|
748 |
|
|
.pointer19_s( pointer19_s ),
|
749 |
|
|
.ch19_csr( ch19_csr ),
|
750 |
|
|
.ch19_txsz( ch19_txsz ),
|
751 |
|
|
.ch19_adr0( ch19_adr0 ),
|
752 |
|
|
.ch19_adr1( ch19_adr1 ),
|
753 |
|
|
.ch19_am0( ch19_am0 ),
|
754 |
|
|
.ch19_am1( ch19_am1 ),
|
755 |
|
|
.pointer20( pointer20 ),
|
756 |
|
|
.pointer20_s( pointer20_s ),
|
757 |
|
|
.ch20_csr( ch20_csr ),
|
758 |
|
|
.ch20_txsz( ch20_txsz ),
|
759 |
|
|
.ch20_adr0( ch20_adr0 ),
|
760 |
|
|
.ch20_adr1( ch20_adr1 ),
|
761 |
|
|
.ch20_am0( ch20_am0 ),
|
762 |
|
|
.ch20_am1( ch20_am1 ),
|
763 |
|
|
.pointer21( pointer21 ),
|
764 |
|
|
.pointer21_s( pointer21_s ),
|
765 |
|
|
.ch21_csr( ch21_csr ),
|
766 |
|
|
.ch21_txsz( ch21_txsz ),
|
767 |
|
|
.ch21_adr0( ch21_adr0 ),
|
768 |
|
|
.ch21_adr1( ch21_adr1 ),
|
769 |
|
|
.ch21_am0( ch21_am0 ),
|
770 |
|
|
.ch21_am1( ch21_am1 ),
|
771 |
|
|
.pointer22( pointer22 ),
|
772 |
|
|
.pointer22_s( pointer22_s ),
|
773 |
|
|
.ch22_csr( ch22_csr ),
|
774 |
|
|
.ch22_txsz( ch22_txsz ),
|
775 |
|
|
.ch22_adr0( ch22_adr0 ),
|
776 |
|
|
.ch22_adr1( ch22_adr1 ),
|
777 |
|
|
.ch22_am0( ch22_am0 ),
|
778 |
|
|
.ch22_am1( ch22_am1 ),
|
779 |
|
|
.pointer23( pointer23 ),
|
780 |
|
|
.pointer23_s( pointer23_s ),
|
781 |
|
|
.ch23_csr( ch23_csr ),
|
782 |
|
|
.ch23_txsz( ch23_txsz ),
|
783 |
|
|
.ch23_adr0( ch23_adr0 ),
|
784 |
|
|
.ch23_adr1( ch23_adr1 ),
|
785 |
|
|
.ch23_am0( ch23_am0 ),
|
786 |
|
|
.ch23_am1( ch23_am1 ),
|
787 |
|
|
.pointer24( pointer24 ),
|
788 |
|
|
.pointer24_s( pointer24_s ),
|
789 |
|
|
.ch24_csr( ch24_csr ),
|
790 |
|
|
.ch24_txsz( ch24_txsz ),
|
791 |
|
|
.ch24_adr0( ch24_adr0 ),
|
792 |
|
|
.ch24_adr1( ch24_adr1 ),
|
793 |
|
|
.ch24_am0( ch24_am0 ),
|
794 |
|
|
.ch24_am1( ch24_am1 ),
|
795 |
|
|
.pointer25( pointer25 ),
|
796 |
|
|
.pointer25_s( pointer25_s ),
|
797 |
|
|
.ch25_csr( ch25_csr ),
|
798 |
|
|
.ch25_txsz( ch25_txsz ),
|
799 |
|
|
.ch25_adr0( ch25_adr0 ),
|
800 |
|
|
.ch25_adr1( ch25_adr1 ),
|
801 |
|
|
.ch25_am0( ch25_am0 ),
|
802 |
|
|
.ch25_am1( ch25_am1 ),
|
803 |
|
|
.pointer26( pointer26 ),
|
804 |
|
|
.pointer26_s( pointer26_s ),
|
805 |
|
|
.ch26_csr( ch26_csr ),
|
806 |
|
|
.ch26_txsz( ch26_txsz ),
|
807 |
|
|
.ch26_adr0( ch26_adr0 ),
|
808 |
|
|
.ch26_adr1( ch26_adr1 ),
|
809 |
|
|
.ch26_am0( ch26_am0 ),
|
810 |
|
|
.ch26_am1( ch26_am1 ),
|
811 |
|
|
.pointer27( pointer27 ),
|
812 |
|
|
.pointer27_s( pointer27_s ),
|
813 |
|
|
.ch27_csr( ch27_csr ),
|
814 |
|
|
.ch27_txsz( ch27_txsz ),
|
815 |
|
|
.ch27_adr0( ch27_adr0 ),
|
816 |
|
|
.ch27_adr1( ch27_adr1 ),
|
817 |
|
|
.ch27_am0( ch27_am0 ),
|
818 |
|
|
.ch27_am1( ch27_am1 ),
|
819 |
|
|
.pointer28( pointer28 ),
|
820 |
|
|
.pointer28_s( pointer28_s ),
|
821 |
|
|
.ch28_csr( ch28_csr ),
|
822 |
|
|
.ch28_txsz( ch28_txsz ),
|
823 |
|
|
.ch28_adr0( ch28_adr0 ),
|
824 |
|
|
.ch28_adr1( ch28_adr1 ),
|
825 |
|
|
.ch28_am0( ch28_am0 ),
|
826 |
|
|
.ch28_am1( ch28_am1 ),
|
827 |
|
|
.pointer29( pointer29 ),
|
828 |
|
|
.pointer29_s( pointer29_s ),
|
829 |
|
|
.ch29_csr( ch29_csr ),
|
830 |
|
|
.ch29_txsz( ch29_txsz ),
|
831 |
|
|
.ch29_adr0( ch29_adr0 ),
|
832 |
|
|
.ch29_adr1( ch29_adr1 ),
|
833 |
|
|
.ch29_am0( ch29_am0 ),
|
834 |
|
|
.ch29_am1( ch29_am1 ),
|
835 |
|
|
.pointer30( pointer30 ),
|
836 |
|
|
.pointer30_s( pointer30_s ),
|
837 |
|
|
.ch30_csr( ch30_csr ),
|
838 |
|
|
.ch30_txsz( ch30_txsz ),
|
839 |
|
|
.ch30_adr0( ch30_adr0 ),
|
840 |
|
|
.ch30_adr1( ch30_adr1 ),
|
841 |
|
|
.ch30_am0( ch30_am0 ),
|
842 |
|
|
.ch30_am1( ch30_am1 ),
|
843 |
|
|
|
844 |
|
|
.ch_sel( ch_sel ),
|
845 |
|
|
.ndnr( ndnr ),
|
846 |
|
|
.de_start( de_start ),
|
847 |
|
|
.ndr( ndr ),
|
848 |
|
|
.csr( csr ),
|
849 |
|
|
.pointer( pointer ),
|
850 |
|
|
.txsz( txsz ),
|
851 |
|
|
.adr0( adr0 ),
|
852 |
|
|
.adr1( adr1 ),
|
853 |
|
|
.am0( am0 ),
|
854 |
|
|
.am1( am1 ),
|
855 |
|
|
.pointer_s( pointer_s ),
|
856 |
|
|
.next_ch( next_ch ),
|
857 |
|
|
.de_ack( de_ack ),
|
858 |
|
|
.dma_busy( dma_busy )
|
859 |
|
|
);
|
860 |
|
|
|
861 |
|
|
|
862 |
|
|
// DMA Engine
|
863 |
|
|
wb_dma_de u2(
|
864 |
8 |
rudi |
.clk( clk_i ),
|
865 |
9 |
rudi |
.rst( ~rst_i ),
|
866 |
5 |
rudi |
.mast0_go( mast0_go ),
|
867 |
|
|
.mast0_we( mast0_we ),
|
868 |
|
|
.mast0_adr( mast0_adr ),
|
869 |
|
|
.mast0_din( mast0_dout ),
|
870 |
|
|
.mast0_dout( mast0_din ),
|
871 |
|
|
.mast0_err( mast0_err ),
|
872 |
|
|
.mast0_drdy( mast0_drdy ),
|
873 |
|
|
.mast0_wait( mast0_wait ),
|
874 |
|
|
.mast1_go( mast1_go ),
|
875 |
|
|
.mast1_we( mast1_we ),
|
876 |
|
|
.mast1_adr( mast1_adr ),
|
877 |
|
|
.mast1_din( mast1_dout ),
|
878 |
|
|
.mast1_dout( mast1_din ),
|
879 |
|
|
.mast1_err( mast1_err ),
|
880 |
|
|
.mast1_drdy( mast1_drdy ),
|
881 |
|
|
.mast1_wait( mast1_wait ),
|
882 |
|
|
.de_start( de_start ),
|
883 |
|
|
.nd( ndr ),
|
884 |
|
|
.csr( csr ),
|
885 |
|
|
.pointer( pointer ),
|
886 |
|
|
.pointer_s( pointer_s ),
|
887 |
|
|
.txsz( txsz ),
|
888 |
|
|
.adr0( adr0 ),
|
889 |
|
|
.adr1( adr1 ),
|
890 |
|
|
.am0( am0 ),
|
891 |
|
|
.am1( am1 ),
|
892 |
|
|
.de_csr_we( de_csr_we ),
|
893 |
|
|
.de_txsz_we( de_txsz_we ),
|
894 |
|
|
.de_adr0_we( de_adr0_we ),
|
895 |
|
|
.de_adr1_we( de_adr1_we ),
|
896 |
|
|
.de_fetch_descr(de_fetch_descr ),
|
897 |
|
|
.ptr_set( ptr_set ),
|
898 |
|
|
.de_csr( de_csr ),
|
899 |
|
|
.de_txsz( de_txsz ),
|
900 |
|
|
.de_adr0( de_adr0 ),
|
901 |
|
|
.de_adr1( de_adr1 ),
|
902 |
|
|
.next_ch( next_ch ),
|
903 |
|
|
.de_ack( de_ack ),
|
904 |
|
|
.pause_req( pause_req ),
|
905 |
|
|
.paused( paused ),
|
906 |
|
|
.dma_abort( dma_abort ),
|
907 |
|
|
.dma_busy( dma_busy ),
|
908 |
|
|
.dma_err( dma_err ),
|
909 |
|
|
.dma_done( dma_done ),
|
910 |
|
|
.dma_done_all( dma_done_all )
|
911 |
|
|
);
|
912 |
|
|
|
913 |
|
|
// Wishbone Interface 0
|
914 |
|
|
wb_dma_wb_if u3(
|
915 |
8 |
rudi |
.clk( clk_i ),
|
916 |
9 |
rudi |
.rst( ~rst_i ),
|
917 |
5 |
rudi |
.wbs_data_i( wb0s_data_i ),
|
918 |
|
|
.wbs_data_o( wb0s_data_o ),
|
919 |
|
|
.wb_addr_i( wb0_addr_i ),
|
920 |
|
|
.wb_sel_i( wb0_sel_i ),
|
921 |
|
|
.wb_we_i( wb0_we_i ),
|
922 |
|
|
.wb_cyc_i( wb0_cyc_i ),
|
923 |
|
|
.wb_stb_i( wb0_stb_i ),
|
924 |
|
|
.wb_ack_o( wb0_ack_o ),
|
925 |
|
|
.wb_err_o( wb0_err_o ),
|
926 |
|
|
.wb_rty_o( wb0_rty_o ),
|
927 |
|
|
.wbm_data_i( wb0m_data_i ),
|
928 |
|
|
.wbm_data_o( wb0m_data_o ),
|
929 |
|
|
.wb_addr_o( wb0_addr_o ),
|
930 |
|
|
.wb_sel_o( wb0_sel_o ),
|
931 |
|
|
.wb_we_o( wb0_we_o ),
|
932 |
|
|
.wb_cyc_o( wb0_cyc_o ),
|
933 |
|
|
.wb_stb_o( wb0_stb_o ),
|
934 |
|
|
.wb_ack_i( wb0_ack_i ),
|
935 |
|
|
.wb_err_i( wb0_err_i ),
|
936 |
|
|
.wb_rty_i( wb0_rty_i ),
|
937 |
|
|
.mast_go( mast0_go ),
|
938 |
|
|
.mast_we( mast0_we ),
|
939 |
|
|
.mast_adr( mast0_adr ),
|
940 |
|
|
.mast_din( mast0_din ),
|
941 |
|
|
.mast_dout( mast0_dout ),
|
942 |
|
|
.mast_err( mast0_err ),
|
943 |
|
|
.mast_drdy( mast0_drdy ),
|
944 |
|
|
.mast_wait( mast0_wait ),
|
945 |
|
|
.pt_sel_i( pt0_sel_i ),
|
946 |
|
|
.mast_pt_in( mast0_pt_in ),
|
947 |
|
|
.mast_pt_out( mast0_pt_out ),
|
948 |
|
|
.slv_adr( slv0_adr ),
|
949 |
|
|
.slv_din( slv0_din ),
|
950 |
|
|
.slv_dout( slv0_dout ),
|
951 |
|
|
.slv_re( slv0_re ),
|
952 |
|
|
.slv_we( slv0_we ),
|
953 |
|
|
.pt_sel_o( pt0_sel_o ),
|
954 |
|
|
.slv_pt_out( slv0_pt_out ),
|
955 |
|
|
.slv_pt_in( slv0_pt_in )
|
956 |
|
|
);
|
957 |
|
|
|
958 |
|
|
// Wishbone Interface 1
|
959 |
|
|
wb_dma_wb_if u4(
|
960 |
8 |
rudi |
.clk( clk_i ),
|
961 |
9 |
rudi |
.rst( ~rst_i ),
|
962 |
5 |
rudi |
.wbs_data_i( wb1s_data_i ),
|
963 |
|
|
.wbs_data_o( wb1s_data_o ),
|
964 |
|
|
.wb_addr_i( wb1_addr_i ),
|
965 |
|
|
.wb_sel_i( wb1_sel_i ),
|
966 |
|
|
.wb_we_i( wb1_we_i ),
|
967 |
|
|
.wb_cyc_i( wb1_cyc_i ),
|
968 |
|
|
.wb_stb_i( wb1_stb_i ),
|
969 |
|
|
.wb_ack_o( wb1_ack_o ),
|
970 |
|
|
.wb_err_o( wb1_err_o ),
|
971 |
|
|
.wb_rty_o( wb1_rty_o ),
|
972 |
|
|
.wbm_data_i( wb1m_data_i ),
|
973 |
|
|
.wbm_data_o( wb1m_data_o ),
|
974 |
|
|
.wb_addr_o( wb1_addr_o ),
|
975 |
|
|
.wb_sel_o( wb1_sel_o ),
|
976 |
|
|
.wb_we_o( wb1_we_o ),
|
977 |
|
|
.wb_cyc_o( wb1_cyc_o ),
|
978 |
|
|
.wb_stb_o( wb1_stb_o ),
|
979 |
|
|
.wb_ack_i( wb1_ack_i ),
|
980 |
|
|
.wb_err_i( wb1_err_i ),
|
981 |
|
|
.wb_rty_i( wb1_rty_i ),
|
982 |
|
|
.mast_go( mast1_go ),
|
983 |
|
|
.mast_we( mast1_we ),
|
984 |
|
|
.mast_adr( mast1_adr ),
|
985 |
|
|
.mast_din( mast1_din ),
|
986 |
|
|
.mast_dout( mast1_dout ),
|
987 |
|
|
.mast_err( mast1_err ),
|
988 |
|
|
.mast_drdy( mast1_drdy ),
|
989 |
|
|
.mast_wait( mast1_wait ),
|
990 |
|
|
.pt_sel_i( pt1_sel_i ),
|
991 |
|
|
.mast_pt_in( mast1_pt_in ),
|
992 |
|
|
.mast_pt_out( mast1_pt_out ),
|
993 |
|
|
.slv_adr( slv1_adr ),
|
994 |
|
|
.slv_din( 32'h0 ), // Not Connected
|
995 |
|
|
.slv_dout( slv1_dout ), // Not Connected
|
996 |
|
|
.slv_re( slv1_re ), // Not Connected
|
997 |
|
|
.slv_we( slv1_we ), // Not Connected
|
998 |
|
|
.pt_sel_o( pt1_sel_o ),
|
999 |
|
|
.slv_pt_out( slv1_pt_out ),
|
1000 |
|
|
.slv_pt_in( slv1_pt_in )
|
1001 |
|
|
);
|
1002 |
|
|
|
1003 |
|
|
|
1004 |
|
|
endmodule
|