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URL https://opencores.org/ocsvn/wb_dma/wb_dma/trunk

Subversion Repositories wb_dma

[/] [wb_dma/] [trunk/] [sim/] [rtl_sim/] [bin/] [Makefile] - Blame information for rev 17

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Line No. Rev Author Line
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all:    sim
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SHELL = /bin/sh
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MS=-s
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##########################################################################
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#
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# DUT Sources
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#
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##########################################################################
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DUT_SRC_DIR=../../../rtl/verilog
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_TARGETS_=      $(DUT_SRC_DIR)/wb_dma_ch_pri_enc.v      \
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                $(DUT_SRC_DIR)/wb_dma_ch_arb.v          \
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                $(DUT_SRC_DIR)/wb_dma_pri_enc_sub.v     \
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                $(DUT_SRC_DIR)/wb_dma_ch_sel.v          \
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                $(DUT_SRC_DIR)/wb_dma_top.v             \
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                $(DUT_SRC_DIR)/wb_dma_ch_rf.v           \
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                $(DUT_SRC_DIR)/wb_dma_rf.v              \
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                $(DUT_SRC_DIR)/wb_dma_wb_if.v           \
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                $(DUT_SRC_DIR)/wb_dma_wb_mast.v         \
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                $(DUT_SRC_DIR)/wb_dma_wb_slv.v          \
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                $(DUT_SRC_DIR)/wb_dma_de.v              \
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                $(DUT_SRC_DIR)/wb_dma_inc30r.v
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##########################################################################
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#
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# Test Bench Sources
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#
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##########################################################################
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_TOP_=test
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TB_SRC_DIR=../../../bench/verilog
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_TB_=           $(TB_SRC_DIR)/test_bench_top.v          \
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                $(TB_SRC_DIR)/wb_slv_model.v            \
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                $(TB_SRC_DIR)/wb_mast_model.v
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##########################################################################
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#
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# Misc Variables
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#
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##########################################################################
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#INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
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#LOGF=-LOGFILE .nclog
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#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
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INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
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LOGF=-l .nclog
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UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
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GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v
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##########################################################################
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#
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# Make Targets
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#
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##########################################################################
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ss:
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        signalscan -do waves/waves.do -waves waves/waves.trn &
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simxl:
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        verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR)    \
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        $(_TARGETS_) $(_TB_)
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simw:
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        @$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
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sim:
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        ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_)      \
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                $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus  \
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                +ncuid+`hostname`
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gatew:
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        @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
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gate:
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        ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB)        \
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                $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS)    \
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                $(LOGF) +ncstatus +ncuid+`hostname`
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81 6 rudi
hal:
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        @echo ""
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        @echo "----- Running HAL ... ----------"
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        @hal    -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK  \
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                +incdir+$(DUT_SRC_DIR) $(_TARGETS_)
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        @echo "----- DONE ... ----------"
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clean:
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        rm -rf  ./waves/*.dsn ./waves/*.trn                     \
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                ncwork/inc* ncwork/.inc* ncverilog.key          \
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                ./verilog.* .nclog hal.log INCA_libs
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##########################################################################

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