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daniel.kho |
/*
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This file is part of the Memories project:
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http://opencores.org/project,wb_fifo
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Description
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FIFO memory model.
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To Do:
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG.
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library tauhop;
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--package fifoTypes is new tauhop.types generic map(t_data=>unsigned(31 downto 0));
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use tauhop.fifoTransactor.all;
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--library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
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--library tauhop; use tauhop.fifoTypes.all;
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entity fifo is
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generic(memoryDepth:positive);
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port(clk,reset:in std_ulogic;
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fifoInterface:inout t_fifoTransactor
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);
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end entity fifo;
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architecture rtl of fifo is
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type t_memory is array(memoryDepth-1 downto 0) of i_transactor.t_msg;
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signal memory:t_memory;
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signal ptr:natural range 0 to memoryDepth-1;
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signal i_writeRequest,i_readRequest:i_transactor.t_bfm;
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signal write,read:boolean;
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begin
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controller: process(reset,clk) is begin
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if reset then fifoInterface.readResponse.message<=(others=>'Z');
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elsif falling_edge(clk) then
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if fifoInterface.writeRequest.trigger xor i_writeRequest.trigger then
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memory(ptr)<=fifoInterface.writeRequest.message;
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end if;
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if fifoInterface.readRequest.trigger xor i_readRequest.trigger then
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fifoInterface.readResponse.message<=memory(ptr);
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end if;
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end if;
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end process controller;
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write<=fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
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read<=fifoInterface.readRequest.trigger xor i_readRequest.trigger;
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addrPointer: process(reset,clk) is begin
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if reset then ptr<=0;
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elsif falling_edge(clk) then
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/* Increment or decrement the address pointer only when write or read is HIGH;
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do nothing when both are HIGH or when both are LOW.
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*/
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if write xor read then
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if write then
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if ptr<memoryDepth-1 then ptr<=ptr+1; end if;
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end if;
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if read then
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if ptr>0 then ptr<=ptr-1; end if;
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end if;
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end if;
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end if;
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end process addrPointer;
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/* Registers and pipelines. */
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process(clk) is begin
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i_writeRequest<=fifoInterface.writeRequest;
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i_readRequest<=fifoInterface.readRequest;
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end process;
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fifoInterface.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoInterface.pctFilled'length);
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process(clk) is begin
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if rising_edge(clk) then
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fifoInterface.nearFull<=true when fifoInterface.pctFilled>=d"75" and fifoInterface.pctFilled<d"100" else false;
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fifoInterface.full<=true when fifoInterface.pctFilled=d"100" else false;
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fifoInterface.nearEmpty<=true when fifoInterface.pctFilled<=d"25" and fifoInterface.pctFilled>d"0" else false;
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fifoInterface.empty<=true when fifoInterface.pctFilled=d"0" else false;
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end if;
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end process;
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process(clk) is begin
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if falling_edge(clk) then
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fifoInterface.overflow<=fifoInterface.full and write;
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fifoInterface.underflow<=fifoInterface.empty and read;
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end if;
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end process;
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end architecture rtl;
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