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[/] [wb_fifo/] [trunk/] [model/] [vhdl/] [fifo.vhdl] - Blame information for rev 7

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1 2 daniel.kho
/*
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        This file is part of the Memories project:
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                http://opencores.org/project,wb_fifo
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        Description
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        FIFO memory model.
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        To Do:
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        Author(s):
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        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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        Copyright (C) 2012-2013 Authors and OPENCORES.ORG.
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        This source file may be used and distributed without
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        restriction provided that this copyright statement is not
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        removed from the file and that any derivative work contains
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        the original copyright notice and the associated disclaimer.
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        This source file is free software; you can redistribute it
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        and/or modify it under the terms of the GNU Lesser General
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        Public License as published by the Free Software Foundation;
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        either version 2.1 of the License, or (at your option) any
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        later version.
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        This source is distributed in the hope that it will be
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        useful, but WITHOUT ANY WARRANTY; without even the implied
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        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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        PURPOSE. See the GNU Lesser General Public License for more
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        details.
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        You should have received a copy of the GNU Lesser General
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        Public License along with this source; if not, download it
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        from http://www.opencores.org/lgpl.shtml.
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library tauhop;
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--package fifoTypes is new tauhop.types generic map(t_data=>unsigned(31 downto 0));
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use tauhop.fifoTransactor.all;
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--library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
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--library tauhop; use tauhop.fifoTypes.all;
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entity fifo is
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        generic(memoryDepth:positive);
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        port(clk,reset:in std_ulogic;
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                fifoInterface:inout t_fifoTransactor
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        );
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end entity fifo;
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architecture rtl of fifo is
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        type t_memory is array(memoryDepth-1 downto 0) of i_transactor.t_msg;
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        signal memory:t_memory;
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        signal ptr:natural range 0 to memoryDepth-1;
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55 4 daniel.kho
        /* FIFO control signalling. */
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        signal fifoCtrl:t_fifo;
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58 3 daniel.kho
        /*
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                writeRequest and readRequest are inputs. This indicate that a block is requesting to write to or
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                        read from the FIFO.
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                        For write requests, the external block requests to write some data into the FIFO. The data
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                        is attached as part of the write request (writeRequest.message).
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                        For read requests, the external block requests to read some data from the FIFO. The data will
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                        later be attached in the read response (readResponse.message).
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                There is no such concept as messages attached to a write response (no writeResponse.message) or
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                        read request (no readRequest.message).
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                To generate a write response, the FIFO can assert an acknowledge signal, which could be part of
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                        the response (writeResponse.trigger). The acknowledge is generated only when the FIFO is not
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                        full. The requester can check this flag so that it will not continue requesting a write when
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                        the FIFO is full.
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                        When generating a read response, the FIFO can assert an acknowledge signal as part of the
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                        response (readResponse.trigger), while at the same time, sending data back to the external
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                        requester (readResponse.message). The acknowledge signal is generated only when the FIFO is
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                        not empty. The requester can check this flag so that it will not continue requesting a read
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                        when the FIFO is empty.
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        */
79 2 daniel.kho
        signal i_writeRequest,i_readRequest:i_transactor.t_bfm;
80 3 daniel.kho
        signal i_full,i_empty:boolean;
81 2 daniel.kho
        signal write,read:boolean;
82 7 daniel.kho
 
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        signal writeRequested, readRequested: boolean;
84 2 daniel.kho
begin
85 7 daniel.kho
        /* Registers and pipelines. */
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        /* TODO recheck pipelining. */
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        process(clk) is begin
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                if falling_edge(clk) then
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                        /* TODO add buffers for pipelined request signals,
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                                i.e., add a flip-flop and a buffer.
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                        */
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                        i_writeRequest <= fifoInterface.writeRequest after 1 ps;
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                        i_readRequest <= fifoInterface.readRequest after 1 ps;
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                        i_full <= fifoCtrl.full;
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                        i_empty <= fifoCtrl.empty;
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                end if;
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        end process;
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        /* Synchronous FIFO. */
101 2 daniel.kho
        controller: process(reset,clk) is begin
102 7 daniel.kho
                --if reset then
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                --      fifoInterface.readResponse.message<=(others=>'Z');
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                --      fifoInterface.readResponse.trigger<=false;
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                if falling_edge(clk) then
106 3 daniel.kho
                        /* Default assignments. */
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                        fifoInterface.readResponse.trigger<=false;
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                        fifoInterface.writeResponse.trigger<=false;
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                        /* Write request.
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                                Safety control: allow writing only when FIFO is not full.
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                        */
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                        --if i_pctFilled<d"100" and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
114 7 daniel.kho
                        --if not i_full and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then                -- TODO change to write
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                        if not i_full and write then
116 3 daniel.kho
                                fifoInterface.writeResponse.trigger<=true;
117 2 daniel.kho
                                memory(ptr)<=fifoInterface.writeRequest.message;
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                        end if;
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120 3 daniel.kho
                        /* Read request.
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                                Safety control: allow reading only when FIFO is not empty.
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                        */
123 7 daniel.kho
                        --if not i_empty and (fifoInterface.readRequest.trigger xor i_readRequest.trigger) then         -- TODO change to read
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                        if not i_empty and read then
125 3 daniel.kho
                                fifoInterface.readResponse.trigger<=true;
126 2 daniel.kho
                                fifoInterface.readResponse.message<=memory(ptr);
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                        end if;
128 7 daniel.kho
 
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                        /* Synchronous reset. */
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                        if reset then
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                                fifoInterface.readResponse.message<=(others=>'Z');
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                                fifoInterface.readResponse.trigger<=false;
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                        end if;
134 2 daniel.kho
                end if;
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        end process controller;
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137 7 daniel.kho
        write <= fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
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        read <= fifoInterface.readRequest.trigger xor i_readRequest.trigger;
139 2 daniel.kho
 
140 7 daniel.kho
        /* Request indicator. Derived from fifoInterface.writeRequest.trigger
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                and fifoInterface.readRequest.trigger.
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                Asserts when there are incoming requests.
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        */
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        process(clk) is begin
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                if falling_edge(clk) then
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                        writeRequested <= fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
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                        readRequested <= fifoInterface.readRequest.trigger xor i_readRequest.trigger;
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                end if;
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        end process;
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151 2 daniel.kho
        addrPointer: process(reset,clk) is begin
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                if reset then ptr<=0;
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                elsif falling_edge(clk) then
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                        /* Increment or decrement the address pointer only when write or read is HIGH;
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                                do nothing when both are HIGH or when both are LOW.
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                        */
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                        if write xor read then
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                                if write then
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                                        if ptr<memoryDepth-1 then ptr<=ptr+1; end if;
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                                end if;
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                                if read then
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                                        if ptr>0 then ptr<=ptr-1; end if;
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                                end if;
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                        end if;
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                end if;
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        end process addrPointer;
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168 4 daniel.kho
        fifoCtrl.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoCtrl.pctFilled'length);
169 2 daniel.kho
 
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        process(clk) is begin
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                if rising_edge(clk) then
172 4 daniel.kho
                        fifoCtrl.nearFull<=true when fifoCtrl.pctFilled>=d"75" and fifoCtrl.pctFilled<d"100" else false;
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                        fifoCtrl.full<=true when fifoCtrl.pctFilled=d"100" else false;
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                        fifoCtrl.nearEmpty<=true when fifoCtrl.pctFilled<=d"25" and fifoCtrl.pctFilled>d"0" else false;
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                        fifoCtrl.empty<=true when fifoCtrl.pctFilled=d"0" else false;
176 2 daniel.kho
                end if;
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        end process;
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        process(clk) is begin
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                if falling_edge(clk) then
181 4 daniel.kho
                        fifoCtrl.overflow<=fifoCtrl.full and write;
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                        fifoCtrl.underflow<=fifoCtrl.empty and read;
183 2 daniel.kho
                end if;
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        end process;
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end architecture rtl;

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