URL
https://opencores.org/ocsvn/wb_fifo/wb_fifo/trunk
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| Line No. |
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Author |
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| 1 |
8 |
daniel.kho |
configure wave -signalnamewidth 1
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| 2 |
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| 3 |
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add wave -position end sim:/testbench/clk
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| 4 |
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add wave -position end sim:/testbench/reset
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| 5 |
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add wave -position end sim:/testbench/fifoInterface.writeRequest
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| 6 |
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add wave -position end sim:/testbench/fifoInterface.readRequest
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| 7 |
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add wave -position end sim:/testbench/memoryDepth
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| 8 |
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add wave -position end -hexadecimal -expand sim:/testbench/fifoInterface.writeRequest
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| 9 |
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add wave -position end -hexadecimal -expand sim:/testbench/duv/i_writeRequest
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| 10 |
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add wave -position end sim:/testbench/duv/writeRequested
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| 11 |
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add wave -position end -hexadecimal sim:/testbench/fifoInterface.writeResponse
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| 12 |
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add wave -position end -hexadecimal -expand sim:/testbench/fifoInterface.readRequest
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| 13 |
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add wave -position end -hexadecimal -expand sim:/testbench/duv/i_readRequest
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| 14 |
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add wave -position end sim:/testbench/duv/readRequested
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| 15 |
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add wave -position end -hexadecimal sim:/testbench/fifoInterface.readResponse
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| 16 |
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add wave -position end -hexadecimal sim:/testbench/duv/ptr
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| 17 |
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add wave -position end -decimal sim:/testbench/duv/fifoCtrl.pctFilled
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| 18 |
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add wave -position end sim:/testbench/duv/write
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| 19 |
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add wave -position end sim:/testbench/duv/read
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| 20 |
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add wave -position end sim:/testbench/duv/fifoCtrl.nearFull
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| 21 |
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add wave -position end sim:/testbench/duv/fifoCtrl.full
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| 22 |
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add wave -position end sim:/testbench/duv/fifoCtrl.nearEmpty
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| 23 |
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add wave -position end sim:/testbench/duv/fifoCtrl.empty
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| 24 |
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add wave -position end sim:/testbench/duv/fifoCtrl.overflow
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| 25 |
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add wave -position end sim:/testbench/duv/fifoCtrl.underflow
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| 26 |
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add wave -position end -hexadecimal sim:/testbench/duv/memory
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| 27 |
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| 28 |
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run 80 ns;
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| 29 |
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| 30 |
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wave zoomfull
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| 31 |
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#.wave.tree zoomfull # with some versions of ModelSim
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