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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [rtl/] [wb_lcd.v] - Blame information for rev 2

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1 2 jvillar
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  wb_lcd.v                                                    ////
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////                                                              ////
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////  This file is part of:                                       ////
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////  WISHBONE/MEM MAPPED CONTROLLER FOR LCD CHARACTER DISPLAYS   ////
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////  http://www.opencores.org/projects/wb_lcd/                   ////
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////                                                              ////
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////  Description                                                 ////
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////   -  Wishbone wrapper.                                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////   - José Ignacio Villar, jose@dte.us.es , jvillar@gmail.com  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 José Ignacio Villar - jvillar@gmail.com   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 3 of the License, or (at your option) any     ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.gnu.org/licenses/lgpl.txt                    ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "lcd_defines.v"
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module wb_lcd (
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        //
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        // I/O Ports
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        //
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        input                   wb_clk_i,
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        input                   wb_rst_i,
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        //
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        // WB slave interface
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        //
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        input   [`WB_DAT_RNG]   wb_dat_i,
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        output  reg [`WB_DAT_RNG]       wb_dat_o,
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        input   [`WB_ADDR_RNG]  wb_adr_i,
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        input   [`WB_BSEL_RNG]  wb_sel_i,
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        input                   wb_we_i,
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        input                   wb_cyc_i,
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        input                   wb_stb_i,
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        output  reg             wb_ack_o,
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        output                  wb_err_o,
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        //
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        // LCD interface
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        //
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        output  [3:0]            SF_D,
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        output                  LCD_E,
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        output                  LCD_RS,
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        output                  LCD_RW
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        );
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assign wb_err_o = 0;
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wire cs = wb_cyc_i & wb_stb_i;
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wire we = cs & wb_we_i;
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wire re = cs & !wb_we_i;
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wire special_address = (`SPECIAL_REG_ADDR_MASK == (`SPECIAL_REG_ADDR_MASK & wb_adr_i));
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wire lcd_busy;
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wire lcd_we = !special_address & we;
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wire [`ADDR_WIDTH-1:0] lcd_addr = wb_adr_i[`ADDR_WIDTH-1:0];
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wire repaint_req =  we & (wb_adr_i == `COMMAND_REG_ADDR) & (wb_dat_i == `COMMAND_REPAINT_CODE);
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wire status = lcd_busy ? `STATUS_BUSY_CODE : `STATUS_IDDLE_CODE;
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// wb_ack management: two clk cycles per WB access to avoid long combinational paths.
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always @(posedge wb_clk_i) begin
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        if(wb_rst_i)
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                wb_ack_o <= 1'b0;
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        else begin
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                if(cs)
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                        wb_ack_o <= ~wb_ack_o;
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                else
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                        wb_ack_o <= 1'b0;
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        end
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end
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// Status register (only checks if lcd is busy)
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always @(posedge wb_clk_i) // wb_dat_o always outputs the status register not depending on what address is being accessed
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        wb_dat_o = status;
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// Command register (only issues repaint commands)
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reg lcd_repaint = 0;
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always @(posedge wb_clk_i) begin
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        if(repaint_req & !lcd_busy)
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                lcd_repaint <= 1;
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        else
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                lcd_repaint <= 0;
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end
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//----------------------------------------------------------------------------
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// Memory mapped LCD display controller
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//----------------------------------------------------------------------------
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lcd lcd(
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        .clk    ( wb_clk_i ),
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        .reset  ( wb_rst_i ),
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        .dat    ( wb_dat_i[`DAT_RNG] ),
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        .addr   ( lcd_addr ),
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        .we     ( lcd_we ),
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        .repaint( lcd_repaint ),
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        .busy   ( lcd_busy ),
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        .SF_D   ( SF_D ),
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        .LCD_E  ( LCD_E ),
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        .LCD_RS ( LCD_RS ),
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        .LCD_RW ( LCD_RW )
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        );
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endmodule
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