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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [workspace/] [lcd_display/] [src/] [lcd.v] - Blame information for rev 2

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// File: lcd.v
// Generated by MyHDL 0.6
// Date: Wed Apr 15 12:33:13 2009
 
`timescale 1ns/10ps
 
module lcd (
    clk,
    reset,
    dat,
    addr,
    we,
    repaint,
    busy,
    SF_D,
    LCD_E,
    LCD_RS,
    LCD_RW
);
 
input clk;
input reset;
input [31:0] dat;
input [6:0] addr;
input we;
input repaint;
output busy;
wire busy;
output [3:0] SF_D;
reg [3:0] SF_D;
output LCD_E;
reg LCD_E;
output LCD_RS;
wire LCD_RS;
output LCD_RW;
wire LCD_RW;
 
wire tx_init;
reg [8:0] pos;
wire delay_load;
reg tx_done;
reg [3:0] SF_D1;
reg [3:0] SF_D0;
reg LCD_E1;
reg LCD_E0;
wire delay_done;
reg [7:0] tx_byte;
wire output_selector;
reg [4:0] state;
reg [19:0] tx_delay_value;
reg [19:0] main_delay_value;
reg tx_delay_load;
reg [19:0] delay_value;
reg main_delay_load;
reg [2:0] tx_state;
reg [20:0] counter_counter;
 
reg [7:0] ram [0:80-1];
 
 
 
assign output_selector = ((state == 5'b00000) | (state == 5'b00001) | (state == 5'b00010) | (state == 5'b00011) | (state == 5'b00100) | (state == 5'b00101) | (state == 5'b00110) | (state == 5'b00111) | (state == 5'b01000) | (state == 5'b01001));
 
always @(main_delay_value, tx_delay_load, tx_delay_value) begin: LCD_CONUNTER_SHARING_VALUE
    if (tx_delay_load) begin
        delay_value <= tx_delay_value;
    end
    else begin
        delay_value <= main_delay_value;
    end
end
 
always @(posedge clk, posedge reset) begin: LCD_TXFSM
    if ((reset == 1)) begin
        tx_state <= 3'b110;
        SF_D0 <= 0;
        LCD_E0 <= 0;
    end
    else begin
        tx_delay_load <= 0;
 
        tx_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (tx_state)
            3'b000: begin
                LCD_E0 <= 0;
                SF_D0 <= tx_byte[8-1:4];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b001;
                    tx_delay_load <= 1;
                    tx_delay_value <= 12;
                end
            end
            3'b001: begin
                LCD_E0 <= 1;
                SF_D0 <= tx_byte[8-1:4];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b010;
                    tx_delay_load <= 1;
                    tx_delay_value <= 50;
                end
            end
            3'b010: begin
                LCD_E0 <= 0;
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b011;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2;
                end
            end
            3'b011: begin
                LCD_E0 <= 0;
                SF_D0 <= tx_byte[4-1:0];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b100;
                    tx_delay_load <= 1;
                    tx_delay_value <= 12;
                end
            end
            3'b100: begin
                LCD_E0 <= 1;
                SF_D0 <= tx_byte[4-1:0];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b101;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2000;
                end
            end
            3'b101: begin
                LCD_E0 <= 0;
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b110;
                    tx_done <= 1;
                end
            end
            3'b110: begin
                LCD_E0 <= 0;
                tx_done <= 0;
                tx_delay_load <= 0;
                if (tx_init) begin
                    tx_state <= 3'b000;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2;
                end
            end
        endcase
    end
end
 
 
assign delay_load = (tx_delay_load || main_delay_load);
 
 
assign busy = (state != 5'b10100);
assign LCD_RW = 0;
 
always @(SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) begin: LCD_OUTPUT_TX_OR_INIT_MUX
    if (output_selector) begin
        SF_D <= SF_D1;
        LCD_E <= LCD_E1;
    end
    else begin
        SF_D <= SF_D0;
        LCD_E <= LCD_E0;
    end
end
 
always @(posedge clk) begin: LCD_MEMWRITE
    if (we) begin
        ram[addr] <= dat;
    end
end
 
always @(posedge clk, posedge reset) begin: LCD_DISPLAYFSM
    if ((reset == 1)) begin
        state <= 5'b00000;
        main_delay_load <= 0;
        main_delay_value <= 0;
        SF_D1 <= 0;
        LCD_E1 <= 0;
        tx_byte <= 0;
        pos <= 0;
    end
    else begin
        main_delay_load <= 0;
 
        main_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (state)
            5'b00000: begin
                tx_byte <= 0;
                state <= 5'b00001;
                main_delay_load <= 1;
                main_delay_value <= 750000;
            end
            5'b00001: begin
                main_delay_load <= 0;
                if (delay_done) begin
                    state <= 5'b00010;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00010: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00011;
 
                    main_delay_load <= 1;
                    main_delay_value <= 205000;
                end
            end
            5'b00011: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b00100;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00100: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00101;
 
                    main_delay_load <= 1;
                    main_delay_value <= 5000;
                end
            end
            5'b00101: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b00110;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00110: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00111;
 
                    main_delay_load <= 1;
                    main_delay_value <= 2000;
                end
            end
            5'b00111: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b01000;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b01000: begin
                main_delay_load <= 0;
                SF_D1 <= 2;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b01001;
 
                    main_delay_load <= 1;
                    main_delay_value <= 2000;
                end
            end
            5'b01001: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b01010;
 
                end
            end
            5'b01010: begin
                tx_byte <= 40;
                if (tx_done) begin
                    state <= 5'b01011;
                end
            end
            5'b01011: begin
                tx_byte <= 6;
                if (tx_done) begin
                    state <= 5'b01100;
                end
            end
            5'b01100: begin
                tx_byte <= 12;
                if (tx_done) begin
                    state <= 5'b01101;
                end
            end
            5'b01101: begin
                tx_byte <= 1;
                if (tx_done) begin
                    state <= 5'b01110;
                    main_delay_load <= 1;
                    main_delay_value <= 82000;
                end
            end
            5'b01110: begin
                state <= 5'b01111;
            end
            5'b01111: begin
                tx_byte <= 0;
                if (delay_done) begin
                    state <= 5'b10000;
 
                end
            end
            5'b10000: begin
                tx_byte <= 128;
                if (tx_done) begin
                    state <= 5'b10001;
                    pos <= 0;
                end
            end
            5'b10001: begin
                tx_byte <= ram[pos];
                if (tx_done) begin
                    if ((pos == 15)) begin
                        state <= 5'b10010;
 
                    end
                    else begin
                        pos <= (pos + 1);
                    end
                end
            end
            5'b10010: begin
                tx_byte <= 192;
                if (tx_done) begin
                    state <= 5'b10011;
                    pos <= 64;
                end
            end
            5'b10011: begin
                tx_byte <= ram[pos];
                if (tx_done) begin
                    if ((pos == 79)) begin
                        state <= 5'b10100;
 
                    end
                    else begin
                        pos <= (pos + 1);
                    end
                end
            end
            5'b10100: begin
                tx_byte <= 0;
                if (repaint) begin
                    state <= 5'b01010;
                end
                else begin
                    state <= 5'b10100;
                end
            end
        endcase
    end
end
 
 
assign delay_done = (counter_counter == 0);
 
always @(posedge clk) begin: LCD_COUNTER_COUNTDOWN_LOGIC
    if (delay_load) begin
        counter_counter <= delay_value;
    end
    else begin
        counter_counter <= (counter_counter - 1);
    end
end
 
 
assign tx_init = ((~tx_done) & ((state == 5'b01010) | (state == 5'b01011) | (state == 5'b01100) | (state == 5'b01101) | (state == 5'b10000) | (state == 5'b10001) | (state == 5'b10010) | (state == 5'b10011)));
assign LCD_RS = (~(((state == 5'b01010) != 0) | (state == 5'b01011) | (state == 5'b01100) | (state == 5'b01101) | (state == 5'b10000) | (state == 5'b10010)));
 
endmodule

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Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [workspace/] [lcd_display/] [src/] [lcd.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jvillar	`// File: lcd.v`
2			`// Generated by MyHDL 0.6`
3			`// Date: Wed Apr 15 12:33:13 2009`
4
5			`timescale 1ns/10ps
6
7			`module lcd (`
8			`clk,`
9			`reset,`
10			`dat,`
11			`addr,`
12			`we,`
13			`repaint,`
14			`busy,`
15			`SF_D,`
16			`LCD_E,`
17			`LCD_RS,`
18			`LCD_RW`
19			`);`
20
21			`input clk;`
22			`input reset;`
23			`input [31:0] dat;`
24			`input [6:0] addr;`
25			`input we;`
26			`input repaint;`
27			`output busy;`
28			`wire busy;`
29			`output [3:0] SF_D;`
30			`reg [3:0] SF_D;`
31			`output LCD_E;`
32			`reg LCD_E;`
33			`output LCD_RS;`
34			`wire LCD_RS;`
35			`output LCD_RW;`
36			`wire LCD_RW;`
37
38			`wire tx_init;`
39			`reg [8:0] pos;`
40			`wire delay_load;`
41			`reg tx_done;`
42			`reg [3:0] SF_D1;`
43			`reg [3:0] SF_D0;`
44			`reg LCD_E1;`
45			`reg LCD_E0;`
46			`wire delay_done;`
47			`reg [7:0] tx_byte;`
48			`wire output_selector;`
49			`reg [4:0] state;`
50			`reg [19:0] tx_delay_value;`
51			`reg [19:0] main_delay_value;`
52			`reg tx_delay_load;`
53			`reg [19:0] delay_value;`
54			`reg main_delay_load;`
55			`reg [2:0] tx_state;`
56			`reg [20:0] counter_counter;`
57
58			`reg [7:0] ram [0:80-1];`
59
60
61
62			`assign output_selector = ((state == 5'b00000) \| (state == 5'b00001) \| (state == 5'b00010) \| (state == 5'b00011) \| (state == 5'b00100) \| (state == 5'b00101) \| (state == 5'b00110) \| (state == 5'b00111) \| (state == 5'b01000) \| (state == 5'b01001));`
63
64			`always @(main_delay_value, tx_delay_load, tx_delay_value) begin: LCD_CONUNTER_SHARING_VALUE`
65			`if (tx_delay_load) begin`
66			`delay_value <= tx_delay_value;`
67			`end`
68			`else begin`
69			`delay_value <= main_delay_value;`
70			`end`
71			`end`
72
73			`always @(posedge clk, posedge reset) begin: LCD_TXFSM`
74			`if ((reset == 1)) begin`
75			`tx_state <= 3'b110;`
76			`SF_D0 <= 0;`
77			`LCD_E0 <= 0;`
78			`end`
79			`else begin`
80			`tx_delay_load <= 0;`
81
82			`tx_delay_value <= 0;`
83
84			`// synthesis parallel_case full_case`
85			`casez (tx_state)`
86			`3'b000: begin`
87			`LCD_E0 <= 0;`
88			`SF_D0 <= tx_byte[8-1:4];`
89			`tx_delay_load <= 0;`
90			`if (delay_done) begin`
91			`tx_state <= 3'b001;`
92			`tx_delay_load <= 1;`
93			`tx_delay_value <= 12;`
94			`end`
95			`end`
96			`3'b001: begin`
97			`LCD_E0 <= 1;`
98			`SF_D0 <= tx_byte[8-1:4];`
99			`tx_delay_load <= 0;`
100			`if (delay_done) begin`
101			`tx_state <= 3'b010;`
102			`tx_delay_load <= 1;`
103			`tx_delay_value <= 50;`
104			`end`
105			`end`
106			`3'b010: begin`
107			`LCD_E0 <= 0;`
108			`tx_delay_load <= 0;`
109			`if (delay_done) begin`
110			`tx_state <= 3'b011;`
111			`tx_delay_load <= 1;`
112			`tx_delay_value <= 2;`
113			`end`
114			`end`
115			`3'b011: begin`
116			`LCD_E0 <= 0;`
117			`SF_D0 <= tx_byte[4-1:0];`
118			`tx_delay_load <= 0;`
119			`if (delay_done) begin`
120			`tx_state <= 3'b100;`
121			`tx_delay_load <= 1;`
122			`tx_delay_value <= 12;`
123			`end`
124			`end`
125			`3'b100: begin`
126			`LCD_E0 <= 1;`
127			`SF_D0 <= tx_byte[4-1:0];`
128			`tx_delay_load <= 0;`
129			`if (delay_done) begin`
130			`tx_state <= 3'b101;`
131			`tx_delay_load <= 1;`
132			`tx_delay_value <= 2000;`
133			`end`
134			`end`
135			`3'b101: begin`
136			`LCD_E0 <= 0;`
137			`tx_delay_load <= 0;`
138			`if (delay_done) begin`
139			`tx_state <= 3'b110;`
140			`tx_done <= 1;`
141			`end`
142			`end`
143			`3'b110: begin`
144			`LCD_E0 <= 0;`
145			`tx_done <= 0;`
146			`tx_delay_load <= 0;`
147			`if (tx_init) begin`
148			`tx_state <= 3'b000;`
149			`tx_delay_load <= 1;`
150			`tx_delay_value <= 2;`
151			`end`
152			`end`
153			`endcase`
154			`end`
155			`end`
156
157
158			`assign delay_load = (tx_delay_load \|\| main_delay_load);`
159
160
161			`assign busy = (state != 5'b10100);`
162			`assign LCD_RW = 0;`
163
164			`always @(SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) begin: LCD_OUTPUT_TX_OR_INIT_MUX`
165			`if (output_selector) begin`
166			`SF_D <= SF_D1;`
167			`LCD_E <= LCD_E1;`
168			`end`
169			`else begin`
170			`SF_D <= SF_D0;`
171			`LCD_E <= LCD_E0;`
172			`end`
173			`end`
174
175			`always @(posedge clk) begin: LCD_MEMWRITE`
176			`if (we) begin`
177			`ram[addr] <= dat;`
178			`end`
179			`end`
180
181			`always @(posedge clk, posedge reset) begin: LCD_DISPLAYFSM`
182			`if ((reset == 1)) begin`
183			`state <= 5'b00000;`
184			`main_delay_load <= 0;`
185			`main_delay_value <= 0;`
186			`SF_D1 <= 0;`
187			`LCD_E1 <= 0;`
188			`tx_byte <= 0;`
189			`pos <= 0;`
190			`end`
191			`else begin`
192			`main_delay_load <= 0;`
193
194			`main_delay_value <= 0;`
195
196			`// synthesis parallel_case full_case`
197			`casez (state)`
198			`5'b00000: begin`
199			`tx_byte <= 0;`
200			`state <= 5'b00001;`
201			`main_delay_load <= 1;`
202			`main_delay_value <= 750000;`
203			`end`
204			`5'b00001: begin`
205			`main_delay_load <= 0;`
206			`if (delay_done) begin`
207			`state <= 5'b00010;`
208
209			`main_delay_load <= 1;`
210			`main_delay_value <= 11;`
211			`end`
212			`end`
213			`5'b00010: begin`
214			`main_delay_load <= 0;`
215			`SF_D1 <= 3;`
216			`LCD_E1 <= 1;`
217			`if (delay_done) begin`
218			`state <= 5'b00011;`
219
220			`main_delay_load <= 1;`
221			`main_delay_value <= 205000;`
222			`end`
223			`end`
224			`5'b00011: begin`
225			`main_delay_load <= 0;`
226			`LCD_E1 <= 0;`
227			`if (delay_done) begin`
228			`state <= 5'b00100;`
229
230			`main_delay_load <= 1;`
231			`main_delay_value <= 11;`
232			`end`
233			`end`
234			`5'b00100: begin`
235			`main_delay_load <= 0;`
236			`SF_D1 <= 3;`
237			`LCD_E1 <= 1;`
238			`if (delay_done) begin`
239			`state <= 5'b00101;`
240
241			`main_delay_load <= 1;`
242			`main_delay_value <= 5000;`
243			`end`
244			`end`
245			`5'b00101: begin`
246			`main_delay_load <= 0;`
247			`LCD_E1 <= 0;`
248			`if (delay_done) begin`
249			`state <= 5'b00110;`
250
251			`main_delay_load <= 1;`
252			`main_delay_value <= 11;`
253			`end`
254			`end`
255			`5'b00110: begin`
256			`main_delay_load <= 0;`
257			`SF_D1 <= 3;`
258			`LCD_E1 <= 1;`
259			`if (delay_done) begin`
260			`state <= 5'b00111;`
261
262			`main_delay_load <= 1;`
263			`main_delay_value <= 2000;`
264			`end`
265			`end`
266			`5'b00111: begin`
267			`main_delay_load <= 0;`
268			`LCD_E1 <= 0;`
269			`if (delay_done) begin`
270			`state <= 5'b01000;`
271
272			`main_delay_load <= 1;`
273			`main_delay_value <= 11;`
274			`end`
275			`end`
276			`5'b01000: begin`
277			`main_delay_load <= 0;`
278			`SF_D1 <= 2;`
279			`LCD_E1 <= 1;`
280			`if (delay_done) begin`
281			`state <= 5'b01001;`
282
283			`main_delay_load <= 1;`
284			`main_delay_value <= 2000;`
285			`end`
286			`end`
287			`5'b01001: begin`
288			`main_delay_load <= 0;`
289			`LCD_E1 <= 0;`
290			`if (delay_done) begin`
291			`state <= 5'b01010;`
292
293			`end`
294			`end`
295			`5'b01010: begin`
296			`tx_byte <= 40;`
297			`if (tx_done) begin`
298			`state <= 5'b01011;`
299			`end`
300			`end`
301			`5'b01011: begin`
302			`tx_byte <= 6;`
303			`if (tx_done) begin`
304			`state <= 5'b01100;`
305			`end`
306			`end`
307			`5'b01100: begin`
308			`tx_byte <= 12;`
309			`if (tx_done) begin`
310			`state <= 5'b01101;`
311			`end`
312			`end`
313			`5'b01101: begin`
314			`tx_byte <= 1;`
315			`if (tx_done) begin`
316			`state <= 5'b01110;`
317			`main_delay_load <= 1;`
318			`main_delay_value <= 82000;`
319			`end`
320			`end`
321			`5'b01110: begin`
322			`state <= 5'b01111;`
323			`end`
324			`5'b01111: begin`
325			`tx_byte <= 0;`
326			`if (delay_done) begin`
327			`state <= 5'b10000;`
328
329			`end`
330			`end`
331			`5'b10000: begin`
332			`tx_byte <= 128;`
333			`if (tx_done) begin`
334			`state <= 5'b10001;`
335			`pos <= 0;`
336			`end`
337			`end`
338			`5'b10001: begin`
339			`tx_byte <= ram[pos];`
340			`if (tx_done) begin`
341			`if ((pos == 15)) begin`
342			`state <= 5'b10010;`
343
344			`end`
345			`else begin`
346			`pos <= (pos + 1);`
347			`end`
348			`end`
349			`end`
350			`5'b10010: begin`
351			`tx_byte <= 192;`
352			`if (tx_done) begin`
353			`state <= 5'b10011;`
354			`pos <= 64;`
355			`end`
356			`end`
357			`5'b10011: begin`
358			`tx_byte <= ram[pos];`
359			`if (tx_done) begin`
360			`if ((pos == 79)) begin`
361			`state <= 5'b10100;`
362
363			`end`
364			`else begin`
365			`pos <= (pos + 1);`
366			`end`
367			`end`
368			`end`
369			`5'b10100: begin`
370			`tx_byte <= 0;`
371			`if (repaint) begin`
372			`state <= 5'b01010;`
373			`end`
374			`else begin`
375			`state <= 5'b10100;`
376			`end`
377			`end`
378			`endcase`
379			`end`
380			`end`
381
382
383			`assign delay_done = (counter_counter == 0);`
384
385			`always @(posedge clk) begin: LCD_COUNTER_COUNTDOWN_LOGIC`
386			`if (delay_load) begin`
387			`counter_counter <= delay_value;`
388			`end`
389			`else begin`
390			`counter_counter <= (counter_counter - 1);`
391			`end`
392			`end`
393
394
395			`assign tx_init = ((~tx_done) & ((state == 5'b01010) \| (state == 5'b01011) \| (state == 5'b01100) \| (state == 5'b01101) \| (state == 5'b10000) \| (state == 5'b10001) \| (state == 5'b10010) \| (state == 5'b10011)));`
396			`assign LCD_RS = (~(((state == 5'b01010) != 0) \| (state == 5'b01011) \| (state == 5'b01100) \| (state == 5'b01101) \| (state == 5'b10000) \| (state == 5'b10010)));`
397
398			`endmodule`