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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [workspace/] [lcd_display/] [src/] [lcd.vhd] - Blame information for rev 2

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-- File: lcd.vhd
-- Generated by MyHDL 0.6
-- Date: Wed Apr 15 16:54:27 2009
 
 
package pck_lcd is
 
    type t_enum_t_TxState_2 is (
    tx_high_setup,
    tx_high_hold,
    tx_oneus,
    tx_low_setup,
    tx_low_hold,
    tx_fortyus,
    tx_done
);
    type t_enum_t_State_1 is (
    display_init,
    init_fifteenms,
    init_one,
    init_two,
    init_three,
    init_four,
    init_five,
    init_six,
    init_seven,
    init_eight,
    display_function_set,
    display_entry_set,
    display_set_display,
    display_clr_display,
    display_pause_setup,
    display_pause,
    display_set_addr1,
    display_char_write1,
    display_set_addr2,
    display_char_write2,
    display_done
);
 
end package pck_lcd;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_06.all;
 
use work.pck_lcd.all;
 
entity lcd is
    port (
        clk: in std_logic;
        reset: in std_logic;
        dat: in unsigned(31 downto 0);
        addr: in unsigned(6 downto 0);
        we: in std_logic;
        repaint: in std_logic;
        busy: out std_logic;
        SF_D: out unsigned(3 downto 0);
        LCD_E: out std_logic;
        LCD_RS: out std_logic;
        LCD_RW: out std_logic
    );
end entity lcd;
 
architecture MyHDL of lcd is
 
signal tx_init: std_logic;
signal pos: unsigned(8 downto 0);
signal delay_load: std_logic;
signal tx_done: std_logic;
signal SF_D1: unsigned(3 downto 0);
signal SF_D0: unsigned(3 downto 0);
signal LCD_E1: std_logic;
signal LCD_E0: std_logic;
signal delay_done: std_logic;
signal tx_byte: unsigned(7 downto 0);
signal output_selector: std_logic;
signal state: t_enum_t_State_1;
signal tx_delay_value: unsigned(19 downto 0);
signal main_delay_value: unsigned(19 downto 0);
signal tx_delay_load: std_logic;
signal delay_value: unsigned(19 downto 0);
signal main_delay_load: std_logic;
signal tx_state: t_enum_t_TxState_2;
signal counter_counter: unsigned(20 downto 0);
type t_array_ram is array(0 to 80-1) of unsigned(7 downto 0);
signal ram: t_array_ram;
 
begin
 
 
 
output_selector <= ((state = display_init) or (state = init_fifteenms) or (state = init_one) or (state = init_two) or (state = init_three) or (state = init_four) or (state = init_five) or (state = init_six) or (state = init_seven) or (state = init_eight));
 
LCD_CONUNTER_SHARING_VALUE: process (main_delay_value, tx_delay_load, tx_delay_value) is
begin
    if to_boolean(tx_delay_load) then
        delay_value <= tx_delay_value;
    else
        delay_value <= main_delay_value;
    end if;
end process LCD_CONUNTER_SHARING_VALUE;
 
LCD_TXFSM: process (clk, reset) is
begin
    if (reset = '1') then
        tx_state <= tx_done;
        SF_D0 <= "0000";
        LCD_E0 <= '0';
    elsif rising_edge(clk) then
        tx_delay_load <= '0';
 
        tx_delay_value <= "00000000000000000000";
 
        case tx_state is
            when tx_high_setup =>
                LCD_E0 <= '0';
                SF_D0 <= tx_byte(8-1 downto 4);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_high_hold;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000001100";
                end if;
            when tx_high_hold =>
                LCD_E0 <= '1';
                SF_D0 <= tx_byte(8-1 downto 4);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_oneus;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000110010";
                end if;
            when tx_oneus =>
                LCD_E0 <= '0';
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_low_setup;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000000010";
                end if;
            when tx_low_setup =>
                LCD_E0 <= '0';
                SF_D0 <= tx_byte(4-1 downto 0);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_low_hold;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000001100";
                end if;
            when tx_low_hold =>
                LCD_E0 <= '1';
                SF_D0 <= tx_byte(4-1 downto 0);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_fortyus;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000011111010000";
                end if;
            when tx_fortyus =>
                LCD_E0 <= '0';
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_done;
                    tx_done <= '1';
                end if;
            when tx_done =>
                LCD_E0 <= '0';
                tx_done <= '0';
                tx_delay_load <= '0';
                if to_boolean(tx_init) then
                    tx_state <= tx_high_setup;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000000010";
                end if;
        end case;
    end if;
end process LCD_TXFSM;
 
 
delay_load <= to_std_logic(to_boolean(tx_delay_load) or to_boolean(main_delay_load));
 
 
busy <= to_std_logic(state /= display_done);
LCD_RW <= '0';
 
LCD_OUTPUT_TX_OR_INIT_MUX: process (SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) is
begin
    if to_boolean(output_selector) then
        SF_D <= SF_D1;
        LCD_E <= LCD_E1;
    else
        SF_D <= SF_D0;
        LCD_E <= LCD_E0;
    end if;
end process LCD_OUTPUT_TX_OR_INIT_MUX;
 
LCD_MEMWRITE: process (clk) is
begin
    if rising_edge(clk) then
        if to_boolean(we) then
            ram(to_integer(addr)) <= resize(dat, 8);
        end if;
    end if;
end process LCD_MEMWRITE;
 
LCD_DISPLAYFSM: process (clk, reset) is
begin
    if (reset = '1') then
        state <= display_init;
        main_delay_load <= '0';
        main_delay_value <= "00000000000000000000";
        SF_D1 <= "0000";
        LCD_E1 <= '0';
        tx_byte <= "00000000";
        pos <= "000000000";
    elsif rising_edge(clk) then
        main_delay_load <= '0';
 
        main_delay_value <= "00000000000000000000";
 
        case state is
            when display_init =>
                tx_byte <= "00000000";
                state <= init_fifteenms;
                main_delay_load <= '1';
                main_delay_value <= "10110111000110110000";
            when init_fifteenms =>
                main_delay_load <= '0';
                if to_boolean(delay_done) then
                    state <= init_one;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_one =>
                main_delay_load <= '0';
                SF_D1 <= "0011";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_two;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00110010000011001000";
                end if;
            when init_two =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= init_three;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_three =>
                main_delay_load <= '0';
                SF_D1 <= "0011";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_four;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000001001110001000";
                end if;
            when init_four =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= init_five;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_five =>
                main_delay_load <= '0';
                SF_D1 <= "0011";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_six;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000011111010000";
                end if;
            when init_six =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= init_seven;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_seven =>
                main_delay_load <= '0';
                SF_D1 <= "0010";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_eight;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000011111010000";
                end if;
            when init_eight =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= display_function_set;
 
                end if;
            when display_function_set =>
                tx_byte <= "00101000";
                if to_boolean(tx_done) then
                    state <= display_entry_set;
                end if;
            when display_entry_set =>
                tx_byte <= "00000110";
                if to_boolean(tx_done) then
                    state <= display_set_display;
                end if;
            when display_set_display =>
                tx_byte <= "00001100";
                if to_boolean(tx_done) then
                    state <= display_clr_display;
                end if;
            when display_clr_display =>
                tx_byte <= "00000001";
                if to_boolean(tx_done) then
                    state <= display_pause_setup;
                    main_delay_load <= '1';
                    main_delay_value <= "00010100000001010000";
                end if;
            when display_pause_setup =>
                state <= display_pause;
            when display_pause =>
                tx_byte <= "00000000";
                if to_boolean(delay_done) then
                    state <= display_set_addr1;
 
                end if;
            when display_set_addr1 =>
                tx_byte <= "10000000";
                if to_boolean(tx_done) then
                    state <= display_char_write1;
                    pos <= "000000000";
                end if;
            when display_char_write1 =>
                tx_byte <= ram(pos);
                if to_boolean(tx_done) then
                    if (pos = 15) then
                        state <= display_set_addr2;
 
                    else
                        pos <= (pos + 1);
                    end if;
                end if;
            when display_set_addr2 =>
                tx_byte <= "11000000";
                if to_boolean(tx_done) then
                    state <= display_char_write2;
                    pos <= "001000000";
                end if;
            when display_char_write2 =>
                tx_byte <= ram(pos);
                if to_boolean(tx_done) then
                    if (pos = 79) then
                        state <= display_done;
 
                    else
                        pos <= (pos + 1);
                    end if;
                end if;
            when display_done =>
                tx_byte <= "00000000";
                if to_boolean(repaint) then
                    state <= display_function_set;
                else
                    state <= display_done;
                end if;
        end case;
    end if;
end process LCD_DISPLAYFSM;
 
 
delay_done <= to_std_logic(counter_counter = 0);
 
LCD_COUNTER_COUNTDOWN_LOGIC: process (clk) is
begin
    if rising_edge(clk) then
        if to_boolean(delay_load) then
            counter_counter <= resize(delay_value, 21);
        else
            counter_counter <= (counter_counter - 1);
        end if;
    end if;
end process LCD_COUNTER_COUNTDOWN_LOGIC;
 
 
tx_init <= ((not tx_done) and ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr1) or (state = display_char_write1) or (state = display_set_addr2) or (state = display_char_write2)));
LCD_RS <= (not ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr1) or (state = display_set_addr2)));
 
end architecture MyHDL;

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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace/] [workspace/] [lcd_display/] [src/] [lcd.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jvillar	`-- File: lcd.vhd`
2			`-- Generated by MyHDL 0.6`
3			`-- Date: Wed Apr 15 16:54:27 2009`
4
5
6			`package pck_lcd is`
7
8			`type t_enum_t_TxState_2 is (`
9			`tx_high_setup,`
10			`tx_high_hold,`
11			`tx_oneus,`
12			`tx_low_setup,`
13			`tx_low_hold,`
14			`tx_fortyus,`
15			`tx_done`
16			`);`
17			`type t_enum_t_State_1 is (`
18			`display_init,`
19			`init_fifteenms,`
20			`init_one,`
21			`init_two,`
22			`init_three,`
23			`init_four,`
24			`init_five,`
25			`init_six,`
26			`init_seven,`
27			`init_eight,`
28			`display_function_set,`
29			`display_entry_set,`
30			`display_set_display,`
31			`display_clr_display,`
32			`display_pause_setup,`
33			`display_pause,`
34			`display_set_addr1,`
35			`display_char_write1,`
36			`display_set_addr2,`
37			`display_char_write2,`
38			`display_done`
39			`);`
40
41			`end package pck_lcd;`
42
43			`library IEEE;`
44			`use IEEE.std_logic_1164.all;`
45			`use IEEE.numeric_std.all;`
46			`use std.textio.all;`
47
48			`use work.pck_myhdl_06.all;`
49
50			`use work.pck_lcd.all;`
51
52			`entity lcd is`
53			`port (`
54			`clk: in std_logic;`
55			`reset: in std_logic;`
56			`dat: in unsigned(31 downto 0);`
57			`addr: in unsigned(6 downto 0);`
58			`we: in std_logic;`
59			`repaint: in std_logic;`
60			`busy: out std_logic;`
61			`SF_D: out unsigned(3 downto 0);`
62			`LCD_E: out std_logic;`
63			`LCD_RS: out std_logic;`
64			`LCD_RW: out std_logic`
65			`);`
66			`end entity lcd;`
67
68			`architecture MyHDL of lcd is`
69
70			`signal tx_init: std_logic;`
71			`signal pos: unsigned(8 downto 0);`
72			`signal delay_load: std_logic;`
73			`signal tx_done: std_logic;`
74			`signal SF_D1: unsigned(3 downto 0);`
75			`signal SF_D0: unsigned(3 downto 0);`
76			`signal LCD_E1: std_logic;`
77			`signal LCD_E0: std_logic;`
78			`signal delay_done: std_logic;`
79			`signal tx_byte: unsigned(7 downto 0);`
80			`signal output_selector: std_logic;`
81			`signal state: t_enum_t_State_1;`
82			`signal tx_delay_value: unsigned(19 downto 0);`
83			`signal main_delay_value: unsigned(19 downto 0);`
84			`signal tx_delay_load: std_logic;`
85			`signal delay_value: unsigned(19 downto 0);`
86			`signal main_delay_load: std_logic;`
87			`signal tx_state: t_enum_t_TxState_2;`
88			`signal counter_counter: unsigned(20 downto 0);`
89			`type t_array_ram is array(0 to 80-1) of unsigned(7 downto 0);`
90			`signal ram: t_array_ram;`
91
92			`begin`
93
94
95
96			`output_selector <= ((state = display_init) or (state = init_fifteenms) or (state = init_one) or (state = init_two) or (state = init_three) or (state = init_four) or (state = init_five) or (state = init_six) or (state = init_seven) or (state = init_eight));`
97
98			`LCD_CONUNTER_SHARING_VALUE: process (main_delay_value, tx_delay_load, tx_delay_value) is`
99			`begin`
100			`if to_boolean(tx_delay_load) then`
101			`delay_value <= tx_delay_value;`
102			`else`
103			`delay_value <= main_delay_value;`
104			`end if;`
105			`end process LCD_CONUNTER_SHARING_VALUE;`
106
107			`LCD_TXFSM: process (clk, reset) is`
108			`begin`
109			`if (reset = '1') then`
110			`tx_state <= tx_done;`
111			`SF_D0 <= "0000";`
112			`LCD_E0 <= '0';`
113			`elsif rising_edge(clk) then`
114			`tx_delay_load <= '0';`
115
116			`tx_delay_value <= "00000000000000000000";`
117
118			`case tx_state is`
119			`when tx_high_setup =>`
120			`LCD_E0 <= '0';`
121			`SF_D0 <= tx_byte(8-1 downto 4);`
122			`tx_delay_load <= '0';`
123			`if to_boolean(delay_done) then`
124			`tx_state <= tx_high_hold;`
125			`tx_delay_load <= '1';`
126			`tx_delay_value <= "00000000000000001100";`
127			`end if;`
128			`when tx_high_hold =>`
129			`LCD_E0 <= '1';`
130			`SF_D0 <= tx_byte(8-1 downto 4);`
131			`tx_delay_load <= '0';`
132			`if to_boolean(delay_done) then`
133			`tx_state <= tx_oneus;`
134			`tx_delay_load <= '1';`
135			`tx_delay_value <= "00000000000000110010";`
136			`end if;`
137			`when tx_oneus =>`
138			`LCD_E0 <= '0';`
139			`tx_delay_load <= '0';`
140			`if to_boolean(delay_done) then`
141			`tx_state <= tx_low_setup;`
142			`tx_delay_load <= '1';`
143			`tx_delay_value <= "00000000000000000010";`
144			`end if;`
145			`when tx_low_setup =>`
146			`LCD_E0 <= '0';`
147			`SF_D0 <= tx_byte(4-1 downto 0);`
148			`tx_delay_load <= '0';`
149			`if to_boolean(delay_done) then`
150			`tx_state <= tx_low_hold;`
151			`tx_delay_load <= '1';`
152			`tx_delay_value <= "00000000000000001100";`
153			`end if;`
154			`when tx_low_hold =>`
155			`LCD_E0 <= '1';`
156			`SF_D0 <= tx_byte(4-1 downto 0);`
157			`tx_delay_load <= '0';`
158			`if to_boolean(delay_done) then`
159			`tx_state <= tx_fortyus;`
160			`tx_delay_load <= '1';`
161			`tx_delay_value <= "00000000011111010000";`
162			`end if;`
163			`when tx_fortyus =>`
164			`LCD_E0 <= '0';`
165			`tx_delay_load <= '0';`
166			`if to_boolean(delay_done) then`
167			`tx_state <= tx_done;`
168			`tx_done <= '1';`
169			`end if;`
170			`when tx_done =>`
171			`LCD_E0 <= '0';`
172			`tx_done <= '0';`
173			`tx_delay_load <= '0';`
174			`if to_boolean(tx_init) then`
175			`tx_state <= tx_high_setup;`
176			`tx_delay_load <= '1';`
177			`tx_delay_value <= "00000000000000000010";`
178			`end if;`
179			`end case;`
180			`end if;`
181			`end process LCD_TXFSM;`
182
183
184			`delay_load <= to_std_logic(to_boolean(tx_delay_load) or to_boolean(main_delay_load));`
185
186
187			`busy <= to_std_logic(state /= display_done);`
188			`LCD_RW <= '0';`
189
190			`LCD_OUTPUT_TX_OR_INIT_MUX: process (SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) is`
191			`begin`
192			`if to_boolean(output_selector) then`
193			`SF_D <= SF_D1;`
194			`LCD_E <= LCD_E1;`
195			`else`
196			`SF_D <= SF_D0;`
197			`LCD_E <= LCD_E0;`
198			`end if;`
199			`end process LCD_OUTPUT_TX_OR_INIT_MUX;`
200
201			`LCD_MEMWRITE: process (clk) is`
202			`begin`
203			`if rising_edge(clk) then`
204			`if to_boolean(we) then`
205			`ram(to_integer(addr)) <= resize(dat, 8);`
206			`end if;`
207			`end if;`
208			`end process LCD_MEMWRITE;`
209
210			`LCD_DISPLAYFSM: process (clk, reset) is`
211			`begin`
212			`if (reset = '1') then`
213			`state <= display_init;`
214			`main_delay_load <= '0';`
215			`main_delay_value <= "00000000000000000000";`
216			`SF_D1 <= "0000";`
217			`LCD_E1 <= '0';`
218			`tx_byte <= "00000000";`
219			`pos <= "000000000";`
220			`elsif rising_edge(clk) then`
221			`main_delay_load <= '0';`
222
223			`main_delay_value <= "00000000000000000000";`
224
225			`case state is`
226			`when display_init =>`
227			`tx_byte <= "00000000";`
228			`state <= init_fifteenms;`
229			`main_delay_load <= '1';`
230			`main_delay_value <= "10110111000110110000";`
231			`when init_fifteenms =>`
232			`main_delay_load <= '0';`
233			`if to_boolean(delay_done) then`
234			`state <= init_one;`
235
236			`main_delay_load <= '1';`
237			`main_delay_value <= "00000000000000001011";`
238			`end if;`
239			`when init_one =>`
240			`main_delay_load <= '0';`
241			`SF_D1 <= "0011";`
242			`LCD_E1 <= '1';`
243			`if to_boolean(delay_done) then`
244			`state <= init_two;`
245
246			`main_delay_load <= '1';`
247			`main_delay_value <= "00110010000011001000";`
248			`end if;`
249			`when init_two =>`
250			`main_delay_load <= '0';`
251			`LCD_E1 <= '0';`
252			`if to_boolean(delay_done) then`
253			`state <= init_three;`
254
255			`main_delay_load <= '1';`
256			`main_delay_value <= "00000000000000001011";`
257			`end if;`
258			`when init_three =>`
259			`main_delay_load <= '0';`
260			`SF_D1 <= "0011";`
261			`LCD_E1 <= '1';`
262			`if to_boolean(delay_done) then`
263			`state <= init_four;`
264
265			`main_delay_load <= '1';`
266			`main_delay_value <= "00000001001110001000";`
267			`end if;`
268			`when init_four =>`
269			`main_delay_load <= '0';`
270			`LCD_E1 <= '0';`
271			`if to_boolean(delay_done) then`
272			`state <= init_five;`
273
274			`main_delay_load <= '1';`
275			`main_delay_value <= "00000000000000001011";`
276			`end if;`
277			`when init_five =>`
278			`main_delay_load <= '0';`
279			`SF_D1 <= "0011";`
280			`LCD_E1 <= '1';`
281			`if to_boolean(delay_done) then`
282			`state <= init_six;`
283
284			`main_delay_load <= '1';`
285			`main_delay_value <= "00000000011111010000";`
286			`end if;`
287			`when init_six =>`
288			`main_delay_load <= '0';`
289			`LCD_E1 <= '0';`
290			`if to_boolean(delay_done) then`
291			`state <= init_seven;`
292
293			`main_delay_load <= '1';`
294			`main_delay_value <= "00000000000000001011";`
295			`end if;`
296			`when init_seven =>`
297			`main_delay_load <= '0';`
298			`SF_D1 <= "0010";`
299			`LCD_E1 <= '1';`
300			`if to_boolean(delay_done) then`
301			`state <= init_eight;`
302
303			`main_delay_load <= '1';`
304			`main_delay_value <= "00000000011111010000";`
305			`end if;`
306			`when init_eight =>`
307			`main_delay_load <= '0';`
308			`LCD_E1 <= '0';`
309			`if to_boolean(delay_done) then`
310			`state <= display_function_set;`
311
312			`end if;`
313			`when display_function_set =>`
314			`tx_byte <= "00101000";`
315			`if to_boolean(tx_done) then`
316			`state <= display_entry_set;`
317			`end if;`
318			`when display_entry_set =>`
319			`tx_byte <= "00000110";`
320			`if to_boolean(tx_done) then`
321			`state <= display_set_display;`
322			`end if;`
323			`when display_set_display =>`
324			`tx_byte <= "00001100";`
325			`if to_boolean(tx_done) then`
326			`state <= display_clr_display;`
327			`end if;`
328			`when display_clr_display =>`
329			`tx_byte <= "00000001";`
330			`if to_boolean(tx_done) then`
331			`state <= display_pause_setup;`
332			`main_delay_load <= '1';`
333			`main_delay_value <= "00010100000001010000";`
334			`end if;`
335			`when display_pause_setup =>`
336			`state <= display_pause;`
337			`when display_pause =>`
338			`tx_byte <= "00000000";`
339			`if to_boolean(delay_done) then`
340			`state <= display_set_addr1;`
341
342			`end if;`
343			`when display_set_addr1 =>`
344			`tx_byte <= "10000000";`
345			`if to_boolean(tx_done) then`
346			`state <= display_char_write1;`
347			`pos <= "000000000";`
348			`end if;`
349			`when display_char_write1 =>`
350			`tx_byte <= ram(pos);`
351			`if to_boolean(tx_done) then`
352			`if (pos = 15) then`
353			`state <= display_set_addr2;`
354
355			`else`
356			`pos <= (pos + 1);`
357			`end if;`
358			`end if;`
359			`when display_set_addr2 =>`
360			`tx_byte <= "11000000";`
361			`if to_boolean(tx_done) then`
362			`state <= display_char_write2;`
363			`pos <= "001000000";`
364			`end if;`
365			`when display_char_write2 =>`
366			`tx_byte <= ram(pos);`
367			`if to_boolean(tx_done) then`
368			`if (pos = 79) then`
369			`state <= display_done;`
370
371			`else`
372			`pos <= (pos + 1);`
373			`end if;`
374			`end if;`
375			`when display_done =>`
376			`tx_byte <= "00000000";`
377			`if to_boolean(repaint) then`
378			`state <= display_function_set;`
379			`else`
380			`state <= display_done;`
381			`end if;`
382			`end case;`
383			`end if;`
384			`end process LCD_DISPLAYFSM;`
385
386
387			`delay_done <= to_std_logic(counter_counter = 0);`
388
389			`LCD_COUNTER_COUNTDOWN_LOGIC: process (clk) is`
390			`begin`
391			`if rising_edge(clk) then`
392			`if to_boolean(delay_load) then`
393			`counter_counter <= resize(delay_value, 21);`
394			`else`
395			`counter_counter <= (counter_counter - 1);`
396			`end if;`
397			`end if;`
398			`end process LCD_COUNTER_COUNTDOWN_LOGIC;`
399
400
401			`tx_init <= ((not tx_done) and ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr1) or (state = display_char_write1) or (state = display_set_addr2) or (state = display_char_write2)));`
402			`LCD_RS <= (not ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr1) or (state = display_set_addr2)));`
403
404			`end architecture MyHDL;`