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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace_ramless/] [workspace/] [lcd_display/] [src/] [lcd.v] - Blame information for rev 2

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// File: lcd.v
// Generated by MyHDL 0.6
// Date: Thu Apr 16 10:52:36 2009
 
`timescale 1ns/10ps
 
module lcd (
    clk,
    reset,
    dat,
    addr,
    we,
    busy,
    SF_D,
    LCD_E,
    LCD_RS,
    LCD_RW
);
 
input clk;
input reset;
input [31:0] dat;
input [6:0] addr;
input we;
output busy;
wire busy;
output [3:0] SF_D;
reg [3:0] SF_D;
output LCD_E;
reg LCD_E;
output LCD_RS;
wire LCD_RS;
output LCD_RW;
wire LCD_RW;
 
wire tx_init;
wire delay_load;
reg tx_done;
reg [3:0] SF_D1;
reg [3:0] SF_D0;
reg LCD_E1;
reg LCD_E0;
wire delay_done;
reg [7:0] tx_byte;
reg [6:0] wr_addr;
wire output_selector;
reg [4:0] state;
reg [19:0] tx_delay_value;
reg [19:0] main_delay_value;
reg tx_delay_load;
reg [19:0] delay_value;
reg [6:0] wr_dat;
reg main_delay_load;
reg [2:0] tx_state;
reg [20:0] counter_counter;
 
 
 
 
assign output_selector = ((state == 5'b00000) | (state == 5'b00001) | (state == 5'b00010) | (state == 5'b00011) | (state == 5'b00100) | (state == 5'b00101) | (state == 5'b00110) | (state == 5'b00111) | (state == 5'b01000) | (state == 5'b01001));
 
always @(main_delay_value, tx_delay_load, tx_delay_value) begin: LCD_CONUNTER_SHARING_VALUE
    if (tx_delay_load) begin
        delay_value <= tx_delay_value;
    end
    else begin
        delay_value <= main_delay_value;
    end
end
 
always @(posedge clk, posedge reset) begin: LCD_DISPLAYFSM
    if ((reset == 1)) begin
        state <= 5'b00000;
        main_delay_load <= 0;
        main_delay_value <= 0;
        SF_D1 <= 0;
        LCD_E1 <= 0;
        tx_byte <= 0;
    end
    else begin
        main_delay_load <= 0;
 
        main_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (state)
            5'b00000: begin
                tx_byte <= 0;
                state <= 5'b00001;
                main_delay_load <= 1;
                main_delay_value <= 750000;
            end
            5'b00001: begin
                main_delay_load <= 0;
                if (delay_done) begin
                    state <= 5'b00010;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00010: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00011;
 
                    main_delay_load <= 1;
                    main_delay_value <= 205000;
                end
            end
            5'b00011: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b00100;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00100: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00101;
 
                    main_delay_load <= 1;
                    main_delay_value <= 5000;
                end
            end
            5'b00101: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b00110;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b00110: begin
                main_delay_load <= 0;
                SF_D1 <= 3;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b00111;
 
                    main_delay_load <= 1;
                    main_delay_value <= 2000;
                end
            end
            5'b00111: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b01000;
 
                    main_delay_load <= 1;
                    main_delay_value <= 11;
                end
            end
            5'b01000: begin
                main_delay_load <= 0;
                SF_D1 <= 2;
                LCD_E1 <= 1;
                if (delay_done) begin
                    state <= 5'b01001;
 
                    main_delay_load <= 1;
                    main_delay_value <= 2000;
                end
            end
            5'b01001: begin
                main_delay_load <= 0;
                LCD_E1 <= 0;
                if (delay_done) begin
                    state <= 5'b01010;
 
                end
            end
            5'b01010: begin
                tx_byte <= 40;
                if (tx_done) begin
                    state <= 5'b01011;
                end
            end
            5'b01011: begin
                tx_byte <= 6;
                if (tx_done) begin
                    state <= 5'b01100;
                end
            end
            5'b01100: begin
                tx_byte <= 12;
                if (tx_done) begin
                    state <= 5'b01101;
                end
            end
            5'b01101: begin
                tx_byte <= 1;
                if (tx_done) begin
                    state <= 5'b01111;
                    main_delay_load <= 1;
                    main_delay_value <= 82000;
                end
            end
            5'b01110: begin
                state <= 5'b01111;
            end
            5'b01111: begin
                tx_byte <= 0;
                if (delay_done) begin
                    state <= 5'b10000;
 
                end
            end
            5'b10000: begin
                tx_byte <= 0;
                if (we) begin
                    state <= 5'b10001;
                    wr_addr <= addr;
                    wr_dat <= dat;
                end
                else begin
                    state <= 5'b10000;
                end
            end
            5'b10001: begin
                tx_byte <= (128 | wr_addr);
                if (tx_done) begin
                    state <= 5'b10010;
                end
            end
            5'b10010: begin
                tx_byte <= wr_dat;
                if (tx_done) begin
                    state <= 5'b10000;
 
                end
            end
        endcase
    end
end
 
always @(posedge clk, posedge reset) begin: LCD_TXFSM
    if ((reset == 1)) begin
        tx_state <= 3'b110;
        SF_D0 <= 0;
        LCD_E0 <= 0;
    end
    else begin
        tx_delay_load <= 0;
 
        tx_delay_value <= 0;
 
        // synthesis parallel_case full_case
        casez (tx_state)
            3'b000: begin
                LCD_E0 <= 0;
                SF_D0 <= tx_byte[8-1:4];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b001;
                    tx_delay_load <= 1;
                    tx_delay_value <= 12;
                end
            end
            3'b001: begin
                LCD_E0 <= 1;
                SF_D0 <= tx_byte[8-1:4];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b010;
                    tx_delay_load <= 1;
                    tx_delay_value <= 50;
                end
            end
            3'b010: begin
                LCD_E0 <= 0;
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b011;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2;
                end
            end
            3'b011: begin
                LCD_E0 <= 0;
                SF_D0 <= tx_byte[4-1:0];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b100;
                    tx_delay_load <= 1;
                    tx_delay_value <= 12;
                end
            end
            3'b100: begin
                LCD_E0 <= 1;
                SF_D0 <= tx_byte[4-1:0];
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b101;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2000;
                end
            end
            3'b101: begin
                LCD_E0 <= 0;
                tx_delay_load <= 0;
                if (delay_done) begin
                    tx_state <= 3'b110;
                    tx_done <= 1;
                end
            end
            3'b110: begin
                LCD_E0 <= 0;
                tx_done <= 0;
                tx_delay_load <= 0;
                if (tx_init) begin
                    tx_state <= 3'b000;
                    tx_delay_load <= 1;
                    tx_delay_value <= 2;
                end
            end
        endcase
    end
end
 
 
assign delay_load = (tx_delay_load || main_delay_load);
 
 
assign busy = (state != 5'b10000);
assign LCD_RW = 0;
 
always @(SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) begin: LCD_OUTPUT_TX_OR_INIT_MUX
    if (output_selector) begin
        SF_D <= SF_D1;
        LCD_E <= LCD_E1;
    end
    else begin
        SF_D <= SF_D0;
        LCD_E <= LCD_E0;
    end
end
 
 
assign tx_init = ((~tx_done) & ((state == 5'b01010) | (state == 5'b01011) | (state == 5'b01100) | (state == 5'b01101) | (state == 5'b10001) | (state == 5'b10010)));
assign LCD_RS = (~(((state == 5'b01010) != 0) | (state == 5'b01011) | (state == 5'b01100) | (state == 5'b01101) | (state == 5'b10001)));
 
 
assign delay_done = (counter_counter == 0);
 
always @(posedge clk) begin: LCD_COUNTER_COUNTDOWN_LOGIC
    if (delay_load) begin
        counter_counter <= delay_value;
    end
    else begin
        counter_counter <= (counter_counter - 1);
    end
end
 
endmodule

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Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace_ramless/] [workspace/] [lcd_display/] [src/] [lcd.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jvillar	`// File: lcd.v`
2			`// Generated by MyHDL 0.6`
3			`// Date: Thu Apr 16 10:52:36 2009`
4
5			`timescale 1ns/10ps
6
7			`module lcd (`
8			`clk,`
9			`reset,`
10			`dat,`
11			`addr,`
12			`we,`
13			`busy,`
14			`SF_D,`
15			`LCD_E,`
16			`LCD_RS,`
17			`LCD_RW`
18			`);`
19
20			`input clk;`
21			`input reset;`
22			`input [31:0] dat;`
23			`input [6:0] addr;`
24			`input we;`
25			`output busy;`
26			`wire busy;`
27			`output [3:0] SF_D;`
28			`reg [3:0] SF_D;`
29			`output LCD_E;`
30			`reg LCD_E;`
31			`output LCD_RS;`
32			`wire LCD_RS;`
33			`output LCD_RW;`
34			`wire LCD_RW;`
35
36			`wire tx_init;`
37			`wire delay_load;`
38			`reg tx_done;`
39			`reg [3:0] SF_D1;`
40			`reg [3:0] SF_D0;`
41			`reg LCD_E1;`
42			`reg LCD_E0;`
43			`wire delay_done;`
44			`reg [7:0] tx_byte;`
45			`reg [6:0] wr_addr;`
46			`wire output_selector;`
47			`reg [4:0] state;`
48			`reg [19:0] tx_delay_value;`
49			`reg [19:0] main_delay_value;`
50			`reg tx_delay_load;`
51			`reg [19:0] delay_value;`
52			`reg [6:0] wr_dat;`
53			`reg main_delay_load;`
54			`reg [2:0] tx_state;`
55			`reg [20:0] counter_counter;`
56
57
58
59
60			`assign output_selector = ((state == 5'b00000) \| (state == 5'b00001) \| (state == 5'b00010) \| (state == 5'b00011) \| (state == 5'b00100) \| (state == 5'b00101) \| (state == 5'b00110) \| (state == 5'b00111) \| (state == 5'b01000) \| (state == 5'b01001));`
61
62			`always @(main_delay_value, tx_delay_load, tx_delay_value) begin: LCD_CONUNTER_SHARING_VALUE`
63			`if (tx_delay_load) begin`
64			`delay_value <= tx_delay_value;`
65			`end`
66			`else begin`
67			`delay_value <= main_delay_value;`
68			`end`
69			`end`
70
71			`always @(posedge clk, posedge reset) begin: LCD_DISPLAYFSM`
72			`if ((reset == 1)) begin`
73			`state <= 5'b00000;`
74			`main_delay_load <= 0;`
75			`main_delay_value <= 0;`
76			`SF_D1 <= 0;`
77			`LCD_E1 <= 0;`
78			`tx_byte <= 0;`
79			`end`
80			`else begin`
81			`main_delay_load <= 0;`
82
83			`main_delay_value <= 0;`
84
85			`// synthesis parallel_case full_case`
86			`casez (state)`
87			`5'b00000: begin`
88			`tx_byte <= 0;`
89			`state <= 5'b00001;`
90			`main_delay_load <= 1;`
91			`main_delay_value <= 750000;`
92			`end`
93			`5'b00001: begin`
94			`main_delay_load <= 0;`
95			`if (delay_done) begin`
96			`state <= 5'b00010;`
97
98			`main_delay_load <= 1;`
99			`main_delay_value <= 11;`
100			`end`
101			`end`
102			`5'b00010: begin`
103			`main_delay_load <= 0;`
104			`SF_D1 <= 3;`
105			`LCD_E1 <= 1;`
106			`if (delay_done) begin`
107			`state <= 5'b00011;`
108
109			`main_delay_load <= 1;`
110			`main_delay_value <= 205000;`
111			`end`
112			`end`
113			`5'b00011: begin`
114			`main_delay_load <= 0;`
115			`LCD_E1 <= 0;`
116			`if (delay_done) begin`
117			`state <= 5'b00100;`
118
119			`main_delay_load <= 1;`
120			`main_delay_value <= 11;`
121			`end`
122			`end`
123			`5'b00100: begin`
124			`main_delay_load <= 0;`
125			`SF_D1 <= 3;`
126			`LCD_E1 <= 1;`
127			`if (delay_done) begin`
128			`state <= 5'b00101;`
129
130			`main_delay_load <= 1;`
131			`main_delay_value <= 5000;`
132			`end`
133			`end`
134			`5'b00101: begin`
135			`main_delay_load <= 0;`
136			`LCD_E1 <= 0;`
137			`if (delay_done) begin`
138			`state <= 5'b00110;`
139
140			`main_delay_load <= 1;`
141			`main_delay_value <= 11;`
142			`end`
143			`end`
144			`5'b00110: begin`
145			`main_delay_load <= 0;`
146			`SF_D1 <= 3;`
147			`LCD_E1 <= 1;`
148			`if (delay_done) begin`
149			`state <= 5'b00111;`
150
151			`main_delay_load <= 1;`
152			`main_delay_value <= 2000;`
153			`end`
154			`end`
155			`5'b00111: begin`
156			`main_delay_load <= 0;`
157			`LCD_E1 <= 0;`
158			`if (delay_done) begin`
159			`state <= 5'b01000;`
160
161			`main_delay_load <= 1;`
162			`main_delay_value <= 11;`
163			`end`
164			`end`
165			`5'b01000: begin`
166			`main_delay_load <= 0;`
167			`SF_D1 <= 2;`
168			`LCD_E1 <= 1;`
169			`if (delay_done) begin`
170			`state <= 5'b01001;`
171
172			`main_delay_load <= 1;`
173			`main_delay_value <= 2000;`
174			`end`
175			`end`
176			`5'b01001: begin`
177			`main_delay_load <= 0;`
178			`LCD_E1 <= 0;`
179			`if (delay_done) begin`
180			`state <= 5'b01010;`
181
182			`end`
183			`end`
184			`5'b01010: begin`
185			`tx_byte <= 40;`
186			`if (tx_done) begin`
187			`state <= 5'b01011;`
188			`end`
189			`end`
190			`5'b01011: begin`
191			`tx_byte <= 6;`
192			`if (tx_done) begin`
193			`state <= 5'b01100;`
194			`end`
195			`end`
196			`5'b01100: begin`
197			`tx_byte <= 12;`
198			`if (tx_done) begin`
199			`state <= 5'b01101;`
200			`end`
201			`end`
202			`5'b01101: begin`
203			`tx_byte <= 1;`
204			`if (tx_done) begin`
205			`state <= 5'b01111;`
206			`main_delay_load <= 1;`
207			`main_delay_value <= 82000;`
208			`end`
209			`end`
210			`5'b01110: begin`
211			`state <= 5'b01111;`
212			`end`
213			`5'b01111: begin`
214			`tx_byte <= 0;`
215			`if (delay_done) begin`
216			`state <= 5'b10000;`
217
218			`end`
219			`end`
220			`5'b10000: begin`
221			`tx_byte <= 0;`
222			`if (we) begin`
223			`state <= 5'b10001;`
224			`wr_addr <= addr;`
225			`wr_dat <= dat;`
226			`end`
227			`else begin`
228			`state <= 5'b10000;`
229			`end`
230			`end`
231			`5'b10001: begin`
232			`tx_byte <= (128 \| wr_addr);`
233			`if (tx_done) begin`
234			`state <= 5'b10010;`
235			`end`
236			`end`
237			`5'b10010: begin`
238			`tx_byte <= wr_dat;`
239			`if (tx_done) begin`
240			`state <= 5'b10000;`
241
242			`end`
243			`end`
244			`endcase`
245			`end`
246			`end`
247
248			`always @(posedge clk, posedge reset) begin: LCD_TXFSM`
249			`if ((reset == 1)) begin`
250			`tx_state <= 3'b110;`
251			`SF_D0 <= 0;`
252			`LCD_E0 <= 0;`
253			`end`
254			`else begin`
255			`tx_delay_load <= 0;`
256
257			`tx_delay_value <= 0;`
258
259			`// synthesis parallel_case full_case`
260			`casez (tx_state)`
261			`3'b000: begin`
262			`LCD_E0 <= 0;`
263			`SF_D0 <= tx_byte[8-1:4];`
264			`tx_delay_load <= 0;`
265			`if (delay_done) begin`
266			`tx_state <= 3'b001;`
267			`tx_delay_load <= 1;`
268			`tx_delay_value <= 12;`
269			`end`
270			`end`
271			`3'b001: begin`
272			`LCD_E0 <= 1;`
273			`SF_D0 <= tx_byte[8-1:4];`
274			`tx_delay_load <= 0;`
275			`if (delay_done) begin`
276			`tx_state <= 3'b010;`
277			`tx_delay_load <= 1;`
278			`tx_delay_value <= 50;`
279			`end`
280			`end`
281			`3'b010: begin`
282			`LCD_E0 <= 0;`
283			`tx_delay_load <= 0;`
284			`if (delay_done) begin`
285			`tx_state <= 3'b011;`
286			`tx_delay_load <= 1;`
287			`tx_delay_value <= 2;`
288			`end`
289			`end`
290			`3'b011: begin`
291			`LCD_E0 <= 0;`
292			`SF_D0 <= tx_byte[4-1:0];`
293			`tx_delay_load <= 0;`
294			`if (delay_done) begin`
295			`tx_state <= 3'b100;`
296			`tx_delay_load <= 1;`
297			`tx_delay_value <= 12;`
298			`end`
299			`end`
300			`3'b100: begin`
301			`LCD_E0 <= 1;`
302			`SF_D0 <= tx_byte[4-1:0];`
303			`tx_delay_load <= 0;`
304			`if (delay_done) begin`
305			`tx_state <= 3'b101;`
306			`tx_delay_load <= 1;`
307			`tx_delay_value <= 2000;`
308			`end`
309			`end`
310			`3'b101: begin`
311			`LCD_E0 <= 0;`
312			`tx_delay_load <= 0;`
313			`if (delay_done) begin`
314			`tx_state <= 3'b110;`
315			`tx_done <= 1;`
316			`end`
317			`end`
318			`3'b110: begin`
319			`LCD_E0 <= 0;`
320			`tx_done <= 0;`
321			`tx_delay_load <= 0;`
322			`if (tx_init) begin`
323			`tx_state <= 3'b000;`
324			`tx_delay_load <= 1;`
325			`tx_delay_value <= 2;`
326			`end`
327			`end`
328			`endcase`
329			`end`
330			`end`
331
332
333			`assign delay_load = (tx_delay_load \|\| main_delay_load);`
334
335
336			`assign busy = (state != 5'b10000);`
337			`assign LCD_RW = 0;`
338
339			`always @(SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) begin: LCD_OUTPUT_TX_OR_INIT_MUX`
340			`if (output_selector) begin`
341			`SF_D <= SF_D1;`
342			`LCD_E <= LCD_E1;`
343			`end`
344			`else begin`
345			`SF_D <= SF_D0;`
346			`LCD_E <= LCD_E0;`
347			`end`
348			`end`
349
350
351			`assign tx_init = ((~tx_done) & ((state == 5'b01010) \| (state == 5'b01011) \| (state == 5'b01100) \| (state == 5'b01101) \| (state == 5'b10001) \| (state == 5'b10010)));`
352			`assign LCD_RS = (~(((state == 5'b01010) != 0) \| (state == 5'b01011) \| (state == 5'b01100) \| (state == 5'b01101) \| (state == 5'b10001)));`
353
354
355			`assign delay_done = (counter_counter == 0);`
356
357			`always @(posedge clk) begin: LCD_COUNTER_COUNTDOWN_LOGIC`
358			`if (delay_load) begin`
359			`counter_counter <= delay_value;`
360			`end`
361			`else begin`
362			`counter_counter <= (counter_counter - 1);`
363			`end`
364			`end`
365
366			`endmodule`