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[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace_ramless/] [workspace/] [lcd_display/] [src/] [lcd.vhd] - Blame information for rev 2

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-- File: lcd.vhd
-- Generated by MyHDL 0.6
-- Date: Thu Apr 16 10:52:36 2009
 
 
package pck_lcd is
 
    type t_enum_t_TxState_2 is (
    tx_high_setup,
    tx_high_hold,
    tx_oneus,
    tx_low_setup,
    tx_low_hold,
    tx_fortyus,
    tx_done
);
    type t_enum_t_State_1 is (
    display_init,
    init_fifteenms,
    init_one,
    init_two,
    init_three,
    init_four,
    init_five,
    init_six,
    init_seven,
    init_eight,
    display_function_set,
    display_entry_set,
    display_set_display,
    display_clr_display,
    display_pause_setup,
    display_pause,
    display_done,
    display_set_addr,
    display_char_write
);
 
end package pck_lcd;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_06.all;
 
use work.pck_lcd.all;
 
entity lcd is
    port (
        clk: in std_logic;
        reset: in std_logic;
        dat: in unsigned(31 downto 0);
        addr: in unsigned(6 downto 0);
        we: in std_logic;
        busy: out std_logic;
        SF_D: out unsigned(3 downto 0);
        LCD_E: out std_logic;
        LCD_RS: out std_logic;
        LCD_RW: out std_logic
    );
end entity lcd;
 
architecture MyHDL of lcd is
 
signal tx_init: std_logic;
signal delay_load: std_logic;
signal tx_done: std_logic;
signal SF_D1: unsigned(3 downto 0);
signal SF_D0: unsigned(3 downto 0);
signal LCD_E1: std_logic;
signal LCD_E0: std_logic;
signal delay_done: std_logic;
signal tx_byte: unsigned(7 downto 0);
signal wr_addr: unsigned(6 downto 0);
signal output_selector: std_logic;
signal state: t_enum_t_State_1;
signal tx_delay_value: unsigned(19 downto 0);
signal main_delay_value: unsigned(19 downto 0);
signal tx_delay_load: std_logic;
signal delay_value: unsigned(19 downto 0);
signal wr_dat: unsigned(6 downto 0);
signal main_delay_load: std_logic;
signal tx_state: t_enum_t_TxState_2;
signal counter_counter: unsigned(20 downto 0);
 
begin
 
 
 
output_selector <= ((state = display_init) or (state = init_fifteenms) or (state = init_one) or (state = init_two) or (state = init_three) or (state = init_four) or (state = init_five) or (state = init_six) or (state = init_seven) or (state = init_eight));
 
LCD_CONUNTER_SHARING_VALUE: process (main_delay_value, tx_delay_load, tx_delay_value) is
begin
    if to_boolean(tx_delay_load) then
        delay_value <= tx_delay_value;
    else
        delay_value <= main_delay_value;
    end if;
end process LCD_CONUNTER_SHARING_VALUE;
 
LCD_DISPLAYFSM: process (clk, reset) is
begin
    if (reset = '1') then
        state <= display_init;
        main_delay_load <= '0';
        main_delay_value <= "00000000000000000000";
        SF_D1 <= "0000";
        LCD_E1 <= '0';
        tx_byte <= "00000000";
    elsif rising_edge(clk) then
        main_delay_load <= '0';
 
        main_delay_value <= "00000000000000000000";
 
        case state is
            when display_init =>
                tx_byte <= "00000000";
                state <= init_fifteenms;
                main_delay_load <= '1';
                main_delay_value <= "10110111000110110000";
            when init_fifteenms =>
                main_delay_load <= '0';
                if to_boolean(delay_done) then
                    state <= init_one;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_one =>
                main_delay_load <= '0';
                SF_D1 <= "0011";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_two;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00110010000011001000";
                end if;
            when init_two =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= init_three;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_three =>
                main_delay_load <= '0';
                SF_D1 <= "0011";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_four;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000001001110001000";
                end if;
            when init_four =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= init_five;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_five =>
                main_delay_load <= '0';
                SF_D1 <= "0011";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_six;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000011111010000";
                end if;
            when init_six =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= init_seven;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000000000001011";
                end if;
            when init_seven =>
                main_delay_load <= '0';
                SF_D1 <= "0010";
                LCD_E1 <= '1';
                if to_boolean(delay_done) then
                    state <= init_eight;
 
                    main_delay_load <= '1';
                    main_delay_value <= "00000000011111010000";
                end if;
            when init_eight =>
                main_delay_load <= '0';
                LCD_E1 <= '0';
                if to_boolean(delay_done) then
                    state <= display_function_set;
 
                end if;
            when display_function_set =>
                tx_byte <= "00101000";
                if to_boolean(tx_done) then
                    state <= display_entry_set;
                end if;
            when display_entry_set =>
                tx_byte <= "00000110";
                if to_boolean(tx_done) then
                    state <= display_set_display;
                end if;
            when display_set_display =>
                tx_byte <= "00001100";
                if to_boolean(tx_done) then
                    state <= display_clr_display;
                end if;
            when display_clr_display =>
                tx_byte <= "00000001";
                if to_boolean(tx_done) then
                    state <= display_pause;
                    main_delay_load <= '1';
                    main_delay_value <= "00010100000001010000";
                end if;
            when display_pause_setup =>
                state <= display_pause;
            when display_pause =>
                tx_byte <= "00000000";
                if to_boolean(delay_done) then
                    state <= display_done;
 
                end if;
            when display_done =>
                tx_byte <= "00000000";
                if to_boolean(we) then
                    state <= display_set_addr;
                    wr_addr <= addr;
                    wr_dat <= resize(dat, 7);
                else
                    state <= display_done;
                end if;
            when display_set_addr =>
                tx_byte <= ("10000000" or wr_addr);
                if to_boolean(tx_done) then
                    state <= display_char_write;
                end if;
            when display_char_write =>
                tx_byte <= resize(wr_dat, 8);
                if to_boolean(tx_done) then
                    state <= display_done;
 
                end if;
        end case;
    end if;
end process LCD_DISPLAYFSM;
 
LCD_TXFSM: process (clk, reset) is
begin
    if (reset = '1') then
        tx_state <= tx_done;
        SF_D0 <= "0000";
        LCD_E0 <= '0';
    elsif rising_edge(clk) then
        tx_delay_load <= '0';
 
        tx_delay_value <= "00000000000000000000";
 
        case tx_state is
            when tx_high_setup =>
                LCD_E0 <= '0';
                SF_D0 <= tx_byte(8-1 downto 4);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_high_hold;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000001100";
                end if;
            when tx_high_hold =>
                LCD_E0 <= '1';
                SF_D0 <= tx_byte(8-1 downto 4);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_oneus;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000110010";
                end if;
            when tx_oneus =>
                LCD_E0 <= '0';
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_low_setup;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000000010";
                end if;
            when tx_low_setup =>
                LCD_E0 <= '0';
                SF_D0 <= tx_byte(4-1 downto 0);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_low_hold;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000001100";
                end if;
            when tx_low_hold =>
                LCD_E0 <= '1';
                SF_D0 <= tx_byte(4-1 downto 0);
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_fortyus;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000011111010000";
                end if;
            when tx_fortyus =>
                LCD_E0 <= '0';
                tx_delay_load <= '0';
                if to_boolean(delay_done) then
                    tx_state <= tx_done;
                    tx_done <= '1';
                end if;
            when tx_done =>
                LCD_E0 <= '0';
                tx_done <= '0';
                tx_delay_load <= '0';
                if to_boolean(tx_init) then
                    tx_state <= tx_high_setup;
                    tx_delay_load <= '1';
                    tx_delay_value <= "00000000000000000010";
                end if;
        end case;
    end if;
end process LCD_TXFSM;
 
 
delay_load <= to_std_logic(to_boolean(tx_delay_load) or to_boolean(main_delay_load));
 
 
busy <= to_std_logic(state /= display_done);
LCD_RW <= '0';
 
LCD_OUTPUT_TX_OR_INIT_MUX: process (SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) is
begin
    if to_boolean(output_selector) then
        SF_D <= SF_D1;
        LCD_E <= LCD_E1;
    else
        SF_D <= SF_D0;
        LCD_E <= LCD_E0;
    end if;
end process LCD_OUTPUT_TX_OR_INIT_MUX;
 
 
tx_init <= ((not tx_done) and ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr) or (state = display_char_write)));
LCD_RS <= (not ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr)));
 
 
delay_done <= to_std_logic(counter_counter = 0);
 
LCD_COUNTER_COUNTDOWN_LOGIC: process (clk) is
begin
    if rising_edge(clk) then
        if to_boolean(delay_load) then
            counter_counter <= resize(delay_value, 21);
        else
            counter_counter <= (counter_counter - 1);
        end if;
    end if;
end process LCD_COUNTER_COUNTDOWN_LOGIC;
 
end architecture MyHDL;

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Subversion Repositories wb_lcd

[/] [wb_lcd/] [trunk/] [myhdl/] [wb_lcd_workspace_ramless/] [workspace/] [lcd_display/] [src/] [lcd.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jvillar	`-- File: lcd.vhd`
2			`-- Generated by MyHDL 0.6`
3			`-- Date: Thu Apr 16 10:52:36 2009`
4
5
6			`package pck_lcd is`
7
8			`type t_enum_t_TxState_2 is (`
9			`tx_high_setup,`
10			`tx_high_hold,`
11			`tx_oneus,`
12			`tx_low_setup,`
13			`tx_low_hold,`
14			`tx_fortyus,`
15			`tx_done`
16			`);`
17			`type t_enum_t_State_1 is (`
18			`display_init,`
19			`init_fifteenms,`
20			`init_one,`
21			`init_two,`
22			`init_three,`
23			`init_four,`
24			`init_five,`
25			`init_six,`
26			`init_seven,`
27			`init_eight,`
28			`display_function_set,`
29			`display_entry_set,`
30			`display_set_display,`
31			`display_clr_display,`
32			`display_pause_setup,`
33			`display_pause,`
34			`display_done,`
35			`display_set_addr,`
36			`display_char_write`
37			`);`
38
39			`end package pck_lcd;`
40
41			`library IEEE;`
42			`use IEEE.std_logic_1164.all;`
43			`use IEEE.numeric_std.all;`
44			`use std.textio.all;`
45
46			`use work.pck_myhdl_06.all;`
47
48			`use work.pck_lcd.all;`
49
50			`entity lcd is`
51			`port (`
52			`clk: in std_logic;`
53			`reset: in std_logic;`
54			`dat: in unsigned(31 downto 0);`
55			`addr: in unsigned(6 downto 0);`
56			`we: in std_logic;`
57			`busy: out std_logic;`
58			`SF_D: out unsigned(3 downto 0);`
59			`LCD_E: out std_logic;`
60			`LCD_RS: out std_logic;`
61			`LCD_RW: out std_logic`
62			`);`
63			`end entity lcd;`
64
65			`architecture MyHDL of lcd is`
66
67			`signal tx_init: std_logic;`
68			`signal delay_load: std_logic;`
69			`signal tx_done: std_logic;`
70			`signal SF_D1: unsigned(3 downto 0);`
71			`signal SF_D0: unsigned(3 downto 0);`
72			`signal LCD_E1: std_logic;`
73			`signal LCD_E0: std_logic;`
74			`signal delay_done: std_logic;`
75			`signal tx_byte: unsigned(7 downto 0);`
76			`signal wr_addr: unsigned(6 downto 0);`
77			`signal output_selector: std_logic;`
78			`signal state: t_enum_t_State_1;`
79			`signal tx_delay_value: unsigned(19 downto 0);`
80			`signal main_delay_value: unsigned(19 downto 0);`
81			`signal tx_delay_load: std_logic;`
82			`signal delay_value: unsigned(19 downto 0);`
83			`signal wr_dat: unsigned(6 downto 0);`
84			`signal main_delay_load: std_logic;`
85			`signal tx_state: t_enum_t_TxState_2;`
86			`signal counter_counter: unsigned(20 downto 0);`
87
88			`begin`
89
90
91
92			`output_selector <= ((state = display_init) or (state = init_fifteenms) or (state = init_one) or (state = init_two) or (state = init_three) or (state = init_four) or (state = init_five) or (state = init_six) or (state = init_seven) or (state = init_eight));`
93
94			`LCD_CONUNTER_SHARING_VALUE: process (main_delay_value, tx_delay_load, tx_delay_value) is`
95			`begin`
96			`if to_boolean(tx_delay_load) then`
97			`delay_value <= tx_delay_value;`
98			`else`
99			`delay_value <= main_delay_value;`
100			`end if;`
101			`end process LCD_CONUNTER_SHARING_VALUE;`
102
103			`LCD_DISPLAYFSM: process (clk, reset) is`
104			`begin`
105			`if (reset = '1') then`
106			`state <= display_init;`
107			`main_delay_load <= '0';`
108			`main_delay_value <= "00000000000000000000";`
109			`SF_D1 <= "0000";`
110			`LCD_E1 <= '0';`
111			`tx_byte <= "00000000";`
112			`elsif rising_edge(clk) then`
113			`main_delay_load <= '0';`
114
115			`main_delay_value <= "00000000000000000000";`
116
117			`case state is`
118			`when display_init =>`
119			`tx_byte <= "00000000";`
120			`state <= init_fifteenms;`
121			`main_delay_load <= '1';`
122			`main_delay_value <= "10110111000110110000";`
123			`when init_fifteenms =>`
124			`main_delay_load <= '0';`
125			`if to_boolean(delay_done) then`
126			`state <= init_one;`
127
128			`main_delay_load <= '1';`
129			`main_delay_value <= "00000000000000001011";`
130			`end if;`
131			`when init_one =>`
132			`main_delay_load <= '0';`
133			`SF_D1 <= "0011";`
134			`LCD_E1 <= '1';`
135			`if to_boolean(delay_done) then`
136			`state <= init_two;`
137
138			`main_delay_load <= '1';`
139			`main_delay_value <= "00110010000011001000";`
140			`end if;`
141			`when init_two =>`
142			`main_delay_load <= '0';`
143			`LCD_E1 <= '0';`
144			`if to_boolean(delay_done) then`
145			`state <= init_three;`
146
147			`main_delay_load <= '1';`
148			`main_delay_value <= "00000000000000001011";`
149			`end if;`
150			`when init_three =>`
151			`main_delay_load <= '0';`
152			`SF_D1 <= "0011";`
153			`LCD_E1 <= '1';`
154			`if to_boolean(delay_done) then`
155			`state <= init_four;`
156
157			`main_delay_load <= '1';`
158			`main_delay_value <= "00000001001110001000";`
159			`end if;`
160			`when init_four =>`
161			`main_delay_load <= '0';`
162			`LCD_E1 <= '0';`
163			`if to_boolean(delay_done) then`
164			`state <= init_five;`
165
166			`main_delay_load <= '1';`
167			`main_delay_value <= "00000000000000001011";`
168			`end if;`
169			`when init_five =>`
170			`main_delay_load <= '0';`
171			`SF_D1 <= "0011";`
172			`LCD_E1 <= '1';`
173			`if to_boolean(delay_done) then`
174			`state <= init_six;`
175
176			`main_delay_load <= '1';`
177			`main_delay_value <= "00000000011111010000";`
178			`end if;`
179			`when init_six =>`
180			`main_delay_load <= '0';`
181			`LCD_E1 <= '0';`
182			`if to_boolean(delay_done) then`
183			`state <= init_seven;`
184
185			`main_delay_load <= '1';`
186			`main_delay_value <= "00000000000000001011";`
187			`end if;`
188			`when init_seven =>`
189			`main_delay_load <= '0';`
190			`SF_D1 <= "0010";`
191			`LCD_E1 <= '1';`
192			`if to_boolean(delay_done) then`
193			`state <= init_eight;`
194
195			`main_delay_load <= '1';`
196			`main_delay_value <= "00000000011111010000";`
197			`end if;`
198			`when init_eight =>`
199			`main_delay_load <= '0';`
200			`LCD_E1 <= '0';`
201			`if to_boolean(delay_done) then`
202			`state <= display_function_set;`
203
204			`end if;`
205			`when display_function_set =>`
206			`tx_byte <= "00101000";`
207			`if to_boolean(tx_done) then`
208			`state <= display_entry_set;`
209			`end if;`
210			`when display_entry_set =>`
211			`tx_byte <= "00000110";`
212			`if to_boolean(tx_done) then`
213			`state <= display_set_display;`
214			`end if;`
215			`when display_set_display =>`
216			`tx_byte <= "00001100";`
217			`if to_boolean(tx_done) then`
218			`state <= display_clr_display;`
219			`end if;`
220			`when display_clr_display =>`
221			`tx_byte <= "00000001";`
222			`if to_boolean(tx_done) then`
223			`state <= display_pause;`
224			`main_delay_load <= '1';`
225			`main_delay_value <= "00010100000001010000";`
226			`end if;`
227			`when display_pause_setup =>`
228			`state <= display_pause;`
229			`when display_pause =>`
230			`tx_byte <= "00000000";`
231			`if to_boolean(delay_done) then`
232			`state <= display_done;`
233
234			`end if;`
235			`when display_done =>`
236			`tx_byte <= "00000000";`
237			`if to_boolean(we) then`
238			`state <= display_set_addr;`
239			`wr_addr <= addr;`
240			`wr_dat <= resize(dat, 7);`
241			`else`
242			`state <= display_done;`
243			`end if;`
244			`when display_set_addr =>`
245			`tx_byte <= ("10000000" or wr_addr);`
246			`if to_boolean(tx_done) then`
247			`state <= display_char_write;`
248			`end if;`
249			`when display_char_write =>`
250			`tx_byte <= resize(wr_dat, 8);`
251			`if to_boolean(tx_done) then`
252			`state <= display_done;`
253
254			`end if;`
255			`end case;`
256			`end if;`
257			`end process LCD_DISPLAYFSM;`
258
259			`LCD_TXFSM: process (clk, reset) is`
260			`begin`
261			`if (reset = '1') then`
262			`tx_state <= tx_done;`
263			`SF_D0 <= "0000";`
264			`LCD_E0 <= '0';`
265			`elsif rising_edge(clk) then`
266			`tx_delay_load <= '0';`
267
268			`tx_delay_value <= "00000000000000000000";`
269
270			`case tx_state is`
271			`when tx_high_setup =>`
272			`LCD_E0 <= '0';`
273			`SF_D0 <= tx_byte(8-1 downto 4);`
274			`tx_delay_load <= '0';`
275			`if to_boolean(delay_done) then`
276			`tx_state <= tx_high_hold;`
277			`tx_delay_load <= '1';`
278			`tx_delay_value <= "00000000000000001100";`
279			`end if;`
280			`when tx_high_hold =>`
281			`LCD_E0 <= '1';`
282			`SF_D0 <= tx_byte(8-1 downto 4);`
283			`tx_delay_load <= '0';`
284			`if to_boolean(delay_done) then`
285			`tx_state <= tx_oneus;`
286			`tx_delay_load <= '1';`
287			`tx_delay_value <= "00000000000000110010";`
288			`end if;`
289			`when tx_oneus =>`
290			`LCD_E0 <= '0';`
291			`tx_delay_load <= '0';`
292			`if to_boolean(delay_done) then`
293			`tx_state <= tx_low_setup;`
294			`tx_delay_load <= '1';`
295			`tx_delay_value <= "00000000000000000010";`
296			`end if;`
297			`when tx_low_setup =>`
298			`LCD_E0 <= '0';`
299			`SF_D0 <= tx_byte(4-1 downto 0);`
300			`tx_delay_load <= '0';`
301			`if to_boolean(delay_done) then`
302			`tx_state <= tx_low_hold;`
303			`tx_delay_load <= '1';`
304			`tx_delay_value <= "00000000000000001100";`
305			`end if;`
306			`when tx_low_hold =>`
307			`LCD_E0 <= '1';`
308			`SF_D0 <= tx_byte(4-1 downto 0);`
309			`tx_delay_load <= '0';`
310			`if to_boolean(delay_done) then`
311			`tx_state <= tx_fortyus;`
312			`tx_delay_load <= '1';`
313			`tx_delay_value <= "00000000011111010000";`
314			`end if;`
315			`when tx_fortyus =>`
316			`LCD_E0 <= '0';`
317			`tx_delay_load <= '0';`
318			`if to_boolean(delay_done) then`
319			`tx_state <= tx_done;`
320			`tx_done <= '1';`
321			`end if;`
322			`when tx_done =>`
323			`LCD_E0 <= '0';`
324			`tx_done <= '0';`
325			`tx_delay_load <= '0';`
326			`if to_boolean(tx_init) then`
327			`tx_state <= tx_high_setup;`
328			`tx_delay_load <= '1';`
329			`tx_delay_value <= "00000000000000000010";`
330			`end if;`
331			`end case;`
332			`end if;`
333			`end process LCD_TXFSM;`
334
335
336			`delay_load <= to_std_logic(to_boolean(tx_delay_load) or to_boolean(main_delay_load));`
337
338
339			`busy <= to_std_logic(state /= display_done);`
340			`LCD_RW <= '0';`
341
342			`LCD_OUTPUT_TX_OR_INIT_MUX: process (SF_D1, SF_D0, LCD_E1, LCD_E0, output_selector) is`
343			`begin`
344			`if to_boolean(output_selector) then`
345			`SF_D <= SF_D1;`
346			`LCD_E <= LCD_E1;`
347			`else`
348			`SF_D <= SF_D0;`
349			`LCD_E <= LCD_E0;`
350			`end if;`
351			`end process LCD_OUTPUT_TX_OR_INIT_MUX;`
352
353
354			`tx_init <= ((not tx_done) and ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr) or (state = display_char_write)));`
355			`LCD_RS <= (not ((state = display_function_set) or (state = display_entry_set) or (state = display_set_display) or (state = display_clr_display) or (state = display_set_addr)));`
356
357
358			`delay_done <= to_std_logic(counter_counter = 0);`
359
360			`LCD_COUNTER_COUNTDOWN_LOGIC: process (clk) is`
361			`begin`
362			`if rising_edge(clk) then`
363			`if to_boolean(delay_load) then`
364			`counter_counter <= resize(delay_value, 21);`
365			`else`
366			`counter_counter <= (counter_counter - 1);`
367			`end if;`
368			`end if;`
369			`end process LCD_COUNTER_COUNTDOWN_LOGIC;`
370
371			`end architecture MyHDL;`