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jvillar |
#############################################################################
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# Master path definitions
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TOPDIR?=$(shell pwd)
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TOOLS_DIR=$(TOPDIR)/../../../tools
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CORE_DIR=$(TOPDIR)/../../../rtl
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BOARD_DIR=$(TOPDIR)/../rtl
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#CHIPSCOPE_DIR=$(TOPDIR)/../chipscope
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#############################################################################
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# Board and core source files for synthesis and simulation
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BOARD_SYN=$(wildcard $(BOARD_DIR)/*.v)
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BOARD_SIM=$(wildcard $(BOARD_DIR)/*.v)
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CORE_SRCS=$(wildcard $(CORE_DIR)/*.v)
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#CHIPSCOPE_SRCS=$(wildcard $(CHIPSCOPE_DIR)/*.v)
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SYN_SRC= \
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$(BOARD_SYN) \
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$(CORE_SRCS)
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#SYN_SRC= \
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# $(BOARD_SYN) \
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# $(CORE_SRCS) \
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# $(CHIPSCOPE_SRCS)
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SIM_SRC= \
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$(BOARD_SYN) \
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$(CORE_SRCS)
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VINCDIR= \
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-I$(CORE_DIR) \
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-I$(BOARD_DIR)
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#############################################################################
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# Syntheis constants
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SYNCLEAN=system.bgn system.drc system.mrp system.ngd system.pcf
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SYNCLEAN+=system.bld system.lso system.ncd system.ngm system.srp
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SYNCLEAN+=system.bit system_signalbrowser.* system-routed_pad.tx system.bin
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SYNCLEAN+=system.map system_summary.xml timing.twr
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SYNCLEAN+=system-routed* system_usage* system.ngc param.opt netlist.lst
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SYNCLEAN+=xst system.prj system.prm
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SYNCLEAN+=*.lso
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# for ISE 10.1
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SYNCLEAN+=xlnx_auto_0.ise system_par.xrpt smartpreview.twr system.ngc_xst.xrpt
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SYNCLEAN+=system_ngdbuild.xrpt system_map.xrpt xlnx_auto_0_xdb _impactbatch.log
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USAGE_DEPTH=5
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SMARTGUIDE=
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#############################################################################
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# Simulation constants
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SIMCLEAN=system_sim.vvp system_sim.vcd verilog.log system_sim.vvp.list
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CVER=cver
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GTKWAVE=gtkwave
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IVERILOG=iverilog
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VVP=vvp
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#############################################################################
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#
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all: system.bit system.bin
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sim: system_sim.vcd
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syn: system.bit
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view: system_sim.view
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#############################################################################
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# Icarus verilog simulation
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system_sim.vvp: $(SIM_SRC)
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rm -f $@.list
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@for i in `echo $^`; do \
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echo $$i >> $@.list; \
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done
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$(IVERILOG) -o $@ $(VINCDIR) -c $@.list -s $(@:.vvp=) -s glbl
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%.vcd: %.vvp
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$(VVP) $<
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#############################################################################
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# ISE Synthesis
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system.prj: $(SYN_SRC)
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rm -f system.prj
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@for i in `echo $^`; do \
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echo "verilog work $$i" >> system.prj; \
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done
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system.ngc: system.prj
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xst -ifn system.xst
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system.ngd: system.ngc system.ucf
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ngdbuild -uc system.ucf system.ngc
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# ngdbuild -uc system.ucf -sd $(CHIPSCOPE_DIR) system.ngc
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system.ncd: system.ngd
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map $(SMARTGUIDE) system.ngd
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system-routed.ncd: system.ncd
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par $(SMARTGUIDE) -ol high -w system.ncd system-routed.ncd
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system.bit: system-routed.ncd
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bitgen -w system-routed.ncd system.bit
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system.bin: system.bit
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promgen -u 0x0 system.bit -p bin -w
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system.mcs: system.bit
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promgen -u 0 system
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system-routed.xdl: system-routed.ncd
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xdl -ncd2xdl system-routed.ncd system-routed.xdl
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system-routed.twr: system-routed.ncd
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trce -v 10 system-routed.ncd system.pcf
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timing: system-routed.twr
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usage: system-routed.xdl
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$(TOOLS_DIR)/xdlanalyze/xdlanalyze.pl system-routed.xdl $(USAGE_DEPTH)
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####################################################################
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# final targets
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load: system.bit
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impact -batch impact.batch
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#analyze: load
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# analyzer.sh
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%.view: %.vcd
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$(GTKWAVE) $< $<.save
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clean:
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rm -Rf $(SYNCLEAN) $(SIMCLEAN)
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.PHONY: clean view
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