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[/] [wb_lpc/] [trunk/] [examples/] [lpc_7seg/] [disp_dec.vhd] - Blame information for rev 20

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Line No. Rev Author Line
1 7 hharte
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-- Company: 
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-- Engineer:
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--
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-- Create Date:    16:07:18 01/02/06
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-- Design Name:    
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-- Module Name:    dip_dec - Behavioral
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-- Project Name:   
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-- Target Device:  
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-- Tool versions:  
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-- Description:
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--
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-- Dependencies:
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-- 
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- 
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity disp_dec is
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port    (
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                disp_dec_in             : in std_logic_vector(3 downto 0);
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                disp_dec_out    : out std_logic_vector(6 downto 0)
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                );
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end disp_dec;
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architecture disp_dec_behave of disp_dec is
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begin
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process (disp_dec_in)
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begin
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        case disp_dec_in is
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                when "0000" =>
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                        disp_dec_out <= "1000000";
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                when "0001" =>
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                        disp_dec_out <= "1111001";
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                when "0010" =>
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                        disp_dec_out <= "0100100";
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                when "0011" =>
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                        disp_dec_out <= "0110000";
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                when "0100" =>
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                        disp_dec_out <= "0011001";
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                when "0101" =>
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                        disp_dec_out <= "0010010";
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                when "0110" =>
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                        disp_dec_out <= "0000010";
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                when "0111" =>
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                        disp_dec_out <= "1111000";
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                when "1000" =>
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                        disp_dec_out <= "0000000";
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                when "1001" =>
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                        disp_dec_out <= "0010000";
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                when "1010" =>
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                        disp_dec_out <= "0001000";
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                when "1011" =>
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                        disp_dec_out <= "0000011";
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                when "1100" =>
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                        disp_dec_out <= "1000110";
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                when "1101" =>
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                        disp_dec_out <= "0100001";
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                when "1110" =>
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                        disp_dec_out <= "0000110";
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                when "1111" =>
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                        disp_dec_out <= "0001110";
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                when others     =>
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                         disp_dec_out <= "1111111";
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        end case;
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end process;
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end disp_dec_behave;

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