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[/] [wb_lpc/] [trunk/] [examples/] [lpc_7seg/] [wb_7seg.vhd] - Blame information for rev 20

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Line No. Rev Author Line
1 7 hharte 
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    10:22:14 12/29/05
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-- Design Name:
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-- Module Name:    wb_7seg - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity wb_7seg is
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        port(
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                clk_i            : in std_logic;
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                nrst_i           : in std_logic;
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                wb_adr_i     : in std_logic_vector(24 downto 0);
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                wb_dat_o     : out std_logic_vector(31 downto 0);
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        wb_dat_i     : in std_logic_vector(31 downto 0);
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                wb_sel_i     : in std_logic_vector(3 downto 0);
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        wb_we_i      : in std_logic;
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                wb_stb_i     : in std_logic;
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                wb_cyc_i     : in std_logic;
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                wb_ack_o     : out std_logic;
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                wb_err_o     : out std_logic;
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                wb_int_o     : out std_logic;
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                DISP_SEL         : inout std_logic_vector(3 downto 0);
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                DISP_LED         : out std_logic_vector(6 downto 0)
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        );
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end wb_7seg;
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architecture wb_7seg_behav of wb_7seg is
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component disp_dec
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port    (
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                disp_dec_in             : in std_logic_vector(3 downto 0);
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                disp_dec_out    : out std_logic_vector(6 downto 0)
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                );
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end component;
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        signal          data_reg                : std_logic_vector(31 downto 0);
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        signal          disp_cnt                : std_logic_vector(6 downto 0);
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        signal          disp_data               : std_logic_vector(3 downto 0);
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        signal          disp_data_led   : std_logic_vector(6 downto 0);
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        signal          disp_pos                : std_logic_vector(3 downto 0);
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        constant        DISP_CNT_MAX    : std_logic_vector(6 downto 0) := "1111111";
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begin
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process (clk_i,nrst_i)
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begin
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        if nrst_i = '0' then
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                data_reg <= x"10eef00d";
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                elsif ( clk_i'event and clk_i = '1' ) then
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                        if ( wb_stb_i = '1' and wb_we_i = '1' ) then
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                                data_reg <= wb_dat_i;
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                        end if;
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        end if;
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end process;
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wb_ack_o <= wb_stb_i;
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wb_err_o <= '0';
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wb_int_o <= '0';
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wb_dat_o <= data_reg;
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process (clk_i,nrst_i)
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begin
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        if nrst_i = '0' then
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                disp_cnt <= ( others => '0' );
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                elsif clk_i'event and clk_i = '1' then
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                        disp_cnt <= disp_cnt + 1;
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        end if;
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end process;
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process (clk_i,nrst_i)
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begin
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        if nrst_i = '0' then
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                disp_pos <= "0001";
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                elsif clk_i'event and clk_i = '1' then
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                        if disp_cnt = DISP_CNT_MAX then
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                                disp_pos <=     (
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                                                        3 => DISP_SEL(2), 2 => DISP_SEL(1),
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                                                        1 => DISP_SEL(0), 0 => DISP_SEL(3)
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                                                        );
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                        end if;
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        end if;
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end process;
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process (clk_i,nrst_i)
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begin
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        if nrst_i = '0' then
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                disp_data <= "0000";
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                elsif clk_i'event and clk_i = '1' then
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                        case DISP_SEL is
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                                when "1000" =>
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                                        disp_data <= data_reg(3 downto 0);
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                                when "0100" =>
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                                        disp_data <= data_reg(7 downto 4);
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                                when "0010" =>
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                                        disp_data <= data_reg(11 downto 8);
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                                when "0001" =>
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                                        disp_data <= data_reg(15 downto 12);
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                                when others     =>
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                                        disp_data <= (others => '0');
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                        end case;
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        end if;
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end process;
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u1: component disp_dec
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port map        (
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                disp_dec_in             => disp_data,
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                        disp_dec_out    => disp_data_led
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                        );
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process (clk_i,nrst_i)
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begin
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        if nrst_i = '0' then
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                DISP_LED <= (others => '0');
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                elsif clk_i'event and clk_i = '1' then
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                        DISP_LED <= disp_data_led;
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        end if;
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end process;
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process (clk_i,nrst_i)
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begin
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        if nrst_i = '0' then
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                DISP_SEL <= (others => '0');
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                elsif clk_i'event and clk_i = '1' then
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                        DISP_SEL <= disp_pos;
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        end if;
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end process;
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end wb_7seg_behav;

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