OpenCores
URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk

Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [examples/] [lpc_7seg/] [wb_7seg.vhd] - Blame information for rev 22

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 hharte 
--------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Create Date:    10:22:14 12/29/05
6 
-- Design Name:
7 
-- Module Name:    wb_7seg - Behavioral
8 
-- Project Name:
9 
-- Target Device:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
-- Revision 0.01 - File Created
17 
-- Additional Comments:
18 
--
19 
--------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
 
26 
entity wb_7seg is
27 
        port(
28 
 
29 
                clk_i            : in std_logic;
30 
                nrst_i           : in std_logic;
31 
                wb_adr_i     : in std_logic_vector(24 downto 0);
32 
                wb_dat_o     : out std_logic_vector(31 downto 0);
33 
        wb_dat_i     : in std_logic_vector(31 downto 0);
34 
                wb_sel_i     : in std_logic_vector(3 downto 0);
35 
        wb_we_i      : in std_logic;
36 
                wb_stb_i     : in std_logic;
37 
                wb_cyc_i     : in std_logic;
38 
                wb_ack_o     : out std_logic;
39 
                wb_err_o     : out std_logic;
40 
                wb_int_o     : out std_logic;
41 
                DISP_SEL         : inout std_logic_vector(3 downto 0);
42 
                DISP_LED         : out std_logic_vector(6 downto 0)
43 
 
44 
        );
45 
 
46 
end wb_7seg;
47 
 
48 
architecture wb_7seg_behav of wb_7seg is
49 
 
50 
component disp_dec
51 
port    (
52 
                disp_dec_in             : in std_logic_vector(3 downto 0);
53 
                disp_dec_out    : out std_logic_vector(6 downto 0)
54 
                );
55 
end component;
56 
 
57 
 
58 
        signal          data_reg                : std_logic_vector(31 downto 0);
59 
        signal          disp_cnt                : std_logic_vector(6 downto 0);
60 
        signal          disp_data               : std_logic_vector(3 downto 0);
61 
        signal          disp_data_led   : std_logic_vector(6 downto 0);
62 
        signal          disp_pos                : std_logic_vector(3 downto 0);
63 
        constant        DISP_CNT_MAX    : std_logic_vector(6 downto 0) := "1111111";
64 
 
65 
 
66 
 
67 
begin
68 
 
69 
process (clk_i,nrst_i)
70 
begin
71 
        if nrst_i = '0' then
72 
                data_reg <= x"10eef00d";
73 
                elsif ( clk_i'event and clk_i = '1' ) then
74 
                        if ( wb_stb_i = '1' and wb_we_i = '1' ) then
75 
                                data_reg <= wb_dat_i;
76 
                        end if;
77 
        end if;
78 
end process;
79 
 
80 
wb_ack_o <= wb_stb_i;
81 
wb_err_o <= '0';
82 
wb_int_o <= '0';
83 
wb_dat_o <= data_reg;
84 
 
85 
 
86 
 
87 
process (clk_i,nrst_i)
88 
begin
89 
        if nrst_i = '0' then
90 
                disp_cnt <= ( others => '0' );
91 
                elsif clk_i'event and clk_i = '1' then
92 
                        disp_cnt <= disp_cnt + 1;
93 
        end if;
94 
end process;
95 
 
96 
process (clk_i,nrst_i)
97 
begin
98 
        if nrst_i = '0' then
99 
                disp_pos <= "0001";
100 
                elsif clk_i'event and clk_i = '1' then
101 
                        if disp_cnt = DISP_CNT_MAX then
102 
                                disp_pos <=     (
103 
                                                        3 => DISP_SEL(2), 2 => DISP_SEL(1),
104 
                                                        1 => DISP_SEL(0), 0 => DISP_SEL(3)
105 
                                                        );
106 
                        end if;
107 
        end if;
108 
end process;
109 
 
110 
process (clk_i,nrst_i)
111 
begin
112 
        if nrst_i = '0' then
113 
                disp_data <= "0000";
114 
                elsif clk_i'event and clk_i = '1' then
115 
                        case DISP_SEL is
116 
                                when "1000" =>
117 
                                        disp_data <= data_reg(3 downto 0);
118 
                                when "0100" =>
119 
                                        disp_data <= data_reg(7 downto 4);
120 
                                when "0010" =>
121 
                                        disp_data <= data_reg(11 downto 8);
122 
                                when "0001" =>
123 
                                        disp_data <= data_reg(15 downto 12);
124 
                                when others     =>
125 
                                        disp_data <= (others => '0');
126 
                        end case;
127 
        end if;
128 
end process;
129 
 
130 
 
131 
u1: component disp_dec
132 
port map        (
133 
                disp_dec_in             => disp_data,
134 
                        disp_dec_out    => disp_data_led
135 
                        );
136 
 
137 
process (clk_i,nrst_i)
138 
begin
139 
        if nrst_i = '0' then
140 
                DISP_LED <= (others => '0');
141 
                elsif clk_i'event and clk_i = '1' then
142 
                        DISP_LED <= disp_data_led;
143 
        end if;
144 
end process;
145 
 
146 
process (clk_i,nrst_i)
147 
begin
148 
        if nrst_i = '0' then
149 
                DISP_SEL <= (others => '0');
150 
                elsif clk_i'event and clk_i = '1' then
151 
                        DISP_SEL <= disp_pos;
152 
        end if;
153 
end process;
154 
 
155 
end wb_7seg_behav;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.