OpenCores
URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk

Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [serirq_defines.v] - Blame information for rev 20

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 hharte
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3 19 hharte
////  $Id: serirq_defines.v,v 1.2 2008-12-27 19:46:18 hharte Exp $
4 11 hharte
////  wb_lpc_defines.v                                            ////
5
////                                                              ////
6
////  This file is part of the Wishbone LPC Bridge project        ////
7
////  http://www.opencores.org/projects/wb_lpc/                   ////
8
////                                                              ////
9
////  Author:                                                     ////
10
////      - Howard M. Harte (hharte@opencores.org)                ////
11
////                                                              ////
12
//////////////////////////////////////////////////////////////////////
13
////                                                              ////
14
//// Copyright (C) 2008 Howard M. Harte                           ////
15
////                                                              ////
16
//// This source file may be used and distributed without         ////
17
//// restriction provided that this copyright statement is not    ////
18
//// removed from the file and that any derivative work contains  ////
19
//// the original copyright notice and the associated disclaimer. ////
20
////                                                              ////
21
//// This source file is free software; you can redistribute it   ////
22
//// and/or modify it under the terms of the GNU Lesser General   ////
23
//// Public License as published by the Free Software Foundation; ////
24
//// either version 2.1 of the License, or (at your option) any   ////
25
//// later version.                                               ////
26
////                                                              ////
27
//// This source is distributed in the hope that it will be       ////
28
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
29
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
30
//// PURPOSE.  See the GNU Lesser General Public License for more ////
31
//// details.                                                     ////
32
////                                                              ////
33
//// You should have received a copy of the GNU Lesser General    ////
34
//// Public License along with this source; if not, download it   ////
35
//// from http://www.opencores.org/lgpl.shtml                     ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
 
39
// Wishbone SERIRQ Host/Slave Interface Definitions
40
`define SERIRQ_ST_IDLE    13'h000             // SERIRQ Idle state
41
`define SERIRQ_ST_START   13'h001             // SERIRQ Start state
42
`define SERIRQ_ST_START_R 13'h002             // SERIRQ Start state
43
`define SERIRQ_ST_START_T 13'h004             // SERIRQ Start state
44
`define SERIRQ_ST_IRQ     13'h008             // SERIRQ IRQ Frame State
45
`define SERIRQ_ST_IRQ_R   13'h010             // SERIRQ IRQ Frame State
46
`define SERIRQ_ST_IRQ_T   13'h020             // SERIRQ IRQ Frame State
47
`define SERIRQ_ST_STOP    13'h040             // SERIRQ Stop State
48
`define SERIRQ_ST_STOP_R  13'h080             // SERIRQ Stop State
49
`define SERIRQ_ST_STOP_T  13'h100             // SERIRQ Stop State
50
`define SERIRQ_ST_WAIT_STOP 13'h200
51
 
52
`define SERIRQ_MODE_CONTINUOUS 1'b0           // Serirq "Continuous Mode"
53 19 hharte
`define SERIRQ_MODE_QUIET  1'b1               // Serirq "Quiet Mode"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.