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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [serirq_slave.v] - Blame information for rev 20

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $  ////
////  serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge       ////
////                                                              ////
////  This file is part of the Wishbone LPC Bridge project        ////
////  http://www.opencores.org/projects/lpc/                      ////
////                                                              ////
////  Author:                                                     ////
////      - Howard M. Harte (hharte@opencores.org)                ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 Howard M. Harte                           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ns / 1 ns
 
`include "../../rtl/verilog/serirq_defines.v"
 
module serirq_slave(clk_i, nrst_i,
                    irq_i,
                    serirq_o, serirq_i, serirq_oe
);
    // Wishbone Slave Interface
    input             clk_i;
    input             nrst_i;       // Active low reset.
 
    // SERIRQ Master Interface
    output reg        serirq_o;     // SERIRQ output
    input             serirq_i;     // SERIRQ Input
    output reg        serirq_oe;    // SERIRQ Output Enable
 
    input      [31:0] irq_i;        // IRQ Input Bus
    reg        [31:0] current_irq;
 
    reg        [12:0] state;        // Current state
    reg         [4:0] irq_cnt;      // IRQ Frame counter
 
    reg found_stop;
    reg found_start;
    reg serirq_mode;
 
    wire irq_changed = (serirq_mode & (current_irq != irq_i));
 
    always @(posedge clk_i or negedge nrst_i)
        if(~nrst_i)
        begin
            state <= `SERIRQ_ST_IDLE;
            serirq_oe <= 1'b0;
            serirq_o <= 4'b1;
            irq_cnt <= 5'h00;
            current_irq <= irq_i;
        end
        else begin
            case(state)
                `SERIRQ_ST_IDLE:
                    begin
                        serirq_oe <= 1'b0;
                        irq_cnt <= 5'h00;
                        serirq_o <= 1'b1;
 
                        if(found_start == 1'b1) // Wait for Start cycle
                        begin
                            current_irq <= irq_i;
                            if(irq_i[irq_cnt] == 1'b0) begin
                                serirq_oe <= 1'b1;
                                serirq_o <= 1'b0;
                            end
                            state <= `SERIRQ_ST_IRQ_R;
                        end
                        else if(irq_changed) begin
                            current_irq <= irq_i;
                            serirq_o <= 1'b0;
                            serirq_oe <= 1'b1;
                            state <= `SERIRQ_ST_IDLE;
                        end else
                            state <= `SERIRQ_ST_IDLE;
                    end
                `SERIRQ_ST_IRQ:
                    begin
                        if(irq_i[irq_cnt] == 1'b0) begin
                            serirq_oe <= 1'b1;
                            serirq_o <= 1'b0;
                        end
                            if(found_stop == 1'b0)
                                state <= `SERIRQ_ST_IRQ_R;
                            else
                                state <= `SERIRQ_ST_IDLE;
                    end
                `SERIRQ_ST_IRQ_R:
                    begin
                        serirq_o <= 1'b1;
                        if(found_stop == 1'b0)
                            state <= `SERIRQ_ST_IRQ_T;
                        else
                            state <= `SERIRQ_ST_IDLE;
                    end
                `SERIRQ_ST_IRQ_T:
                    begin
                        serirq_oe <= 1'b0;
                        if(irq_cnt == 5'h1f)
                        begin
                            state <= `SERIRQ_ST_WAIT_STOP;
                        end
                        else begin
                            irq_cnt <= irq_cnt + 1;
                            if(found_stop == 1'b0)
                                state <= `SERIRQ_ST_IRQ;
                            else
                                state <= `SERIRQ_ST_IDLE;
                        end
                    end
                    `SERIRQ_ST_WAIT_STOP:
                        begin
                            if(found_stop == 1'b0)
                                state <= `SERIRQ_ST_WAIT_STOP;
                            else
                                state <= `SERIRQ_ST_IDLE;
                        end
            endcase
        end
 
    reg [3:0] stop_clk_cnt;
 
    // Look for STOP cycles
    always @(posedge clk_i or negedge nrst_i)
        if(~nrst_i)
        begin
            found_stop <= 1'b0;
            found_start <= 1'b0;
            serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
            stop_clk_cnt <= 4'h0;
        end
        else begin
            if(serirq_i == 1'b0) begin
                stop_clk_cnt <= stop_clk_cnt + 1;
            end
            else begin
                case (stop_clk_cnt)
                    4'h2:
                        begin
                            found_stop <= 1'b1;
                            found_start <= 1'b0;
                            serirq_mode <= `SERIRQ_MODE_QUIET;
                        end
                    4'h3:
                        begin
                            found_stop <= 1'b1;
                            found_start <= 1'b0;
                            serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
                        end
                    4'h4:
                        begin
                            found_stop <= 1'b0;
                            found_start <= 1'b1;
                        end
                    4'h6:
                        begin
                            found_stop <= 1'b0;
                            found_start <= 1'b1;
                        end
                    4'h8:
                        begin
                            found_stop <= 1'b0;
                            found_start <= 1'b1;
                        end
                    default:
                        begin
                            found_stop <= 1'b0;
                            found_start <= 1'b0;
                        end
                    endcase
                    stop_clk_cnt <= 4'h0;
            end
        end
endmodule
 

Line No.	Rev	Author	Line
1	11	hharte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	19	hharte	`//// $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////`
4	11	hharte	`//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////`
5			`//// ////`
6			`//// This file is part of the Wishbone LPC Bridge project ////`
7			`//// http://www.opencores.org/projects/lpc/ ////`
8			`//// ////`
9			`//// Author: ////`
10			`//// - Howard M. Harte (hharte@opencores.org) ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2008 Howard M. Harte ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38
39			`timescale 1 ns / 1 ns
40
41			`include "../../rtl/verilog/serirq_defines.v"
42
43			`module serirq_slave(clk_i, nrst_i,`
44			`irq_i,`
45			`serirq_o, serirq_i, serirq_oe`
46			`);`
47			`// Wishbone Slave Interface`
48			`input clk_i;`
49			`input nrst_i; // Active low reset.`
50
51			`// SERIRQ Master Interface`
52			`output reg serirq_o; // SERIRQ output`
53			`input serirq_i; // SERIRQ Input`
54			`output reg serirq_oe; // SERIRQ Output Enable`
55
56			`input [31:0] irq_i; // IRQ Input Bus`
57			`reg [31:0] current_irq;`
58
59			`reg [12:0] state; // Current state`
60			`reg [4:0] irq_cnt; // IRQ Frame counter`
61
62			`reg found_stop;`
63			`reg found_start;`
64			`reg serirq_mode;`
65
66			`wire irq_changed = (serirq_mode & (current_irq != irq_i));`
67
68			`always @(posedge clk_i or negedge nrst_i)`
69			`if(~nrst_i)`
70			`begin`
71			state <= `SERIRQ_ST_IDLE;
72			`serirq_oe <= 1'b0;`
73			`serirq_o <= 4'b1;`
74			`irq_cnt <= 5'h00;`
75			`current_irq <= irq_i;`
76			`end`
77			`else begin`
78			`case(state)`
79			`SERIRQ_ST_IDLE:
80			`begin`
81			`serirq_oe <= 1'b0;`
82			`irq_cnt <= 5'h00;`
83			`serirq_o <= 1'b1;`
84
85			`if(found_start == 1'b1) // Wait for Start cycle`
86			`begin`
87			`current_irq <= irq_i;`
88			`if(irq_i[irq_cnt] == 1'b0) begin`
89			`serirq_oe <= 1'b1;`
90			`serirq_o <= 1'b0;`
91			`end`
92			state <= `SERIRQ_ST_IRQ_R;
93			`end`
94			`else if(irq_changed) begin`
95			`current_irq <= irq_i;`
96			`serirq_o <= 1'b0;`
97			`serirq_oe <= 1'b1;`
98			state <= `SERIRQ_ST_IDLE;
99			`end else`
100			state <= `SERIRQ_ST_IDLE;
101			`end`
102			`SERIRQ_ST_IRQ:
103			`begin`
104			`if(irq_i[irq_cnt] == 1'b0) begin`
105			`serirq_oe <= 1'b1;`
106			`serirq_o <= 1'b0;`
107			`end`
108			`if(found_stop == 1'b0)`
109			state <= `SERIRQ_ST_IRQ_R;
110			`else`
111			state <= `SERIRQ_ST_IDLE;
112			`end`
113			`SERIRQ_ST_IRQ_R:
114			`begin`
115			`serirq_o <= 1'b1;`
116			`if(found_stop == 1'b0)`
117			state <= `SERIRQ_ST_IRQ_T;
118			`else`
119			state <= `SERIRQ_ST_IDLE;
120			`end`
121			`SERIRQ_ST_IRQ_T:
122			`begin`
123			`serirq_oe <= 1'b0;`
124			`if(irq_cnt == 5'h1f)`
125			`begin`
126			state <= `SERIRQ_ST_WAIT_STOP;
127			`end`
128			`else begin`
129			`irq_cnt <= irq_cnt + 1;`
130			`if(found_stop == 1'b0)`
131			state <= `SERIRQ_ST_IRQ;
132			`else`
133			state <= `SERIRQ_ST_IDLE;
134			`end`
135			`end`
136			`SERIRQ_ST_WAIT_STOP:
137			`begin`
138			`if(found_stop == 1'b0)`
139			state <= `SERIRQ_ST_WAIT_STOP;
140			`else`
141			state <= `SERIRQ_ST_IDLE;
142			`end`
143			`endcase`
144			`end`
145
146			`reg [3:0] stop_clk_cnt;`
147
148			`// Look for STOP cycles`
149			`always @(posedge clk_i or negedge nrst_i)`
150			`if(~nrst_i)`
151			`begin`
152			`found_stop <= 1'b0;`
153			`found_start <= 1'b0;`
154			serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
155			`stop_clk_cnt <= 4'h0;`
156			`end`
157			`else begin`
158			`if(serirq_i == 1'b0) begin`
159			`stop_clk_cnt <= stop_clk_cnt + 1;`
160			`end`
161			`else begin`
162			`case (stop_clk_cnt)`
163			`4'h2:`
164			`begin`
165			`found_stop <= 1'b1;`
166			`found_start <= 1'b0;`
167	19	hharte	serirq_mode <= `SERIRQ_MODE_QUIET;
168	11	hharte	`end`
169			`4'h3:`
170			`begin`
171			`found_stop <= 1'b1;`
172			`found_start <= 1'b0;`
173	19	hharte	serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
174	11	hharte	`end`
175			`4'h4:`
176			`begin`
177			`found_stop <= 1'b0;`
178			`found_start <= 1'b1;`
179			`end`
180			`4'h6:`
181			`begin`
182			`found_stop <= 1'b0;`
183			`found_start <= 1'b1;`
184			`end`
185			`4'h8:`
186			`begin`
187			`found_stop <= 1'b0;`
188			`found_start <= 1'b1;`
189			`end`
190			`default:`
191			`begin`
192			`found_stop <= 1'b0;`
193			`found_start <= 1'b0;`
194			`end`
195			`endcase`
196			`stop_clk_cnt <= 4'h0;`
197			`end`
198			`end`
199			`endmodule`
200

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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [serirq_slave.v] - Blame information for rev 20