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hharte |
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// $Id: wb_dreq_host.v,v 1.1 2008-03-02 20:46:40 hharte Exp $
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//// wb_dreq_host.v - Wishbone DMA Controller for LPC Host ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 1 ns
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`include "../../rtl/verilog/wb_lpc_defines.v"
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module wb_dreq_host(clk_i, nrst_i,
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dma_chan_o, dma_req_o,
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ldrq_i
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);
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// Wishbone Slave Interface
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input clk_i;
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input nrst_i; // Active low reset.
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// Private DMA Interface
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output reg [2:0] dma_chan_o;
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output reg dma_req_o;
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// LPC Bus DMA Request Input
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input ldrq_i;
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reg [1:0] adr_cnt;
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reg [3:0] state;
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always @(posedge clk_i or negedge nrst_i)
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if(~nrst_i)
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begin
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state <= `LDRQ_ST_IDLE;
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dma_chan_o <= 3'h0;
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dma_req_o <= 3'h0;
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adr_cnt <= 2'b00;
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end
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else begin
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case(state)
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`LDRQ_ST_IDLE:
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begin
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dma_req_o <= 1'b0;
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if(~ldrq_i) begin
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state <= `LDRQ_ST_ADDR;
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adr_cnt <= 2'h2;
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end
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end
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`LDRQ_ST_ADDR:
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begin
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dma_chan_o[adr_cnt] <= ldrq_i;
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adr_cnt <= adr_cnt - 1;
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if(adr_cnt == 2'h0)
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state <= `LDRQ_ST_ACT;
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end
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`LDRQ_ST_ACT:
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begin
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dma_req_o <= ldrq_i;
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state <= `LDRQ_ST_DONE;
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end
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`LDRQ_ST_DONE:
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begin
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dma_req_o <= 1'b0;
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state <= `LDRQ_ST_IDLE;
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end
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endcase
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end
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endmodule
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