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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_dreq_periph.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  $Id: wb_dreq_periph.v,v 1.2 2008-03-05 05:50:59 hharte Exp $////
////  wb_dreq_periph.v - Wishbone DMA Requestor for LPC Peripheral////
////                                                              ////
////  This file is part of the Wishbone LPC Bridge project        ////
////  http://www.opencores.org/projects/wb_lpc/                   ////
////                                                              ////
////  Author:                                                     ////
////      - Howard M. Harte (hharte@opencores.org)                ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 Howard M. Harte                           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ns / 1 ns
 
`include "../../rtl/verilog/wb_lpc_defines.v"
 
module wb_dreq_periph(clk_i, nrst_i,
                      dma_chan_i, dma_req_i,
                      ldrq_o
);
    // Wishbone Slave Interface
    input       clk_i;
    input       nrst_i;             // Active low reset.
 
    // Private DMA Interface
    input [2:0] dma_chan_i;
    input       dma_req_i;
 
    // LPC Bus DMA Request Output
    output reg  ldrq_o;
 
    reg [1:0]   adr_cnt;
    reg [3:0]   state;
 
    always @(posedge clk_i or negedge nrst_i)
        if(~nrst_i)
        begin
            state <= `LDRQ_ST_IDLE;
            ldrq_o <= 1'b1; // LDRQ# Idle
            adr_cnt <= 2'b00;
        end
        else begin
            case(state)
                `LDRQ_ST_IDLE:
                    begin
                        if(dma_req_i) begin
                            ldrq_o <= 1'b0;
                            state <= `LDRQ_ST_ADDR;
                            adr_cnt <= 2'h2;
                        end
                    end
                `LDRQ_ST_ADDR:
                    begin
                        ldrq_o <= dma_chan_i[adr_cnt];
                        adr_cnt <= adr_cnt - 1;
 
                        if(adr_cnt == 2'h0)
                            state <= `LDRQ_ST_ACT;
                    end
                `LDRQ_ST_ACT:
                    begin
                        ldrq_o <= 1'b1;
                        state <= `LDRQ_ST_DONE;
                    end
                `LDRQ_ST_DONE:
                    begin
                        ldrq_o <= 1'b1;
                        state <= `LDRQ_ST_IDLE;
                    end
            endcase
        end
 
endmodule
 

Line No.	Rev	Author	Line
1	3	hharte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	6	hharte	`//// $Id: wb_dreq_periph.v,v 1.2 2008-03-05 05:50:59 hharte Exp $////`
4	3	hharte	`//// wb_dreq_periph.v - Wishbone DMA Requestor for LPC Peripheral////`
5			`//// ////`
6			`//// This file is part of the Wishbone LPC Bridge project ////`
7			`//// http://www.opencores.org/projects/wb_lpc/ ////`
8			`//// ////`
9			`//// Author: ////`
10			`//// - Howard M. Harte (hharte@opencores.org) ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2008 Howard M. Harte ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38
39			`timescale 1 ns / 1 ns
40
41			`include "../../rtl/verilog/wb_lpc_defines.v"
42
43			`module wb_dreq_periph(clk_i, nrst_i,`
44	6	hharte	`dma_chan_i, dma_req_i,`
45			`ldrq_o`
46	3	hharte	`);`
47	6	hharte	`// Wishbone Slave Interface`
48			`input clk_i;`
49			`input nrst_i; // Active low reset.`
50	3	hharte
51	6	hharte	`// Private DMA Interface`
52			`input [2:0] dma_chan_i;`
53			`input dma_req_i;`
54	3	hharte
55	6	hharte	`// LPC Bus DMA Request Output`
56			`output reg ldrq_o;`
57
58			`reg [1:0] adr_cnt;`
59			`reg [3:0] state;`
60
61			`always @(posedge clk_i or negedge nrst_i)`
62			`if(~nrst_i)`
63			`begin`
64			state <= `LDRQ_ST_IDLE;
65			`ldrq_o <= 1'b1; // LDRQ# Idle`
66			`adr_cnt <= 2'b00;`
67			`end`
68			`else begin`
69			`case(state)`
70			`LDRQ_ST_IDLE:
71			`begin`
72			`if(dma_req_i) begin`
73			`ldrq_o <= 1'b0;`
74			state <= `LDRQ_ST_ADDR;
75			`adr_cnt <= 2'h2;`
76			`end`
77			`end`
78			`LDRQ_ST_ADDR:
79			`begin`
80			`ldrq_o <= dma_chan_i[adr_cnt];`
81			`adr_cnt <= adr_cnt - 1;`
82
83			`if(adr_cnt == 2'h0)`
84			state <= `LDRQ_ST_ACT;
85			`end`
86			`LDRQ_ST_ACT:
87			`begin`
88			`ldrq_o <= 1'b1;`
89			state <= `LDRQ_ST_DONE;
90			`end`
91			`LDRQ_ST_DONE:
92			`begin`
93			`ldrq_o <= 1'b1;`
94			state <= `LDRQ_ST_IDLE;
95			`end`
96			`endcase`
97			`end`
98	3	hharte
99			`endmodule`
100

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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_dreq_periph.v] - Blame information for rev 6