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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_lpc_defines.v] - Blame information for rev 3

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  wb_lpc_defines.v                                            ////
////                                                              ////
////  This file is part of the Wishbone LPC Bridge project        ////
////  http://www.opencores.org/projects/wb_lpc/                   ////
////                                                              ////
////  Author:                                                     ////
////      - Howard M. Harte (hharte@opencores.org)                ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 Howard M. Harte                           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// Wishbone LPC Master/Slave Interface Definitions
 
`define LPC_START                       4'b0000
`define LPC_STOP                        4'b1111
`define LPC_FW_READ             4'b1101
`define LPC_FW_WRITE            4'b1110
 
`define LPC_SYNC_READY  4'b0000                         // LPC Sync Ready
`define LPC_SYNC_SWAIT  4'b0101                         // LPC Sync Short Wait
`define LPC_SYNC_LWAIT  4'b0110                         // LPC Sync Long Wait
`define LPC_SYNC_MORE   4'b1001                         // LPC Sync Ready More (DMA only)
`define LPC_SYNC_ERROR  4'b1010                         // LPC Sync Error
 
`define LPC_ST_IDLE             13'h000                         // LPC Idle state
`define LPC_ST_START            13'h001                         // LPC Start state
`define LPC_ST_CYCTYP   13'h002                         // LPC Cycle Type State
`define LPC_ST_ADDR             13'h004                         // LPC Address state (4 cycles)
`define LPC_ST_CHAN             13'h008                         // LPC Address state (4 cycles)
`define LPC_ST_SIZE             13'h010                         // LPC Address state (4 cycles)
`define LPC_ST_H_DATA   13'h020                         // LPC Host Data state (2 cycles)
`define LPC_ST_P_DATA   13'h040                         // LPC Peripheral Data state (2 cycles)
`define LPC_ST_H_TAR1   13'h080                         // LPC Host Turnaround 1 (Drive LAD 4'hF)
`define LPC_ST_H_TAR2   13'h100                         // LPC Host Turnaround 2 (Float LAD)
`define LPC_ST_P_TAR1   13'h200                         // LPC Peripheral Turnaround 1 (Drive LAD = 4'hF)
`define LPC_ST_P_TAR2   13'h400                         // LPC Peripheral Turnaround 2 (Float LAD)
`define LPC_ST_SYNC             13'h800                         // LPC Sync State (may be multiple cycles for wait-states)
`define LPC_ST_P_WAIT1  13'h1000                                // LPC Sync State (may be multiple cycles for wait-states)
 
 
`define WB_SEL_BYTE             4'b0001                         // Byte Transfer
`define WB_SEL_SHORT            4'b0011                         // Short Transfer
`define WB_SEL_WORD             4'b1111                         // Word Transfer
 
`define WB_TGA_MEM              2'b00                                   // Memory Cycle
`define WB_TGA_IO                       2'b01                                   // I/O Cycle
`define WB_TGA_FW                       2'b10                                   // Firmware Cycle
`define WB_TGA_DMA              2'b11                                   // DMA Cycle
 
// LDRQ States
 
`define LDRQ_ST_IDLE            4'h0
`define LDRQ_ST_ADDR            4'h1
`define LDRQ_ST_ACT             4'h2
`define LDRQ_ST_DONE            4'h4

Line No.	Rev	Author	Line
1	3	hharte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// wb_lpc_defines.v ////`
4			`//// ////`
5			`//// This file is part of the Wishbone LPC Bridge project ////`
6			`//// http://www.opencores.org/projects/wb_lpc/ ////`
7			`//// ////`
8			`//// Author: ////`
9			`//// - Howard M. Harte (hharte@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2008 Howard M. Harte ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37
38			`// Wishbone LPC Master/Slave Interface Definitions`
39
40			`define LPC_START 4'b0000
41			`define LPC_STOP 4'b1111
42			`define LPC_FW_READ 4'b1101
43			`define LPC_FW_WRITE 4'b1110
44
45			`define LPC_SYNC_READY 4'b0000 // LPC Sync Ready
46			`define LPC_SYNC_SWAIT 4'b0101 // LPC Sync Short Wait
47			`define LPC_SYNC_LWAIT 4'b0110 // LPC Sync Long Wait
48			`define LPC_SYNC_MORE 4'b1001 // LPC Sync Ready More (DMA only)
49			`define LPC_SYNC_ERROR 4'b1010 // LPC Sync Error
50
51			`define LPC_ST_IDLE 13'h000 // LPC Idle state
52			`define LPC_ST_START 13'h001 // LPC Start state
53			`define LPC_ST_CYCTYP 13'h002 // LPC Cycle Type State
54			`define LPC_ST_ADDR 13'h004 // LPC Address state (4 cycles)
55			`define LPC_ST_CHAN 13'h008 // LPC Address state (4 cycles)
56			`define LPC_ST_SIZE 13'h010 // LPC Address state (4 cycles)
57			`define LPC_ST_H_DATA 13'h020 // LPC Host Data state (2 cycles)
58			`define LPC_ST_P_DATA 13'h040 // LPC Peripheral Data state (2 cycles)
59			`define LPC_ST_H_TAR1 13'h080 // LPC Host Turnaround 1 (Drive LAD 4'hF)
60			`define LPC_ST_H_TAR2 13'h100 // LPC Host Turnaround 2 (Float LAD)
61			`define LPC_ST_P_TAR1 13'h200 // LPC Peripheral Turnaround 1 (Drive LAD = 4'hF)
62			`define LPC_ST_P_TAR2 13'h400 // LPC Peripheral Turnaround 2 (Float LAD)
63			`define LPC_ST_SYNC 13'h800 // LPC Sync State (may be multiple cycles for wait-states)
64			`define LPC_ST_P_WAIT1 13'h1000 // LPC Sync State (may be multiple cycles for wait-states)
65
66
67			`define WB_SEL_BYTE 4'b0001 // Byte Transfer
68			`define WB_SEL_SHORT 4'b0011 // Short Transfer
69			`define WB_SEL_WORD 4'b1111 // Word Transfer
70
71			`define WB_TGA_MEM 2'b00 // Memory Cycle
72			`define WB_TGA_IO 2'b01 // I/O Cycle
73			`define WB_TGA_FW 2'b10 // Firmware Cycle
74			`define WB_TGA_DMA 2'b11 // DMA Cycle
75
76			`// LDRQ States`
77
78			`define LDRQ_ST_IDLE 4'h0
79			`define LDRQ_ST_ADDR 4'h1
80			`define LDRQ_ST_ACT 4'h2
81			`define LDRQ_ST_DONE 4'h4

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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_lpc_defines.v] - Blame information for rev 3