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hharte |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// $Id: wb_lpc_host.v,v 1.1 2008-03-02 20:46:40 hharte Exp $
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//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 1 ns
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`include "../../rtl/verilog/wb_lpc_defines.v"
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// I/O Write I/O Read DMA Read DMA Write
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//
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// States - 1. H Start H Start H Start H Start
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// 2. H CYCTYPE+DIR H CYCTYPE+DIR H CYCTYPE+DIR H CYCTYPE+DIR
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// 3. H Addr (4) H Addr (4) H CHAN+TC H CHAN+TC
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// H SIZE H SIZE
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// 4. H Data (2) H TAR (2) +-H DATA (2) H TAR (2)
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// 5. H TAR (2) P SYNC (1+) | H TAR (2) +-P SYNC (1+)
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// 6. P SYNC (1+) P DATA (2) | H SYNC (1+) +-P DATA (2)
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// 7. P TAR (2) P TAR (2) +-P TAR (2) P TAR
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//
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module wb_lpc_host(clk_i, nrst_i, wbs_adr_i, wbs_dat_o, wbs_dat_i, wbs_sel_i, wbs_tga_i, wbs_we_i,
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wbs_stb_i, wbs_cyc_i, wbs_ack_o,
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dma_chan_i, dma_tc_i,
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lframe_o, lad_i, lad_o, lad_oe
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);
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// Wishbone Slave Interface
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input clk_i;
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input nrst_i; // Active low reset.
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input [31:0] wbs_adr_i;
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output [31:0] wbs_dat_o;
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input [31:0] wbs_dat_i;
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input [3:0] wbs_sel_i;
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input [1:0] wbs_tga_i;
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input wbs_we_i;
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input wbs_stb_i;
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input wbs_cyc_i;
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output reg wbs_ack_o;
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// LPC Master Interface
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output reg lframe_o; // LPC Frame output (active high)
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output reg lad_oe; // LPC AD Output Enable
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input [3:0] lad_i; // LPC AD Input Bus
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output reg [3:0] lad_o; // LPC AD Output Bus
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// DMA-Specific sideband signals
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input [2:0] dma_chan_i; // DMA Channel
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input dma_tc_i; // DMA Terminal Count
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reg [12:0] state; // Current state
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reg [2:0] adr_cnt; // Address nibbe counter
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reg [3:0] dat_cnt; // Data nibble counter
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reg [2:0] xfr_len; // Number of nibbls for transfer
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wire [2:0] byte_cnt = dat_cnt[3:1]; // Byte Counter
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wire nibble_cnt = dat_cnt[0]; // Nibble counter
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reg [31:0] lpc_dat_i; // Temporary storage for input word.
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//
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// generate wishbone register signals
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wire wbs_acc = wbs_cyc_i & wbs_stb_i; // Wishbone access
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wire wbs_wr = wbs_acc & wbs_we_i; // Wishbone write access
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// Memory Cycle (tga== 1'b00) is bit 2=1 for LPC Cycle Type.
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wire mem_xfr = (wbs_tga_i == `WB_TGA_MEM);
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wire dma_xfr = (wbs_tga_i == `WB_TGA_DMA);
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wire fw_xfr = (wbs_tga_i == `WB_TGA_FW);
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assign wbs_dat_o[31:0] = lpc_dat_i;
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always @(posedge clk_i or negedge nrst_i)
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if(~nrst_i)
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begin
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state <= `LPC_ST_IDLE;
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lframe_o <= 1'b0;
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wbs_ack_o <= 1'b0;
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lad_oe <= 1'b0;
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lad_o <= 4'b0;
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adr_cnt <= 3'b0;
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dat_cnt <= 4'h0;
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xfr_len <= 3'b000;
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lpc_dat_i <= 32'h00000000;
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end
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else begin
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case(state)
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`LPC_ST_IDLE:
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begin
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wbs_ack_o <= 1'b0;
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lframe_o <= 1'b0;
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dat_cnt <= 4'h0;
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if(wbs_acc) // Wishbone access starts LPC transaction
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state <= `LPC_ST_START;
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else
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state <= `LPC_ST_IDLE;
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end
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`LPC_ST_START:
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begin
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lframe_o <= 1'b1;
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if(~fw_xfr) begin // For Memory and I/O Cycles
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lad_o <= `LPC_START;
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state <= `LPC_ST_CYCTYP;
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end
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else begin // Firmware Read and Write Cycles
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if(wbs_wr)
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lad_o <= `LPC_FW_WRITE;
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else
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lad_o <= `LPC_FW_READ;
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state <= `LPC_ST_ADDR;
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end
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lad_oe <= 1'b1;
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adr_cnt <= ((mem_xfr | fw_xfr) ? 3'b000 : 3'b100);
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end
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`LPC_ST_CYCTYP:
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begin
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lframe_o <= 1'b0;
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lad_oe <= 1'b1;
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if(~dma_xfr)
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begin
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lad_o <= {1'b0,mem_xfr,wbs_wr,1'b0}; // Cycle Type/Direction for I/O or MEM
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state <= `LPC_ST_ADDR;
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end
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else // it is DMA
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begin
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lad_o <= {1'b1,1'b0,~wbs_wr,1'b0}; // Cycle Type/Direction for DMA, r/w is inverted for DMA
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state <= `LPC_ST_CHAN;
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end
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end
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`LPC_ST_ADDR: // Output four nubbles of address.
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begin
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lframe_o <= 1'b0; // In case we came here from a Firmware cycle, which skips CYCTYP.
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// The LPC Bus Address is sent across the bus a nibble at a time;
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// however, the most significant nibble is sent first. For firmware and
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// memory cycles, the address is 32-bits. Actually, for memeory accesses,
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// the most significant nibble is known as the IDSEL field. For I/O,
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// the address is only 16-bits wide.
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case(adr_cnt)
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3'h0:
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lad_o <= wbs_adr_i[31:28];
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3'h1:
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lad_o <= wbs_adr_i[27:24];
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3'h2:
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lad_o <= wbs_adr_i[23:20];
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3'h3:
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lad_o <= wbs_adr_i[19:16];
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3'h4:
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lad_o <= wbs_adr_i[15:12];
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3'h5:
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lad_o <= wbs_adr_i[11:8];
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3'h6:
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lad_o <= wbs_adr_i[7:4];
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3'h7:
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lad_o <= wbs_adr_i[3:0];
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endcase
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adr_cnt <= adr_cnt + 1;
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if(adr_cnt == 4'h7) // Last address nibble.
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begin
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if(~fw_xfr)
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if(wbs_wr)
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state <= `LPC_ST_H_DATA;
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else
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state <= `LPC_ST_H_TAR1;
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else // For firmware read/write, we need to transfer the MSIZE nibble
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state <= `LPC_ST_SIZE;
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end
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else
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state <= `LPC_ST_ADDR;
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lad_oe <= 1'b1;
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xfr_len <= 3'b001; // One Byte Transfer
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end
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`LPC_ST_CHAN:
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begin
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lad_o <= {dma_tc_i, dma_chan_i};
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state <= `LPC_ST_SIZE;
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end
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`LPC_ST_SIZE:
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begin
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case(wbs_sel_i)
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`WB_SEL_BYTE:
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begin
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xfr_len <= 3'b001;
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lad_o <= 4'h0;
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end
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`WB_SEL_SHORT:
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begin
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xfr_len <= 3'b010;
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lad_o <= 4'h1;
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end
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`WB_SEL_WORD:
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begin
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xfr_len <= 3'b100;
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if(fw_xfr) // Firmware transfer uses '2' for 4-byte transfer.
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lad_o <= 4'h2;
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else // DMA uses '3' for 4-byte transfer.
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lad_o <= 4'h3;
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end
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default:
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begin
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xfr_len <= 3'b001;
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lad_o <= 4'h0;
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end
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endcase
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if(wbs_wr)
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state <= `LPC_ST_H_DATA;
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else
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state <= `LPC_ST_H_TAR1;
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end
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`LPC_ST_H_DATA:
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begin
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lad_oe <= 1'b1;
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case(dat_cnt) // We only support a single byte for I/O.
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4'h0:
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lad_o <= wbs_dat_i[3:0];
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4'h1:
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lad_o <= wbs_dat_i[7:4];
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4'h2:
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lad_o <= wbs_dat_i[11:8];
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4'h3:
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lad_o <= wbs_dat_i[15:12];
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4'h4:
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lad_o <= wbs_dat_i[19:16];
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4'h5:
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lad_o <= wbs_dat_i[23:20];
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4'h6:
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lad_o <= wbs_dat_i[27:24];
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4'h7:
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lad_o <= wbs_dat_i[31:28];
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default:
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lad_o <= 4'hx;
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endcase
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dat_cnt <= dat_cnt + 1;
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| 272 |
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if(nibble_cnt == 1'b1) // end of byte
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begin
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| 274 |
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state <= `LPC_ST_H_TAR1;
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end
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| 276 |
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else
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| 277 |
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state <= `LPC_ST_H_DATA;
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end
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| 279 |
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| 280 |
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`LPC_ST_H_TAR1:
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| 281 |
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begin
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| 282 |
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lad_o <= 4'b1111; // Drive LAD high
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| 283 |
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lad_oe <= 1'b1;
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| 284 |
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state <= `LPC_ST_H_TAR2;
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| 285 |
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end
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| 286 |
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`LPC_ST_H_TAR2:
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| 287 |
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begin
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| 288 |
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lad_oe <= 1'b0; // float LAD
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| 289 |
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state <= `LPC_ST_SYNC;
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| 290 |
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end
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| 291 |
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`LPC_ST_SYNC:
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| 292 |
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begin
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| 293 |
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lad_oe <= 1'b0; // float LAD
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| 294 |
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if(lad_i == `LPC_SYNC_READY) begin
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| 295 |
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if(wbs_wr) begin
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| 296 |
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state <= `LPC_ST_P_TAR1;
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| 297 |
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end
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| 298 |
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else
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| 299 |
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state <= `LPC_ST_P_DATA;
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| 300 |
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end
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| 301 |
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else
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| 302 |
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state <= `LPC_ST_SYNC;
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end
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| 304 |
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| 305 |
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`LPC_ST_P_DATA:
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| 306 |
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begin
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| 307 |
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case(dat_cnt)
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| 308 |
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4'h0:
|
| 309 |
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lpc_dat_i[3:0] <= lad_i;
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| 310 |
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4'h1:
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| 311 |
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lpc_dat_i[7:4] <= lad_i;
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| 312 |
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4'h2:
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| 313 |
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lpc_dat_i[11:8] <= lad_i;
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| 314 |
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4'h3:
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| 315 |
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lpc_dat_i[15:12] <= lad_i;
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| 316 |
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4'h4:
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| 317 |
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lpc_dat_i[19:16] <= lad_i;
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| 318 |
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4'h5:
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| 319 |
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lpc_dat_i[23:20] <= lad_i;
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| 320 |
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4'h6:
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| 321 |
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lpc_dat_i[27:24] <= lad_i;
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| 322 |
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4'h7:
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| 323 |
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lpc_dat_i[31:28] <= lad_i;
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| 324 |
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endcase
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| 325 |
|
|
|
| 326 |
|
|
dat_cnt <= dat_cnt + 1;
|
| 327 |
|
|
|
| 328 |
|
|
if(nibble_cnt == 1'b1) // Byte transfer complete
|
| 329 |
|
|
if (byte_cnt == xfr_len-1) // End of data transfer phase
|
| 330 |
|
|
state <= `LPC_ST_P_TAR1;
|
| 331 |
|
|
else
|
| 332 |
|
|
state <= `LPC_ST_SYNC;
|
| 333 |
|
|
else // Go to next nibble
|
| 334 |
|
|
state <= `LPC_ST_P_DATA;
|
| 335 |
|
|
end
|
| 336 |
|
|
`LPC_ST_P_TAR1:
|
| 337 |
|
|
begin
|
| 338 |
|
|
lad_oe <= 1'b0;
|
| 339 |
|
|
// state <= `LPC_ST_P_TAR2;
|
| 340 |
|
|
// end
|
| 341 |
|
|
// `LPC_ST_P_TAR2:
|
| 342 |
|
|
// begin
|
| 343 |
|
|
// lad_oe <= 1'b0; // float LAD
|
| 344 |
|
|
if(byte_cnt == xfr_len) begin
|
| 345 |
|
|
state <= `LPC_ST_IDLE;
|
| 346 |
|
|
wbs_ack_o <= wbs_acc;
|
| 347 |
|
|
end
|
| 348 |
|
|
else begin
|
| 349 |
|
|
if(wbs_wr) begin // DMA READ (Host to Peripheral)
|
| 350 |
|
|
state <= `LPC_ST_H_DATA;
|
| 351 |
|
|
end
|
| 352 |
|
|
else begin // unhandled READ case
|
| 353 |
|
|
state <= `LPC_ST_IDLE;
|
| 354 |
|
|
end
|
| 355 |
|
|
end
|
| 356 |
|
|
end
|
| 357 |
|
|
endcase
|
| 358 |
|
|
end
|
| 359 |
|
|
|
| 360 |
|
|
endmodule
|
| 361 |
|
|
|
| 362 |
|
|
|
