OpenCores
URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk

Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_regfile.v] - Blame information for rev 20

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 hharte 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 17 hharte 
////  $Id: wb_regfile.v,v 1.3 2008-07-26 19:15:32 hharte Exp $    ////
4 3 hharte 
////  wb_regfile.v - Small Wishbone register file for testing     ////
5 
////                                                              ////
6 
////  This file is part of the Wishbone LPC Bridge project        ////
7 
////  http://www.opencores.org/projects/wb_lpc/                   ////
8 
////                                                              ////
9 
////  Author:                                                     ////
10 
////      - Howard M. Harte (hharte@opencores.org)                ////
11 
////                                                              ////
12 
//////////////////////////////////////////////////////////////////////
13 
////                                                              ////
14 
//// Copyright (C) 2008 Howard M. Harte                           ////
15 
////                                                              ////
16 
//// This source file may be used and distributed without         ////
17 
//// restriction provided that this copyright statement is not    ////
18 
//// removed from the file and that any derivative work contains  ////
19 
//// the original copyright notice and the associated disclaimer. ////
20 
////                                                              ////
21 
//// This source file is free software; you can redistribute it   ////
22 
//// and/or modify it under the terms of the GNU Lesser General   ////
23 
//// Public License as published by the Free Software Foundation; ////
24 
//// either version 2.1 of the License, or (at your option) any   ////
25 
//// later version.                                               ////
26 
////                                                              ////
27 
//// This source is distributed in the hope that it will be       ////
28 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
29 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
30 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
31 
//// details.                                                     ////
32 
////                                                              ////
33 
//// You should have received a copy of the GNU Lesser General    ////
34 
//// Public License along with this source; if not, download it   ////
35 
//// from http://www.opencores.org/lgpl.shtml                     ////
36 
////                                                              ////
37 
//////////////////////////////////////////////////////////////////////
38 
 
39 
module wb_regfile (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
40 17 hharte 
                   wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, ws_i, datareg0, datareg1);
41 3 hharte 
 
42 6 hharte 
    input          clk_i;
43 
    input          nrst_i;
44 17 hharte 
    input    [3:0] wb_adr_i;
45 6 hharte 
    output reg [31:0] wb_dat_o;
46 
    input   [31:0] wb_dat_i;
47 
    input    [3:0] wb_sel_i;
48 
    input          wb_we_i;
49 
    input          wb_stb_i;
50 
    input          wb_cyc_i;
51 
    output reg     wb_ack_o;
52 17 hharte 
    output         wb_err_o;
53 
    input    [7:0] ws_i;
54 6 hharte 
    output  [31:0] datareg0;
55 
    output  [31:0] datareg1;
56 17 hharte 
    reg      [7:0] waitstate;
57 3 hharte 
 
58 6 hharte 
    //
59 
    // generate wishbone register bank writes
60 
    wire wb_acc = wb_cyc_i & wb_stb_i;    // WISHBONE access
61 
    wire wb_wr  = wb_acc & wb_we_i;       // WISHBONE write access
62 3 hharte 
 
63 6 hharte 
    reg [7:0]   datareg0_0;
64 
    reg [7:0]   datareg0_1;
65 
    reg [7:0]   datareg0_2;
66 
    reg [7:0]   datareg0_3;
67 3 hharte 
 
68 6 hharte 
    reg [7:0]   datareg1_0;
69 
    reg [7:0]   datareg1_1;
70 
    reg [7:0]   datareg1_2;
71 
    reg [7:0]   datareg1_3;
72 3 hharte 
 
73 6 hharte 
    always @(posedge clk_i or negedge nrst_i)
74 
        if (~nrst_i)                // reset registers
75 
            begin
76 
                datareg0_0 <= 8'h00;
77 
                datareg0_1 <= 8'h01;
78 
                datareg0_2 <= 8'h02;
79 
                datareg0_3 <= 8'h03;
80 
                datareg1_0 <= 8'h10;
81 
                datareg1_1 <= 8'h11;
82 
                datareg1_2 <= 8'h12;
83 
                datareg1_3 <= 8'h13;
84 17 hharte 
                wb_ack_o <= 1'b0;
85 
                waitstate <= 4'b0;
86 
                                         wb_dat_o <= 32'h00000000;
87 6 hharte 
            end
88 
        else if(wb_wr)          // wishbone write cycle
89 
            case (wb_sel_i)
90 
                4'b0000:
91 
                    case (wb_adr_i)         // synopsys full_case parallel_case
92 17 hharte 
                        4'b0000: datareg0_0 <= wb_dat_i[7:0];
93 
                        4'b0001: datareg0_1 <= wb_dat_i[7:0];
94 
                        4'b0010: datareg0_2 <= wb_dat_i[7:0];
95 
                        4'b0011: datareg0_3 <= wb_dat_i[7:0];
96 
                        4'b0100: datareg1_0 <= wb_dat_i[7:0];
97 
                        4'b0101: datareg1_1 <= wb_dat_i[7:0];
98 
                        4'b0110: datareg1_2 <= wb_dat_i[7:0];
99 
                        4'b0111: datareg1_3 <= wb_dat_i[7:0];
100 6 hharte 
                    endcase
101 
                4'b0001:
102 
                    case (wb_adr_i)         // synopsys full_case parallel_case
103 17 hharte 
                        4'b0000: datareg0_0 <= wb_dat_i[7:0];
104 
                        4'b0001: datareg0_1 <= wb_dat_i[7:0];
105 
                        4'b0010: datareg0_2 <= wb_dat_i[7:0];
106 
                        4'b0011: datareg0_3 <= wb_dat_i[7:0];
107 
                        4'b0100: datareg1_0 <= wb_dat_i[7:0];
108 
                        4'b0101: datareg1_1 <= wb_dat_i[7:0];
109 
                        4'b0110: datareg1_2 <= wb_dat_i[7:0];
110 
                        4'b0111: datareg1_3 <= wb_dat_i[7:0];
111 6 hharte 
                    endcase
112 
                4'b0011:
113 
                    {datareg0_1, datareg0_0} <= wb_dat_i[15:0];
114 
//                  case (wb_adr_i)         // synopsys full_case parallel_case
115 
//                      3'b000: {datareg0_1, datareg0_0} <= wb_dat_i[15:0];
116 
//                  endcase
117 
                4'b1111:
118 
                    {datareg0_3, datareg0_2, datareg0_1, datareg0_0} <= wb_dat_i[31:0];
119 
//                  case (wb_adr_i)         // synopsys full_case parallel_case
120 
//                      3'b000: {datareg0_3, datareg0_2, datareg0_1, datareg0_0} <= wb_dat_i[31:0];
121 
//                  endcase
122 3 hharte 
 
123 6 hharte 
            endcase
124 
    // generate dat_o
125 
    always @(posedge clk_i)
126 
        case (wb_sel_i)
127 
            4'b0000:
128 
                case (wb_adr_i)     // synopsys full_case parallel_case
129 17 hharte 
                    4'b0000: wb_dat_o[7:0] <= datareg0_0;
130 
                    4'b0001: wb_dat_o[7:0] <= datareg0_1;
131 
                    4'b0010: wb_dat_o[7:0] <= datareg0_2;
132 
                    4'b0011: wb_dat_o[7:0] <= datareg0_3;
133 
                    4'b0100: wb_dat_o[7:0] <= datareg1_0;
134 
                    4'b0101: wb_dat_o[7:0] <= datareg1_1;
135 
                    4'b0110: wb_dat_o[7:0] <= datareg1_2;
136 
                    4'b0111: wb_dat_o[7:0] <= datareg1_3;
137 6 hharte 
                endcase
138 
            4'b0001:
139 
                case (wb_adr_i)     // synopsys full_case parallel_case
140 17 hharte 
                    4'b0000: wb_dat_o[7:0] <= datareg0_0;
141 
                    4'b0001: wb_dat_o[7:0] <= datareg0_1;
142 
                    4'b0010: wb_dat_o[7:0] <= datareg0_2;
143 
                    4'b0011: wb_dat_o[7:0] <= datareg0_3;
144 
                    4'b0100: wb_dat_o[7:0] <= datareg1_0;
145 
                    4'b0101: wb_dat_o[7:0] <= datareg1_1;
146 
                    4'b0110: wb_dat_o[7:0] <= datareg1_2;
147 
                    4'b0111: wb_dat_o[7:0] <= datareg1_3;
148 6 hharte 
                endcase
149 
            4'b0011:
150 
                    wb_dat_o[15:0] <= {datareg0_1, datareg0_0};
151 
            4'b1111:
152 
                    wb_dat_o[31:0] <= {datareg0_3, datareg0_2, datareg0_1, datareg0_0};
153 
        endcase
154 
 
155 3 hharte 
   // generate ack_o
156 17 hharte 
    always @(posedge clk_i or negedge nrst_i)
157 
        if (nrst_i) begin            // not in reset
158 
            if (ws_i == 0) begin
159 
                wb_ack_o <= wb_acc & !wb_ack_o;
160 
                end else
161 
            if((waitstate == 4'b0) && (ws_i != 0)) begin
162 
                wb_ack_o <= 1'b0;
163 
                if(wb_acc) begin
164 
                    waitstate <= waitstate + 1;
165 
                end
166 
            end
167 
            else begin
168 
                if(wb_acc) waitstate <= waitstate + 1;
169 
                if(waitstate == ws_i) begin
170 
                    if(wb_acc) wb_ack_o <= 1'b1;
171 
                    waitstate <= 1'b0;
172 
                end
173 
            end
174 
        end
175 3 hharte 
 
176 6 hharte 
    assign datareg0 = { datareg0_3, datareg0_2, datareg0_1, datareg0_0 };
177 
    assign datareg1 = { datareg1_3, datareg1_2, datareg1_1, datareg1_0 };
178 3 hharte 
 
179 17 hharte 
    // Generate an error for registers 0x8-0xF
180 
    assign wb_err_o = wb_ack_o & wb_adr_i[3];
181 
 
182 3 hharte 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.