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hharte |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// $Id: wb_regfile.v,v 1.1 2008-03-02 20:46:40 hharte Exp $
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//// wb_regfile.v - Small Wishbone register file for testing ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module wb_regfile (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
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wb_stb_i, wb_cyc_i, wb_ack_o, datareg0, datareg1);
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input clk_i;
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input nrst_i;
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input [2:0] wb_adr_i;
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output reg [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_cyc_i;
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output reg wb_ack_o;
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output [31:0] datareg0;
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output [31:0] datareg1;
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//
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// generate wishbone register bank writes
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wire wb_acc = wb_cyc_i & wb_stb_i; // WISHBONE access
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wire wb_wr = wb_acc & wb_we_i; // WISHBONE write access
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reg [7:0] datareg0_0;
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reg [7:0] datareg0_1;
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reg [7:0] datareg0_2;
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reg [7:0] datareg0_3;
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reg [7:0] datareg1_0;
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reg [7:0] datareg1_1;
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reg [7:0] datareg1_2;
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reg [7:0] datareg1_3;
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always @(posedge clk_i or negedge nrst_i)
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if (~nrst_i) // reset registers
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begin
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datareg0_0 <= 8'h00;
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datareg0_1 <= 8'h01;
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datareg0_2 <= 8'h02;
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datareg0_3 <= 8'h03;
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datareg1_0 <= 8'h10;
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datareg1_1 <= 8'h11;
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datareg1_2 <= 8'h12;
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datareg1_3 <= 8'h13;
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end
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else if(wb_wr) // wishbone write cycle
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case (wb_sel_i)
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4'b0000:
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case (wb_adr_i) // synopsys full_case parallel_case
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3'b000: datareg0_0 <= wb_dat_i[7:0];
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3'b001: datareg0_1 <= wb_dat_i[7:0];
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3'b010: datareg0_2 <= wb_dat_i[7:0];
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3'b011: datareg0_3 <= wb_dat_i[7:0];
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3'b100: datareg1_0 <= wb_dat_i[7:0];
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3'b101: datareg1_1 <= wb_dat_i[7:0];
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3'b110: datareg1_2 <= wb_dat_i[7:0];
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3'b111: datareg1_3 <= wb_dat_i[7:0];
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endcase
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4'b0001:
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case (wb_adr_i) // synopsys full_case parallel_case
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3'b000: datareg0_0 <= wb_dat_i[7:0];
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3'b001: datareg0_1 <= wb_dat_i[7:0];
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3'b010: datareg0_2 <= wb_dat_i[7:0];
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3'b011: datareg0_3 <= wb_dat_i[7:0];
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3'b100: datareg1_0 <= wb_dat_i[7:0];
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3'b101: datareg1_1 <= wb_dat_i[7:0];
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3'b110: datareg1_2 <= wb_dat_i[7:0];
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3'b111: datareg1_3 <= wb_dat_i[7:0];
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endcase
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4'b0011:
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{datareg0_1, datareg0_0} <= wb_dat_i[15:0];
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// case (wb_adr_i) // synopsys full_case parallel_case
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// 3'b000: {datareg0_1, datareg0_0} <= wb_dat_i[15:0];
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// endcase
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4'b1111:
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{datareg0_3, datareg0_2, datareg0_1, datareg0_0} <= wb_dat_i[31:0];
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// case (wb_adr_i) // synopsys full_case parallel_case
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// 3'b000: {datareg0_3, datareg0_2, datareg0_1, datareg0_0} <= wb_dat_i[31:0];
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// endcase
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endcase
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//
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// generate dat_o
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always @(posedge clk_i)
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case (wb_sel_i)
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4'b0000:
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case (wb_adr_i) // synopsys full_case parallel_case
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3'b000: wb_dat_o[7:0] <= datareg0_0;
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3'b001: wb_dat_o[7:0] <= datareg0_1;
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3'b010: wb_dat_o[7:0] <= datareg0_2;
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3'b011: wb_dat_o[7:0] <= datareg0_3;
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3'b100: wb_dat_o[7:0] <= datareg1_0;
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3'b101: wb_dat_o[7:0] <= datareg1_1;
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3'b110: wb_dat_o[7:0] <= datareg1_2;
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3'b111: wb_dat_o[7:0] <= datareg1_3;
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endcase
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4'b0001:
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case (wb_adr_i) // synopsys full_case parallel_case
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3'b000: wb_dat_o[7:0] <= datareg0_0;
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3'b001: wb_dat_o[7:0] <= datareg0_1;
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3'b010: wb_dat_o[7:0] <= datareg0_2;
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3'b011: wb_dat_o[7:0] <= datareg0_3;
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3'b100: wb_dat_o[7:0] <= datareg1_0;
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3'b101: wb_dat_o[7:0] <= datareg1_1;
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3'b110: wb_dat_o[7:0] <= datareg1_2;
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3'b111: wb_dat_o[7:0] <= datareg1_3;
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endcase
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4'b0011:
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wb_dat_o[15:0] <= {datareg0_1, datareg0_0};
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4'b1111:
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wb_dat_o[31:0] <= {datareg0_3, datareg0_2, datareg0_1, datareg0_0};
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endcase
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//
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// generate ack_o
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always @(posedge clk_i)
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wb_ack_o <= #1 wb_acc & !wb_ack_o;
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assign datareg0 = { datareg0_3, datareg0_2, datareg0_1, datareg0_0 };
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assign datareg1 = { datareg1_3, datareg1_2, datareg1_1, datareg1_0 };
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endmodule
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