OpenCores
URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk

Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [sim/] [wb_lpc_sim/] [wb_lpc_sim.ise] - Blame information for rev 17

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 hharte
PK
2
 
3
 
4 14 hharte
 
5 3 hharte
 
6 14 hharte
P3__OBJSTORE__/HierarchicalDesign/HDProject/HDProjectPK
7
JfXX:__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl    17/wb_lpc_hostTS_EXPANDEDTS_FRAGCOVEREDTS_PACKEDTS_ROUTEDTS_SYNTHESISPK
8
";<<7__OBJSTORE__/HierarchicalDesign/__stored_object_table__(:PK
9
__OBJSTORE__/ISimPlugin/PK
10 3 hharte
(__OBJSTORE__/ISimPlugin/SignalOrdering1/PK
11
7=j@__OBJSTORE__/ISimPlugin/SignalOrdering1/wb_lpc_host_isim_beh.exe     
12 17 hharte

PK
13 14 hharte
||G__OBJSTORE__/ISimPlugin/SignalOrdering1/wb_lpc_host_isim_beh.exe_StrTbl/wb_lpc_host/clk_i/wb_lpc_host/nrst_i/wb_lpc_host/wbs_adr_i/wb_lpc_host/wbs_dat_o/wb_lpc_host/wbs_dat_i/wb_lpc_host/wbs_sel_i/wb_lpc_host/wbs_tga_i/wb_lpc_host/wbs_we_i/wb_lpc_host/wbs_stb_i/wb_lpc_host/wbs_cyc_i/wb_lpc_host/lad_i/wb_lpc_host/dma_chan_i/wb_lpc_host/dma_tc_i/wb_lpc_host/byte_cnt/wb_lpc_host/nibble_cnt/wb_lpc_host/wbs_acc/wb_lpc_host/wbs_wr/wb_lpc_host/mem_xfr/wb_lpc_host/dma_xfr/wb_lpc_host/fw_xfr/wb_lpc_host/state/wb_lpc_host/adr_cnt/wb_lpc_host/dat_cnt/wb_lpc_host/xfr_len/wb_lpc_host/lpc_dat_ib_lpc_host/adr_cnt/wb_lpc_host/dat_cnt/wb_lpc_host/xfr_len/wb_lpc_host/lpc_dat_iPK
14
G[GGH__OBJSTORE__/ISimPlugin/SignalOrdering1/wb_lpc_master_bench_isim_beh.exe1     
15 17 hharte

 !"#$%&'()*+,-./01PK
16
`*EEO__OBJSTORE__/ISimPlugin/SignalOrdering1/wb_lpc_master_bench_isim_beh.exe_StrTbl2/wb_lpc_master_bench/lad_i/wb_lpc_master_bench/wbs_dat_o/wb_lpc_master_bench/wbs_ack_o/wb_lpc_master_bench/wbs_err_o/wb_lpc_master_bench/lframe_o/wb_lpc_master_bench/lad_o/wb_lpc_master_bench/lad_oe/wb_lpc_master_bench/lad_bus/wb_lpc_master_bench/wbm_dat_i/wb_lpc_master_bench/wbm_ack_i/wb_lpc_master_bench/wbm_err_i/wb_lpc_master_bench/wbm_adr_o/wb_lpc_master_bench/wbm_dat_o/wb_lpc_master_bench/wbm_sel_o/wb_lpc_master_bench/wbm_tga_o/wb_lpc_master_bench/wbm_we_o/wb_lpc_master_bench/wbm_stb_o/wb_lpc_master_bench/wbm_cyc_o/wb_lpc_master_bench/dma_chan_o/wb_lpc_master_bench/dma_tc_o/wb_lpc_master_bench/slave_lad_i/wb_lpc_master_bench/slave_lad_o/wb_lpc_master_bench/ldrq_o/wb_lpc_master_bench/master_dma_chan_o/wb_lpc_master_bench/master_dma_req_o/wb_lpc_master_bench/datareg0/wb_lpc_master_bench/datareg1/wb_lpc_master_bench/slave_lad_oe/wb_lpc_master_bench/UUT_Periph/byte_cnt/wb_lpc_master_bench/regfile/ws_i/wb_lpc_master_bench/clk_i/wb_lpc_master_bench/nrst_i/wb_lpc_master_bench/wbs_adr_i/wb_lpc_master_bench/wbs_dat_i/wb_lpc_master_bench/wbs_sel_i/wb_lpc_master_bench/wbs_tga_i/wb_lpc_master_bench/wbs_we_i/wb_lpc_master_bench/wbs_stb_i/wb_lpc_master_bench/wbs_cyc_i/wb_lpc_master_bench/dma_chan_i/wb_lpc_master_bench/dma_tc_i/wb_lpc_master_bench/dma_req_i/wb_lpc_master_bench/UUT_Periph/state/wb_lpc_master_bench/UUT_Periph/lpc_dat_i/wb_lpc_master_bench/UUT_Periph/dma_xfr/wb_lpc_master_bench/UUT_Periph/xfr_len/wb_lpc_master_bench/UUT_Periph/lpc_adr_reg/wb_lpc_master_bench/UUT_Periph/lpc_write/wb_lpc_master_bench/regfile/waitstatePK
17 3 hharte
6R?__OBJSTORE__/ISimPlugin/SignalOrdering1/wb_regfile_isim_beh.exe      
18 17 hharte

PK
19
F__OBJSTORE__/ISimPlugin/SignalOrdering1/wb_regfile_isim_beh.exe_StrTbl/wb_regfile/clk_i/wb_regfile/nrst_i/wb_regfile/wb_adr_i/wb_regfile/wb_dat_i/wb_regfile/wb_sel_i/wb_regfile/wb_we_i/wb_regfile/wb_stb_i/wb_regfile/wb_cyc_i/wb_regfile/wb_err_o/wb_regfile/ws_i/wb_regfile/datareg0/wb_regfile/datareg1/wb_regfile/wb_acc/wb_regfile/wb_wr/wb_regfile/waitstate/wb_regfile/datareg0_0/wb_regfile/datareg0_1/wb_regfile/datareg0_2/wb_regfile/datareg0_3/wb_regfile/datareg1_0/wb_regfile/datareg1_1/wb_regfile/datareg1_2/wb_regfile/datareg1_3regfile/datareg1_2/wb_regfile/datareg1_3PK
20
__OBJSTORE__/PnAutoRun/PK
21
__OBJSTORE__/PnAutoRun/Scripts/PK
22
>*__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tclPK
23
髭1__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTblnamespace eval xilinx {
24 3 hharte
namespace eval Dpm {
25
proc GetIseVersion {} {
26
   set fsetName "fileset.txt"
27
   set fsetPath ""
28
   # Find the file in the Xilinx environment.
29
   # First, construct the environment path.
30
   set sep ":"; # Default to UNIX style seperator.
31
   if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
32
      set sep ";"; # Platform is a Windows variant, so use semi-colon.
33
   }
34
   set xilinxPath $::env(XILINX)
35
   if [info exists ::env(MYXILINX)] then {
36
      set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
37
   }
38
   # Now look in each path of the path until we find a match.
39
   foreach xilElem [split $xilinxPath $sep] {
40
      set checkPath ${xilElem}/$fsetName
41
      set checkPath [ string map { \\ / } $checkPath ]
42
      if { [file exists $checkPath] } {
43
         set fsetPath $checkPath
44
         break
45
      }
46
   }
47
   if { [string equal $fsetPath ""] } {
48
      puts "ERROR: Can not determine the ISE software version."
49
 
50
   }
51
   if { [catch { open $fsetPath r } fset] } {
52
      puts "ERROR: Could not open $fsetPath: $fset"
53
      return ""
54
   }
55
 
56
   set sVersion ""
57
   while { ![eof $fset] } {
58
      set line [gets $fset]
59
      regexp {version=(.*)} $line match sVersion
60
         # The above doesn't stop looking in the file. This assumes that if
61
         # there are multiple version entries, the last one is the one we want.
62
   }
63
   close $fset
64
   return $sVersion
65
}
66
proc CheckForIron {project_name} {
67
68
 
69
   set version [GetIseVersion]
70
   set dotLocation [string first "." $version]
71
   set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
72
   if {$versionBase < 9} {
73
74
      # The project file is newer than Iron, so take action to prevent the
75
      # file from being corrupted.
76
      # Make the file read-only.
77
      if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
78
         # The above will return 0 for a match to "windows" or "windows64".
79
         # This is the non-zero part of the if, for lin and sol.
80
         # Change the permissions to turn off writability.
81
         file attributes $project_name -permissions a-w
82
      } else {
83
         # On Windows, set file to read-only.
84
         file attributes $project_name -readonly 1
85
      }
86
87
      # And tell the user about it.
88
      set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
89
      # In the console window
90
      puts $messageText
91
      # And with a GUI message box if possible.
92
      ::xilinx::Dpm::TOE::loadGuiLibraries
93
      set iInterface 0
94
      set messageDisplay 0
95
      if {[catch {
96
         set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
97
 
98
         if {$messageDisplay != 0} {
99
            # Managed to get a component to display a dialog, so use it
100
            set messageTitle "Incompatible Project Version (Newer)"
101
            set messageType 2
102
               # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
103
 
104
               # in milliseconds, 5 minutes
105
            set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
106
         }
107
      } catchResult]} {
108
         # There was an error, probably because we aren't in a GUI enviroment.
109
      } else {
110
         # All is well.
111
      }
112
      set messageDisplay 0
113
      set iInterface 0
114
   }
115
116
   return 1
117
}
118
}
119
}
120
::xilinx::Dpm::CheckForIronPK
121
__OBJSTORE__/ProjectNavigator/PK
122
/__OBJSTORE__/ProjectNavigator/dpm_project_main/PK
123
ׂP6__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMapPK
124
9
125
126
=__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap_StrTblPK
127 14 hharte
tNN?__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_mainG,PK
128
K=))F__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTblwb_lpc_simspartan3espartan3PK
129
||5__OBJSTORE__/ProjectNavigator/__stored_object_table__(2z]^0_z^q`pO]sa^b,$Vc@FQ3R7b/Pdhe"_:^^sJ<f]taf
fG_g^s]a9M}_[gggMa       1]y`q}c"IhNah  y8iMjHk/8NAl\ugc-1\a{+`K]^8_4m[4^{
130
`axbP4Que."\ma.4nX_<_7b4?ih
131
<'`f/o0
132
Dio^u[n1aa]*`aaOaXgn"_dg^{gMG^`ga_}mYj,mg:C`Md]`_h]a!h
/]]     g^hd1a}xbc-]vf~h^zaadb*9m[omW?a1i`Sa   ^k-ae3]^e^8`>[j"e,   j`dkjW`9.bfah
vHagK)iZg)mKRho4s^D=az`Ehdi]sU^ia}ay^sd ab!:^^`m`6mGNK;>b;-Xl]O]9>I=^ngq_jc_hJh#_Uj3u]Ha~"]aUiF%fh
133 17 hharte
9c^]t,am6_A^__{Ka:`hQ=J1V^c/ba'mL&f3dNf4tioaR]C`i#j_Wa}8^s([aGcJfC_ah 2]s{gega6_Mcgu^svbp%aKxgp#]L_h`E!b-V]^s^Uqe)F@_i+i^uE]|K_zh]^_f:]g]aaOaC*ar5u6cun "mm=bf[]tZ``_'h
argm56C_Ahk/U#5P^u]sad"mJ:huq+sh
r'^b&_km<$]Lb{h\gJbS`l}b1:i_gjm<aAEad)hh	b"*c`Zqc_DmV>]:`LY~a~c!o3gmpmT0>m9(mL*&^cTf9h
134
3]na`a[^j0^sffi%^c#yacSHi0lhk]"`D`Hp`pfrO^qgmDh>b3b,aWq3^]`nj)og+h`I_WzmU^h^m>fMa}?jBd(#^uh`^U_^uWd`o`5n.]_p%<H
.`gi^uA^\jYsht
135
q0u_r+o^^s.a])^sRqzim?ihgCa:]8^uM]>]*^uOi"amgvg`Y/a}BC_]rf3]@WaQla^^$^smX^gN5yj pndOaq2fpg^h']dgk^Oe`:+`X;K`^^h        d6f{h
136
og]L;    p&'.]Dp(pn3bg5fv]l^_*Z9^^q(_fo.hf|s^s^Da7m_Wi^tXe`R^hb;o)Y]kc+JB_{<Y`PGech	8mh"q-~i	q"hig9aYI>`CU^uGlm;B^aaM9Gmc}g_#mPo,XP]{v`;q]K^}b1';fgO_Hjb0a~xh   hgCg]gIa~_&ygj+p']2e^l^fFN_^4a;%_SmIvh        `WM^]=aWc,q`:b_^zM_Tq`=^uIJfh
LLf|gd.ang9?GY_EAih      mHJa^m^h_f|p(.lRamS2]<bkQnhVagaip&~gUlp#a}>aj.q[bfz{e5KfE^CBwmqN^uU]~m]$mOP
^]d)]^Vq|h
137
g_{ mRpb2Y^f;agh
138
Y^H?{_AmZr$`#Cn(hf_)Riah
0j(_hrf6b4o-fmF^tVsc8[^ak
^~F^^sgArfgW?m8^sd,h GG=`7}`r?g3f|`]EXa&`fh	p$^a`Qh&f`4fb `bh	g`cac'_$me^uKarXc!r0qA`8]_6^tTa$&^ Dg/`<]`Qlo5`^-m=aaXeao2:af`Ab/;aah
l~^c-c/D^io#-`?-b+g^]^7^`[c1]aofc/i ^/aQ_4        `bkay0V]]J^q]?I^_a~]mfonc*yjr2hC%mNzga1_/p$kg%}a}b!b)]f_^2_4a}Xa       ^yr-f|QmlJ5fJfz'mm:~]c*|_]hm@e`diib
])c45_fP.Yuht`Tag-akAe mWh]h
'c/t9f7a]^s a/iN_
q`\'htgQqSclpb$c%vgw]c!;_7Obv^8`A!mQ^^]Zac   aQp&i?`M#am``U_6a`H{^4^h^sao+S^s2_|Yb`Fgl__
139
lafa~8^&mMo*mC^kDB+e _C6O^__,WgmA|d=`B`Ji|giucwbj_&h1}n=o/o_o+n,]r(a]ajg/b.^san)ufIa!J^:G`jk]lCae1]`n3hc2c0L[_2Rh
o1lGa'afg^]<^^_!]wmeac4^{o1[a2"mPb*`G},c]mgf#J_|Rh-^i!n^eo,
140
aa\da0_,]ag^6_yc24|`Ui9fhIff ^ab]az`<5^uCHaM^uQ]`Vm2]d3h
141
 
142
^     ^]5i1aGT`OgWEaa!LfUH^^sgf^_]Eczg;cc1a`XR_?Pq ^uS^fbNamdR_bnazn^ZbLo'5h_Uapi?o%*;aG^
ur`7sa<^A^mrh
143
va^sa:Ln`?_/ah
144
]_^s2l}fG`Nm]vu]s`TffmBdh
145
nmpg7^sFa].g^sEmj<^wmbMlve`o
g%p$a~XhJ_p'gc[a`@?c5PaZE^gwݼn@׼%QAٲriT[>6J7Q*hk   J8~/-Bh\c5;E=okϾ_ʀG^p+LXz%.pn;FϯoؤH~Z-gE#xC˺-IˠXBk;DȾ.+g
9%HD'KYAqgpH
F/yEIE$XR(zN|OmԮ6wKL;#tPi~GzTp{n
146
NAtQU0M+2UIwژzIĪa.-Tt('GlerA*v@t@[FG4'ܾBۘV[x,c
147
OG`ys@:GVϩẄ3Bl;`ׂ]B =dr=03D9{nYwJp/@ߝ!CK0rxAÐOxkL`M zcuאFCq2uG[ϟ8x*Gkd{O8fS|'*_Aftn/#RLr 2%%Kd U\dH˃%
]%@1aG֦#.?Rb#^ćD뉳T1n.O+GGГXLeTxug'6Lr_kNLyM!dB)M    h@Ӂ        M[z!
148
RlJM&Z1:bJ
149
 d3VC1nYsXSMOff.Ħv%EB9Y&L[PAe./j~%1HMY[m;CKH[H=^IrHZ')_FMOn)놖2OJhvce_°hv|@::-_wG鳞Q8.Lw%B)N5\C齔[TJq*QJ      xt.EbqD<%%|J8eqfH@]4q%AÖj\bvUH_۸h[s3|rD  iu:WEA/k{?=a˨H)yDu\zWK) Zk57L2Af{x1J*(6o,o82K24f    yZK      π`SwG-q='̝M 4/Y7;N}F!^HזE*v,A9qbEs4H6ɰ;ޫ(5C =hbP,GVId!y3EQ    t#D@yrDw6ӐjC\w6!Oj.Kvc}G̸ZHo5+x^O=DV@Ah23ODT]PNI
150
p2SrB2e;wL
151
B̧U$"0HBAcE>o1H5+G^E/j'FjzE3ǕSfVHhcg@w>dRi{vNl4iFM~@FH3:E/7vIVCpƬ}(iGa]1F
152
5BG,
153
O%3!^PDDb@g֗_o6e}ΨOӗֶ@PuGfZ?E_}eN&,;x59KICӫţ)KWI@C(r ܗ@5c
@g'v!7qwGbΟυEAFąM.Cֿ*7S6hAd|2jU*N?h[M>:^?Aj6IHBfuvOl[Nv]\sW̏K0/(#pPC4ΨV8VOl(tu"AYnVvmDUfCJvl}%M    BH=^]9Dؾ*90_AlO~,>JuWƭ\GyFgBBZ_0$  M7,~8Z#"%N]VG/ƒGt,9s&wAkiޓunB
3J5"vHEz>-;uMOgEɩ!/{JKlƊ9@9s^r-ݧ2}Hіkd
154
lD@*ʊEyU.?pI˝״<	׮|B^3'hɒ\ΰ-H2`EFU
FJo
pK>t8CަDjD\H]VJY~/I;nQL    a(eV,~Hu0K:Ia"hHޏ|^AɃFx>@W1*4s3AM/ۺ{|NF:9)C!?1xRLc_%2GHT|S͝ٵKRR~JȎhE8HOH6HGe8#AxOk7n
155
:J)NujAnN@FMAIx%8j%$D@rc!C׺+G:IY
156
uzKQ9 >'0G{'!HMHꚷxwK(}?(AAغyHňFeLxJ졏4oBkvumGkA0aɹL,ېTl#YeHVHr^u_6EթG.9. J!
@
dza*xVLGG^uu`   JX9kt>b~G\|ӈȜ@ft%0ޟB
157
|RADNVf7Om@oF#5lCѢ*Mg%gJCͯIj].JI1$j
oF)D5M
158

V    8-֐HbQ?s>ROQTE>Lդ^ʭN寁#2ZgEm[KDϿ`~w3FjIq.LJM-ѳsLBh~iP@eNƘ#zFl#CK4
m%<@~/Lp~     JI@#.D:Lz5'rL@AB!tUG KCa:sW;'@~LsZϔ4A#7,AFqĻbJnBk
159
;%l=J`=*?MpFr:oǧQF $ݵ2T@azLv#x+vmGtUE(3T@wz6%oݞ@Cvva7PK@!CYUM@A:1*DO>POQUBݺױihB6M4^f=]Z_`6K]Lշ[!w|E@dG.
160
8@>ɩMօ:I?[B3f?JX
妀$?dA}\Af]A"vE~>vH͘B%2mL
?[   LD=*tP3VNIÃt2y`s"GZxxqx~=~KTG84KJ֣
A}HKliXjC4:Ia_&6Jr>Z'?JƷ%vSӾEZٍZDSGQN V+y@-wWABXXװoB{HĢc4GEm\$D
L<=L#:|mnEؙ3o%PX.@TPME0cd=EBwgI‬K@#ˈ[0GQJuRAU:`gOD:]^sMG%1u1kŅF5w~M)!h2,Mݯ
161
 uB(ڝ3zEhLBε?pkzUG8i&YɷMﱈ.2Hy}?="7Ñ{2/~ۇ&I%^~qی[3K|{h;Ej&4Aml@O	Y48LDCX&5+GOEs`̇@3?7OI͢CFGOa'[v3~ yJܧ7~d0    9Guz>z
A_?F7O*i5JG'tb=hGO7cyU"5IHɥ@   iUŸNxE  +ӓ!F9;҈rFK^)MZiD_%7+J= G2>eLbQt8%^,RE¬PchVzNET
162
*\EPDBZ*wDG@8V',IԮxcC@
B˶@۵bR! CdEFϩIMV+2:_0I܍`,PV}{;_K͗Bs!uOVc3EE?HM8ECz@ŹЌ)E&ҊGF!	}زI`kG0C&Bv1
Gcek1X|%Cܱź3O{е
163
c}=C}Y!.2nL~xdM}eHUcW'1=*AX7lǩfEQlUyp/HȐro =+GC;MJyoG>'T1J'M)3DYH*cIkCՂMǁA]}߭g'
164
Nک}zHI:T3?Olk2>BUC(A@Z5taK/ގNnA
Bs%~7.;+G؋+˓wڿI%[aydE[oOlOUFҭSA݋kF5#%襯RGgӮKRBY%#XvMڷ0c.-gPCM ٰWK@/(b9Ju276KNږii߶IN_JD|-Ș'JATfHyC̤ԝRPcJЪM`X%Vh1.OT"\uyEo~*C5Od$z.l4
165
Dl~8x
166
N>Ԝ޿˙Hꙓ0DfoeіnJyԖeG@P@ɧe D/TngBMZSLWkÜ(7$M&ꬽAS9K.y$u/w(ja        G[uz~C[IjtI:@es6LMa-&Ijiy׋Asz
167
\UOşV9*O/bT8FϒSZsp͖ E<^{dbbLԯahʷ
168 14 hharte
ЄLRۦ>9|iBuЋAM       AG/\}~@3:snX
169
mIY5?
NI_ZxgFIH@rl28LΟ7MbnZBՠ76:DԹD"ZF,EȍZo+!$T/0EOF"b[ϳ+]
@Oxr\wtFȯOaWVDNxŧE@r~+َ،OʟmNQZ.sӎEhxfVbR͐f7Ml|~RHo*DF4WHMb|9ޟd    H
iGjNiDmOs$1٢l4f^lNcʋaxrIp_~/Ghe,=[O=Moc(SحSN@məC$vOFŘD[/yX7Aʺ8PAM6qHG5;!TMTg7(!AJ}Mpo:
170
F
w|0MQӃ,S FWgfցO]
171
xrHl#6SD;NW,˩       `LqFE$a^OFn(2o(0~67C5sQ$F*MߍԉJ.z-
LOn)bNJHkv^v&H5ɓ*b,pfOCL5W\PB ̡M>ˠisC|S]evʉJ]xqNTTMT|ΎX)F2X)$&IE?\aF\:G7=1a|X)IIJ"AF`eN})N*}\KZVzSMBXe]oôbK-@Xڽs^E#{s@!>?K.G.$Q}Dbk'9	Kɕ8Mt<~Mʇ-u׿zy@c^`$R^(<:?Jpw %JܙHߋ|VBqR![N2I)^AO5OZ	J;0 h>wәhB]OzX*<
Hjt~)cE"6pD惇Bbҡ+52&D-_0D>Dg}ѐn{JnA7u/2K|AC'.rNMU@Z3v>=Q֓YfL4*K~GEt'},fKIrn1rBN >^bMP=D#%gBDO$LA2?PlOqDLjg(@8t9zvp̲FAhܲ_`}E  wWɆx'/J~|ᱏj#m@=emḢD}€9SAC![r-
172
PMGgHeإJ|QƼk
bMo@'B;{u_.hNd
oʘPjC"FÉB,>zDP\vKHcEE'fC^O G0GDT{=LկDbElu8dnnv_T!LSk.{V'Cն`=%^Jm3E蟎R-'Mt      FWDKR|BK0B˺gZ8Lc"BބNQSݸeE
173
DY{Oru[EsSVu+fF~t+HjԸJzrr*۔Q"Dm    JK|A{wcM/KDYG\VGW' mGN∂#m
6L@IΓ*em2@D$U\Eb(TjEC:͸
174 17 hharte
DN11~3̗|@N~@A@V@AT;wKLgMGL0)Įq÷@6JezvA%SAiW#_^
D?^x&Mwul3
175
x3OȹT$_U} Eկq6%nDYzh
176
g~Nz,]dpkG=xM3GMgDl?~GDߠ&D2͵g0rqJJOHrGXp78IjID7AY+'J̎n
ZLfp[8z?E{EkC%8U..A8%'Gs\|OP0ݡL!l*PE'I%rӤFut.9@d볰K4gLrNlٮK= üPmJ8e}8teH◀Ck]gcl6K;?KŅDGD650=sBo(͏le]VIO*D3xB**#ijyۚI+FgepGDlAvUƮKSOGL3F+8tdZI@᧋   {[SIjUX&q <{deEҲXͺ҈GG,v-h_nLY7GDqV>z,"\E9G<+GMa
177 14 hharte
/`jD|JT
6@"_yiEar.G>GD="b1hNai8.2LC5"aJX_|BQ[
178 17 hharte
Ǘ06oECE%j?nIgs@MIŬ%G`n4A
179
1bF(E!]'DGd*ĢafOdS뮆@ӎΡ2OhqEĂ\?kBݍ#:{OK`NeC!q
180
 tՋNڟWb2CqD@lH\VwAHED&犷C&@cpϸi)m{D̟>eTQFEvѼ?י1$J1rT^?4$F     կ86h8mD--^NL$z_&[$
181
A
182
{ к   Kt9MQ'[.LA(LcM@H{IIU;g&iMH|xcS:I$5"ͦ]D˴&Ӎq[=BTyv\ze3bNtze#hCAOn;SWJxBgD@ʝ1F v)P@^#:G'agș_*BF {P܌)NcJխ#_BoB2A{Ezi2ks^B&znA/@&~(21Du1.iSI8x;ɖC$JG\=v~V$Elj~aUA䥾@wXV@>H"RRGaGN/-EyXJf7S/;K(ޓq˥Jg^zL`BPICQ!9@QT!nBVLOے=TECǩ?P[tWmJ[3 fMʶ߷$1]}@~іp^=LǶܯ%IMZC<2&ZJ   %F\ӻL9X*eI芯edC
U5uCף<J~h$uOs_XI!y_ZJnAσ
(Oi pܨJԇ^%#xPR
183
dD&l#bACAl$n4'{N8!J@ؘ$etdTQVc+I+MQLo.Eʯr0
184
:JD{u9q0T0G0B*CcnLlmv-Ouarn=GzkB^O+CիpBYnCмwuBL26Fr@&I&zOȼ\D9pGd#
@J>C[+yO<0dr9Sّ'DE9      D#{଻l.C}G_m0Jyx6usD2(Ͽr5IfK^zӑD4FT7?mKH!K
185
ZSfqߠIŦA۷ХRE-eF:QGMg2w4B7$|OHն[G[^}|Lr.kN"Y;ʇdEFx5Ý:iNǵ0h}ϡH&*0       c|I:wpKlDJ@J!GEގzƊQCk47BVrv
186
}LC,X#LΡ     
"uGmoJ0XW8[mWB #՜A/.BڜVy@٦x
187
-5)uPE)VIۼ{!    LDDŚz     󔯠 O}  29!֦eN?Fݣ5\?tͧ@?"_C        H}@K=̗E`h`+nȵ,@_
6XJqNg^\[L^dcEc˖2o0sB7[87N:qhC+
PJgwG-np_Cs

)6B|g]ʌH΀r҆_˱K^CxHTv;v#i"Dhcf"0TvK3[5.nM@FlSD?A
188
lY"\Ao{:fq@J:YN@
189
oVB27詡?;$RA݃
x`C7C*(|FNى
.^G)'.RK5ϔEn]GN/Уw;#I}6"SWC?wn:Y:%D"wF ׸H"G#?LE}/u:mc(N,@
190 14 hharte
cZ*rD=RX*:kHs[gDƁ=B&|,w(GuΠsc'1d|.cB)AAdz^BqMU뿦O~LP'XXgʠK\TJT+Kf@vMϵK>]&JMo;'x.OȔd "b㕰fHd=9e>KEC0"%~KRQj.~ILES4#B>oSmTG6X!
jTۤ!O8sw<:Cʨ1#SU$_eIJ~ގA*QZ~\@xR%EރGHDJ_jHir,tNmK8_T:brI+
191 17 hharte
f<CG8@Q'5u'L櫧[6K:.F"搩v̯@JQ`рR9UxE?\$3l@FA#զٍKxiAXϟ^/EJC=sUȟmD	=JruJ~dE𻨼*lXvCןYBOFa!|DN'@UjOB"[f:P@B$%_4-!L I8y'	!HNߺC+\&'/}hBPLb)ɇDB-y֧pDg]/)Z	1Mkqo!^2㋯^DU>V忱ͭO$gfEcIٕQNemx;ON
xtxN5hҌ~KN6 X#!C܀ͱ      ;Bw
hdH1JհL~tIL~1Gxi;MnP~Cb-N@H:䐏JQ\AOV1bDBÿB5hJ0GlOgӂMߌzbR`nBzE
AhP?C{xL6{af 5ӅTIJz7B\K"ɂ,r,N7Z?KΪҟNrMܞาO#31
192
!BKr'j$EJk:d`wz9wFǬ6C<`68k>IgY0%bMeKedFr|]FT:^⡣C}HqVZĺl:O]ԝfBi9Or391nNk,j
`j>%L?y+I{Dj#[14Y85GmCEޙHBа8}MI졟R_L6QEѶz4\L3nG$&~I>%&HG-(p;Oܹ,8{\BPVs|tZEW]_ܮdE      I&BGҩ6bYӅ.C[I]yJ	P}TlSo%ChCBɇ;>$Nh:Ej-Tq%M5r>F^3}gE_IGLJVLØ4e fe*#OF=vULlz!_^M$7ǯ'XooF>}GHsmM߿dGMy潐
@m".kQd*E
193
Ai
>IEOΟ_aE66UGuGSA5H9RSțMJS6  U6`H=e4$׫0O@Ȫ"LJ𒆿.<%HY
194 14 hharte
=_NmkN_{tK.7J6@,->6X9I39,"r-4qC/|bzF_CMbu9]LDiu֏ F9u0COh)l)!4"LPzFɽ=$B3yŢ@jQW^p%!RF5㕢z%jB?/:ie
195 17 hharte
@`1%OHWr}@x鋾-h^L[ߵ$B{VLNHeuy7+$HDT4@m3DN!I,J'mfaD:߆NjCTIAT^>1IadETDUD4Cި/BW8)HŒMj`kZf"5qFФFRuD%B`&s
196
LpЕ֗J楈h0-hP=9IJ%g<@A,?J4hBՅL&n%5CO{q=KJ}6 k\hE)ZDca&k.]Mty4j4BW"s(wMبHE7-b UqAoY/|,Cہ~ )FB	|@Lfn@J(jLTs(3AC
>022F~MY
Mn!r+DCv[JD5Et φݓ--BFV+W@pqJm1~;g٦I3sk'hj
197
VFۄj%
^iOS68te
$ J 6/wDU༣,~_KH7w7tX.pFɒ=_CgK)sOM[^B#Ĩ)j2kLٿ"4}-bJK{6#KďYB4ZA"DJBdYQF|;N%!V6_)G6   
198
E9^7h$$z@iwi1EHɘ;`5)HKV
199
IԔ?:N+ΖAr6w͎Oi_*(`MHUtFtmN`nz3u*SӷPDjRY:^G      $gzLq|H}K%0$VFܨ
200
[5fWEkSc G8H(2:(nDz^t-߫TSEǼP^=4aI
201
>CA
EθKU(YLi+zID,T
x6W0KP
202
IRp
.](Ir@
203
50`a/DO5d;:/
Hwj   dL    G9:$;3$L
204
Dk@Ww!KCq4*ϟ     (9C:2-εUD`äs@W-h02J>ֺ.~v+w    ݰDb}U0[Q7(H3lqe+K^_y,SC  ޕC&F?4JM=z,L›7U~LH	=wn]pp!O􉶣-]=
i
OⶈIJZZE)9JҠX;%:I*l㦸5A)BY.P@l%ɾZ,VES#BX?
205
%|83O:CByʼDXF]i[erKI(
206
B"GNiQ-AMaJ%ۂN۳~Z6uyBpiT8TL4!?M\a~O:ljWKyW'Aօ\i.Yג}qGN\_[:M/t'GَUilh#lAvfMXi9E3ˤ1G%?LxC[3}+rM5dj_8 IY\G׼^MPmZzN<.&$zlaG9n*nKT,NOϤ`:3OG`&O6IY C2L/-@q\B<\"K8H
207
^⫆Pq@5LO*N.g,
208
eH@EXOtadvB{o^GB      HΦf뻼B9bEFQ(ꋆj[LBM^Zl?Ce-F{Q@)BďcHUY-Fi-\8|+gEV@b4BAk9ݷ0
֨ME0?rMO+-KA|g JK-.njO%wn#={H-
209
UYu
210
S-B}θr=+č۽IeNU8aLs͂)QrRD_flcYk9O!B$wBܓFm|JBȡ/oD+!Q=~E{N>͌0%Ld6tr,B';Π|ՈMbJRvKM!Y|:CՅsu\FkVqXfA(BhIOA_^i# K/N'nFG
/2J}odK9KMcrR}Nm\!FHVyBŨc+M֔{?d;OgPN
,W'+pD7mlW(Bnvp=Mtt%rIߋs^C0;g#ފDOW8G7p5@4,S|7BG0{܉QORfILJ_-MЂaUl3[T/UFYt!qMiIЫŦjw^5TJ
211
qs{ʕI鏱gq[@tMԊ;U!36\6M'JODKR~mf.EfElJg(M֦:"%G?@Y-LmiIg1UUQPܩm7NF.~+{A,K#VO)̯wxaSfD
212 14 hharte
`4H6KޡYd"N@rKD%>8Hɑ/06
213
GP{:6@H8R'bSj[HT{l;v:QjL;]@j0A')f$A߾Zs똴N6yP70NBÍhG5x&$PvC9|;>IEN2|8quaS1Lڣnr>R
214
)GLFbTK\ҫ+1vO͸j5c5UVcMyJOLl{@P@gԠrqqH%bd]OvV)e|N8D;6TNYMUf9gОtQJ6]w{v
215
nߚFo!RwH%c
216
») DAHΔ8Ր=#M~       snzxM孶+
217
)Bg9MH衃FyPIHЀyKoHNjT}>c `CGyd*ڼrF츧L v?RA93UEh5tIȊ?iRyTB3¯D<@Ң@v捋kDG=+CF`Q:K=s[]uDo0gϲGCŘi5 ?IGrK0yND=OՓ6CX:2%        AI?ݙFouEK2i!_誱HL
218
C&a K
219 17 hharte
a*vwZ&ACk
+dFa/:ߨqJAIKlkAq ^*F9A
e,kL=ʤqbAUUhSOK7Mm*IԪN=X
220
g=Kc-ڴ|IZG/3f/JCJF-T"C1*VM<@L@ҰanJݪF[Cts}ALıoiW~92@G@ Q^?L&E2ih5E6"%~_/DB%k&Hφk=Law`pLÜIr[YABSx~/R
LN)a-hhD܇v"ŔICMSL^BbwSv{J;P'!KO_L|-ovR;G&b:؄|DGj+MoA6.@NB74&-*ǧ8KqD ,X}KJώc[bWB 
Dߜ*B,B-,_M'5kd\RGΥXrXL_䟐~"nKK6j8)OMT]7XdDldFb_,-5'4CSR:tYQH.YUy5LĠyr{[,xIͷzQ_؟btuIY-C
 (NFLJB}$ťLq}W@FDLSt3@ލ
221 14 hharte
=Ws!K uuȡ^D\G7F&#&F#hIiVN}L/V,&r(WF"ӨE,2_OPfLG"DEl!hIQD'A/O4NyYЋĴ=KF1BX;F
222 17 hharte
Kb)#hن\*Nø[-ynK«|Ѽu{ئMeۿyYH
QFRCmGL
qx?e:bEv&hYaVqI\wcnPDqգr/ѲJ\Z9"WD=8fwu!@1N3mO>]F_    ar5\YB%9-@=lF\wi
)VAM67}wMA0![#KN]h8jK
223 14 hharte
ڎ$dܠ+z.|O:nHOm\KMו3pDZM##gdRQ5Jyg$ȯ-GxOSz
224
YuEH߻#ZpսB&F!nicY @8Oii-W5!AJR+O@B%v
W))0b5Nny}QB˿Lr_`8=ED]al#xSGl1 A(c
225
@ɮEW̆eO}E'4јG&T Dў5pe
226
YKQ7еmyeJ$޲WQJv{v׉`NT={"ԯ̄GnNIjGRNa9[zh̓B5       OI`POǠX6h8Aq֚D4{9Jx_O
HZoV1+2ZOy%=.˭A&ocujM=RuKGEu:?B|r<<ϊD5%]O'I&͜sKBl$
227
!ۚDIjΨ%>a5GCBHquuKzxv@/
1ۋw!MCB
xt1Z#ME?"ea/tъOĠgOqYo[Nt:aIKF[&"Z>SE(%m62ElWUu^+    O)''jm Y)OR+I=,mܕCCjˍGn9M>F(}̉\A #ʒMN)I+u  =E)A$E[kg9x\x1Gр5=ZwϫCçeNU+ҷ3v٥NU,\.J(NɚdGfC?앩 
h߭.@#,i*GDÌN״&sHiᢋnK}L-8aM5.MiNy*$cMco#Ys}Gra>k?$6NA2Y*MIQ5Lt`Y8lF)Uf}eF7GJW&K,("GZJ^<_T#Eۦ$,ɉH$A{
228 17 hharte
֏dF|A8w\F]!kG`sE#`,v/M>O߃ONHnIXtD_v^D֕ȓ*mE3-d'IOڳ,Hhu"H2s}DXc5lNLվ*0}T*d.I
?e*ȧ*JrýTjrLKێOe'M܃6[FQ@"$cy:o40%H,9A[hx|?1pBRCwe3HhP@7j8KA)Bv0XaO}IG12t#(HK
229 14 hharte
0N2)9A$ɶ/OLQ˟cM<PV'\KK<"(_o5HޅM9V@YJq5K!(P'xCJd'5;t,qA=fLl6/ƽOJE!)'Owl!dGKn(d]:8PhN݂hu,#MêLlOn"F(d׆yGp1W7c$q1DЖҚǺZ6NL*"Q|H-*ZHۚgs[OI3+2SHkIԭuг
230 17 hharte
E2MOsAx|Ҫ             KX
231 14 hharte
}z­MHյҔ痢c%+NLbj`b淊F@=wlMsOϡ؉@Td       즟RGs1_,
vC#PAdmۯMt:j^K5MYs)lO?.yı<7BMhF1{0wBȩnmX
232 17 hharte
qNPhn~.M&>F@N,K|}h[F}[ %>NЈnGFWKY`·QIeq5|ŸCj{"^txNcB
0 RIi eY,	M]$K/HKV-
$|#N::-uGёl@L2|J8~l}/&SAO/~rծ<%ApT=a~]GGM_(!cJ
233
eQOlj O
NYv}ZkF
234 14 hharte
1C%`m@l>02$~EU:l!?g=C:9*OLKT?2M*3l8w vFLA;!"!]PK
235 17 hharte
\xx0__OBJSTORE__/ProjectNavigator/__stored_objects__
236

A !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNO
237
 PQRSTUVWXYR!Q     
238
U$PS"V%T#W&BZ[\]^_`abc%d&e'f4g)h(i*jkl0m1n/o!p+q.r,s-t uv3w#x"y2z${
239
|   }~
X@A:86;975?=><'BBcLP'
n<0jhW=@gpil!R*:5qVa9;[$HD7]NBsF?-UTY  e
240
>_3JtYHUY   H[S    
241
H[S
242 14 hharte
     
243 17 hharte


HU8
 !"#     YYYYYYYYYY  YYYYYYYYYYYYYYY      Y    $$$H[I$YYYYYYYYYY      YYYYYYYYYYYYYY   Y    $$YYYYY        YYYYYYY%&'()%*&*'*(*)*YYY   $Y+H6isim.hdlsourcefiles&'',Wwb_lpc_sim.iseW !"#$%-H:*       h@.-&'..(/
244
W) !"#$%-)H:*       h@.-&*..(/
245
)W+ !"#$%-+H:*       h@.-&,..(/
246
+-./0H6isimwavedata.xwv&0&&11V234wb_lpc_sim.iseV5 !"#$%25H:*      h@/32&63374
247
5V8 !"#$%28H:*       J@.32&93374
248 14 hharte
8V: !"#$%2:H:*       J@-32&;3374
249
:<=>5H6isim.cmd&?%%@6UABCwb_lpc_sim.iseUD !"#$%7DH6@>87&E88F9
250 17 hharte
DUih !"#$%7H6@=87&G88F9
251
UHaf n !"#$%7HH6@<87&I88F9
252 14 hharte
HJKL:H6fuse.log&M$$N;TOPQwb_lpc_sim.iseTRo no !"#$%<RH6H@L=<&S==T>
253
RTUiBxl !"#$%<UH6H@K=<&V==T>
254 17 hharte
UTWsnit !"#$%<WH6H@J=<&X==T>
255
WYZ[?H^isim&\##]@S^_`wb_lpc_sim.iseSairav !"#$%AaH
@[BA&bBBcC
256
aSdliub !"#$%AdH
@ZBA&eBBcC
257 14 hharte
dSf        !"#$%AfH
@YBA&gBBcC
258 17 hharte
fhijDH6wb_lpc_master_bench_isim_beh.exe&k""lERmnowb_lpc_sim.iseRp !"#$%FpH6
259
@jGF&qGGrH
260
pRP  !"#$%FH6
261
@iGF&sGGrH
262
Rt !"#$%FtH6
263
@hGF&uGGrH
264
tvwxIH6xilinxsim.ini&y!!zJQ{|}wb_lpc_sim.iseQ~ !"#$%K~H6
265
@xLK&LLM
266
~Q !"#$%KH6
267
@wLK&LLM
268
QDT !"#$%KH6
269
@vLK&LLM
270
NH6wb_lpc_master_bench_beh.prj&  OPwb_lpc_sim.isePsIte !"#$%PH6
271 14 hharte
{@QP&QQR
272
P !"#$%PH6
273 17 hharte
{@QP&QQR
274
Pon l !"#$%PH6
275
{@QP&QQR
276
SH
tb_lpc_top.v(T        wb_lpc_sim.ise        fie !"#$%UVWXYZH
x [Z+[\
277
H[   h]Y"]^H[       h_U_`H[       haV
abH[       hcXcdH[       heWef       j el !"#$%UVWXYZH
x [Z+[\
278
+<GMH[     h]Y"]^H[       h_U_`H[       haV
abH[       hcXcdH[       heWef       E !"#$%UVWXYZH
x [Z+[\
279
>H[ h]Y"]^H[       h_U_`H[       haV
abH[       hcXcdH[       heWefgHC:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_regfile.v(Twb_lpc_sim.iselct. !"#$%hH
280
 
281
 
282
{ ^h'^\
283
oj e !"#$%hH
284
 
285
iH6vC:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_lpc_periph.v(Twb_lpc_sim.ise"=el !"#$%jH6: dj7d\
286
 !"#$%jH6: dj7d\
287
 
288 14 hharte
 
289
 
290 17 hharte
 
291
 
292
 
293
 
294
 
295
 
296
 
297

298
ppa    !"#$%nH[T bn+b\
299
 
300
oita !"#$%pH[۸ `p,`\
301
< !"#$%pH[۸ `p,`\
302
 
303
H!Аw
304
H!АxG        
305
 
306
H!А<yq=z	~>?H[@{MAH[$ BCDEFGHIJKLMNOPQRH!АS|qT}        ?UH]
x~VWH[XYZ[\]^_`aH!Аbqc     >
307
defghijklmnoH[pLqH[$ rH!Аsqt     mH[$ uKvH[$ H!Аwqx     lH[$ yJzH[{|}H!А~q kH[GH[CDEFHIJKLMNOPRH!Аq       jH]
x~GIH[
308
 
309
H!Аq     H[GHH[
310
H!Аq     H[FH[
311
 
312
H!Аq     iH[EH[H!Аq       hH[DH[H!Аq       gH[CH[H!Аq       fH[BH[H!Аq       eH[ H[oYH!Аq       dnoH[ AH[
313
H!Аq        fH[ @H[lH!Аq       vH[l ?H[lrH!Аq     yH[l <H[lCDEFHIJKLMNOPRH!Аq	nH]
x~<>H[l
314
 
315
H!Аq     mH[l<=H[l
316
H!Аq     lH[l !H[@oY    
317
 
318
HIJKLMNOPH!АQqR        i%H[1S!6TH[1UH!АVqW g$H[1X!5YH[pJKLPH!АZq[     h#H[p\!4]H[p;{|}H!А^q_       e"H[p`!3aH[pH!Аbqc       d!H[pd!2eH[pH!Аfqg       c H[ph!+iH[jCDEFHkIJKLMNOPlRH!Аmqn       opqH]~r+/stH[puv
319
H!Аw
320
 
321
 
322
      
323
H[@
324
H!А
325
 
326
 
327
H6$ 
H[۸H
328
{HtH[TH6:H
x
329
H6$  q!     "#$H[А%&'H6$ (
330
 
331

H6$ *q+     $,H[I-.H[I/012345H!А6q7 ,8H[I9 :H[I;<=>?H!А@!qA"  8H[IB#CH6bH[۸H
332
{HtH[TH6:H
x
333
H6b*qD$     |#EH[(F%GH6dUHI1JKLMNH[۸dH
UH6HH6
334
H6
335
H
336
{HtH[TH6
337
{H6:H
x&       H''K(M)I'L'1N)J)*
338
H6O+qP,     {EQH[(R-SH6)8
339
TUVWXY8H6yH6)H.H6
340
   & (U.W)YV'X)*
341
H:*   hZ/q[0   QH[(\1]^H6$ (
342
H6$ _2
343

H6$ `3qa4     "bH[Аc5deH[(f1ghijH!Аk6
344
H!Аl7qm8     bnH[(o9pqH[(rsH!Аt:
345
H!Аu;qv<	nwH[(x=yH[(H!Аz>q{?       jwH[(|@}H[А      ~
346
H!АAqB     kH[АCHU8 DHUDEEFH[SFGHIJKLMNOPQRSTUVWXYGZ[H\HUP\&&]HUP]*&E^_H[S_`abH[SbcdeH[Sefghijkglfmcndoa`;qUnoXO~RLFMkDKJNHIOElPu4&9%75#8;"$ X?sT;rVU=<W>1U[a])OHMLNKJIP.GQCYZ^\`_

347
   r12/360,4.-5}{;|-:0! 
348
,
'(+/*132N--5Y(,,j  !!jGG<<++vI//~0,,fH//}/,,M//4,,iL//3,,hJ//2,,gB6K  pH\8pqnqrH[@rsH\۸stuvH\۸vqnquwH[(wxH[xyH\8yzPz{H[zX{EEE^|H[(||H[||H[I||H[p||H[(|}H[(}}H[}}H[I}}H[p}}H[(}~H[(~~H[~~H[I~~H[p~~H[(~H[H[IH[pH[(H[(H[H[IH[pH[(H\qH[АEEE^H](H\@H]
x(H\H]
x(H\8PH\8PH\8PH[(H[H[АH[(H[IH[H[H[(H[@H[@H[H[H[H[H[H[H[H[dH[H[H[@H[@H[@H[@H[H[H\      qnuH\
349
=q      nuH[
350
 
351
H[!H["#$%  H[&H['H[(H[)dH[*H[+H[,H[-H[.dH[/H[0H[А1H\
352
=2H[
353
=3H\
354
 
355
H[@b
356 3 hharte
H[@c
H[@dH[@eH[@fH[@gH[@hH[@iH[@jH[@kH[@lH[@mH[@nH[@oH[@pH[@qH[@rH[@sH[@t H[@u v!H[w!"#$H[@x$%H[@y%&H[@z&d'H[;{'(H[@|()H[@})~*H[@*+H[@+,H[@,-H[-.H[./H[@/0H[@0112H[@2314H[@45H[@56H[@67H[@78H[@89H[@9:H[:;H[;<H[<ddd=H[=>H[>?@H[@AH[ABH[BCDH[DEH[EFH[FGH[%`GHH[HIH[IJH[JKH[KLMH[MNH[N33OH[O3PH[;PQHU
xQRHU
xRSHU
xSTH[
357 17 hharte
TUVH[
358
VWH[
359
WXYH[
360
YZH[
361
Z[\H[\]^H[zX^EP_H[zX_O`H[zX`aH\8azPzbH\
362
{bPcdH[$ dPeH[zXePfH[fgH[ghH[phiH[1ijH[pjklH[plkmH[1mknH[pnkoH[1o'OpH[1pqH[1qOrH[rstH[tuH[uvH[vwH[wxH[xyH[;yzz{|}~zH\      hH\  hH[1H[H[(H[(H[(#H[
363
H[
364
H[(H[
365
H[(H[(H[H[pH[pH[p#H[H[H[#H[I?H[IH[(XH[(H[pH[H[I.=.H[I?H[(.V.H[(XH[p..H[pH[..H[H[(H[(H[(sH[(      #H[I
366 14 hharte
?#H[(
X#H[p#H[#H[H[H[H[H[H[H[H[H[H[H[H[H[H[H[ H[!H["H[#H[$%&4H['H[(H\%`)qH\H*H\c+H\q,PH\30-PH\.PH[zX/PH[zX0kkH[zX1PH[zX2PH[zX3PH[zX4H[zX5PH[zX6PH[zX7H[zX8FH[zX9H[zX:PH[;DPH[zX<dPdH[zX=DH[zX>H[zX?PH[zX@DH[zXAH[zXBaCDEaa`H[АF^GHI^E^H[АJH[АK~H[АLH[АMH[АNH[АOHc
xPHcL(Q)HcL(RHcL(SHUTH[UH[VH[WH[XH\۸YqZnquH]
x[(      HS  h\  (PK
367 17 hharte
ŒizMzM7__OBJSTORE__/ProjectNavigator/__stored_objects___StrTbl
368
workverilogwb_lpc_sim****PROP_DevFamilyPMName=spartan3********PROP_Parse_Target=synthesis********PROP_Parse_Target=synthesis****PROP_Parse_TargetsynthesisPROP_DevFamilyPMNamespartan3PROP_DevFamilyAutomotive CoolRunner2Spartan3PROP_Dummydum1CoolRunner XPLA3 CPLDsXC9500XV CPLDsXC9500XL CPLDsXC9500 CPLDsCoolRunner2 CPLDsAutomotive 9500XLVirtexEVirtex2PVirtex2VirtexSpartan3ESpartan-3A DSPSpartan3A and Spartan3ANSpartan2ESpartan2QPro VirtexE MilitaryQPro Virtex Hi-RelQPro Virtex Rad-HardAutomotive Spartan3EAutomotive Spartan3Automotive Spartan2EPROP_xstVeriIncludeDir_GlobalPLUGIN_EdifPLUGIN_GeneralPLUGIN_NcdPLUGIN_VerilogPLUGIN_VhdllibHdl|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/isim.hdlsourcefiles|PLUGIN_General|1216952011|FILE_ISIM_MISC|Generic||isim.hdlsourcefilesisim.hdlsourcefilesDESUT_ISIM_MISC|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/isimwavedata.xwv|PLUGIN_General|1216952018|FILE_XWV|Generic||isimwavedata.xwvisimwavedata.xwvDESUT_XWV|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/isim.cmd|PLUGIN_General|1216952011|FILE_CMD|Generic||isim.cmdisim.cmdDESUT_CMD|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/fuse.log|PLUGIN_General|1216952010|FILE_LOG|Generic||fuse.logfuse.logDESUT_LOG|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/isim|PLUGIN_General|1216942686|FILE_DIRECTORY|Generic||isimisimDESUT_DIRECTORY|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/wb_lpc_master_bench_isim_beh.exe|PLUGIN_General|1216952010|FILE_ISIM_EXE|Generic||wb_lpc_master_bench_isim_beh.exewb_lpc_master_bench_isim_beh.exeDESUT_ISIM_EXE|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/xilinxsim.ini|PLUGIN_General|1216952006|FILE_INI|Generic||xilinxsim.inixilinxsim.iniDESUT_INI|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/wb_lpc_master_bench_beh.prj|PLUGIN_General|1216952006|FILE_XST_PROJECT|Generic||wb_lpc_master_bench_beh.prjwb_lpc_master_bench_beh.prjDESUT_XST_PROJECT|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/wb_lpc_sim/tb_lpc_top.v|PLUGIN_Verilog|1216941541|FILE_VERILOG|ComponentInstantiation||wb_lpc_master_bench|wb_lpc_master_bench|UUT_DREQ_Host|wb_dreq_host||ComponentInstantiation||wb_lpc_master_bench|wb_lpc_master_bench|UUT_DREQ_Periph|wb_dreq_periph||ComponentInstantiation||wb_lpc_master_bench|wb_lpc_master_bench|UUT_Host|wb_lpc_host||ComponentInstantiation||wb_lpc_master_bench|wb_lpc_master_bench|UUT_Periph|wb_lpc_periph||ComponentInstantiation||wb_lpc_master_bench|wb_lpc_master_bench|regfile|wb_regfile||Module||wb_lpc_master_benchwb_lpc_master_benchDESUT_VERILOGregfilewb_regfileUUT_DREQ_Hostwb_dreq_hostUUT_DREQ_Periphwb_dreq_periphUUT_Periphwb_lpc_periphUUT_Hostwb_lpc_host|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_regfile.v|PLUGIN_Verilog|1216942273||Module||wb_regfile|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_lpc_periph.v|PLUGIN_Verilog|1216951926||Module||wb_lpc_periph|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_lpc_host.v|PLUGIN_Verilog|1216836746||Module||wb_lpc_host|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_dreq_periph.v|PLUGIN_Verilog|1204699859||Module||wb_dreq_periph|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_dreq_host.v|PLUGIN_Verilog|1204699859||Module||wb_dreq_hostAutoGeneratedViewVIEW_AssignPackagePinsTBIND_XSTAssignPackagePinsTRAN_assignPackagePinsVIEW_XSTPreSynthesisTBINDEXT_XSTPreSynthesisToStructural_spartan3TRAN_SubProjectPreToStructuralProxyTRAN_compileBCD2TRANEXT_xstsynthesize_spartan3VIEW_StructuralTBIND_StructuralToPost-SynthesisAbstractSimulationTRAN_postSynthesisSimModelVIEW_Post-SynthesisAbstractSimulation/wb_lpc_master_benchTBINDEXT_StructuralToTranslation_FPGATRANEXT_ngdbuild_FPGAVIEW_TranslationTBIND_xlateFloorPlannerTRAN_xlateFloorPlannerVIEW_Post-TranslateFloorPlannerTBIND_xlateAssignPackagePinsTRAN_xlateAssignPackagePinsVIEW_Post-TranslateAssignPinsTBIND_TranslationToPost-TranslateFormalityNetlistTRAN_postXlateFormalityNetlistVIEW_Post-TranslateFormalityNetlistTBIND_TranslationToPost-TranslateAbstractSimulationTRAN_postXlateSimModelVIEW_Post-TranslateAbstractSimulationTBIND_Post-TranslateAbstractToTBWPreSimulationTRAN_createPostXlateTestBenchTRAN_copyPost-TranslateAbstractToPreSimulationVIEW_TBWPost-TranslatePreSimulationTBIND_Post-TranslateAbstractToPreSimulationVIEW_Post-TranslatePreSimulationTBIND_TranslateToSmartTRAN_CopySmartXplorerResultTRAN_SmartXplorerVIEW_SmartXplorerTBIND_NGCAssignPackagePinsTRAN_ngcAssignPackagePinsVIEW_ngcAssignPackagePinsTBIND_FloorplanDesignTRAN_floorplanDesignVIEW_Post-TranslateFloorplanDesignTBIND_CreateTimingConstraintsTRAN_createTimingConstraintsVIEW_Post-TranslateTimingConstraintsTBIND_CreateAreaConstraintsTRAN_createAreaConstraintsVIEW_Post-TranslateAreaConstraintsTBINDEXT_TranslationToMap_spartan3TRANEXT_map_spartan3VIEW_MapTBIND_preRouteTrceTRAN_preRouteTrceVIEW_Post-MapStaticTimingTBIND_mapFpgaEditorTRAN_mapFpgaEditorVIEW_Post-MapFpgaEditorTBIND_mapFloorPlannerTRAN_mapFloorPlannerVIEW_Post-MapFloorPlannerTBIND_MapToPost-MapAbstractSimulationTRAN_postMapSimModelVIEW_Post-MapAbstractSimulationTBIND_Post-MapAbstractToTBWPreSimulationTRAN_createPostMapTestBenchTRAN_copyPost-MapAbstractToPreSimulationVIEW_TBWPost-MapPreSimulationTBIND_Post-MapAbstractToPreSimulationVIEW_Post-MapPreSimulationTBINDEXT_MapToPar_spartan3TRANEXT_par_spartan3VIEW_ParTBIND_postRouteTrceTRAN_postRouteTrceVIEW_Post-ParStaticTimingTBIND_postParPrimetimeNetlistTRAN_postParPrimetimeNetlistVIEW_PrimetimeNetlistTBIND_parFpgaEditorTRAN_parFpgaEditorVIEW_Post-ParFpgaEditorTBIND_parFloorPlannerTRAN_parFloorPlannerVIEW_Post-ParFloorPlannerTBIND_genPowerDataTRAN_genPowerDataVIEW_FPGAGeneratePowerDataTBIND_createIBISModelTRAN_createIBISModelVIEW_IBISModelTBIND_XpowerTRAN_XPowerVIEW_FPGAAnalyzePowerTBIND_ParToPost-ParFormalityNetlistTRAN_postParFormalityNetlistVIEW_Post-ParFormalityNetlistTBIND_ParToPost-ParClockRegionTRAN_clkRegionRptVIEW_Post-ParClockRegionReportTBIND_ParToPost-ParAsyncDelayTRAN_asynDlyRptVIEW_Post-ParAsyncDelayReportTBIND_ParToPost-ParAbstractSimulationTRAN_postParSimModelVIEW_Post-ParAbstractSimulationTBIND_Post-ParAbstractToTBWPreSimulationTRAN_createPostParTestBenchTRAN_copyPost-ParAbstractToPreSimulationVIEW_TBWPost-ParPreSimulationTBIND_TBWPost-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuse(bencher)VIEW_TBWPost-ParFuseTBIND_TBWPost-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModel(bencher)VIEW_TBWPost-ParSimulationISimTBIND_Post-ParAbstractToPreSimulationVIEW_Post-ParPreSimulationTBIND_Post-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuseVIEW_Post-ParFuseTBIND_Post-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModelVIEW_Post-ParSimulationISimTBIND_ParToMpprResultTRAN_copyMpprRsltVIEW_MpprResultTBIND_ParToLockedPinConstraintsTRAN_genLockedPinConstraintsVIEW_LockedPinConstraintsTBIND_ParToBackAnnoPinLocationsTRAN_backAnnoPinLocationsVIEW_BackAnnoPinLocationsTBINDEXT_ParToFPGAConfiguration_spartan3TRANEXT_bitFile_spartan3VIEW_FPGAConfigurationTBIND_analyzeDesignUsingChipscopeTRAN_analyzeDesignUsingChipscopeVIEW_AnalyzedDesignTBIND_UpdateBitstreamXPSTRAN_xpsUpdBitstreamVIEW_UpdatedBitstreamTBIND_FPGAConfigurationToFPGAGeneratePROMTRAN_genImpactFileVIEW_FPGAGeneratePROMTBIND_FPGAConfigurationToFPGAConfigureTargetDeviceTRAN_configureTargetDeviceVIEW_FPGAConfigureTargetDeviceTBIND_FPGAConfigurationToFPGAConfigureDeviceTRAN_impactProgrammingToolVIEW_FPGAConfigureDeviceTBIND_XSTAbstractToPreSynthesisTRAN_SubProjectAbstractToPreProxyTRAN_convertToHdlTRAN_copyAbstractToPreSynthesisForSynthesisVIEW_XSTAbstractSynthesis/wb_lpc_hostTBIND_InitialToXSTAbstractSynthesisTRAN_copyInitialToXSTAbstractSynthesisVIEW_InitialTBIND_InitialToAbstractSimulationTRAN_copyInitialToAbstractSimulationVIEW_AbstractSimulationTBIND_AbstractToPostAbstractSimulationTRAN_copyAbstractToPostAbstractSimulationVIEW_PostAbstractSimulationTBIND_PostAbstractToTBWPreSimulationTRAN_viewBehavioralTestbenchTRAN_copyPostAbstractToPreSimulationVIEW_TBWPreSimulationTBIND_TBWPreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuse(bencher)VIEW_TBWBehavioralFuseTBIND_TBWBehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModel(bencher)VIEW_TBWBehavioralSimulationISimTBIND_PostAbstractToPreSimulationVIEW_PreSimulationTBIND_PreToBehavioralFuseXST (VHDL/Verilog)trueModule|wb_lpc_master_benchfalseHDLTRAN_ISimulateBehavioralModelRunFuseVIEW_BehavioralFuseTBIND_BehavioralFuseToSimulationISim1000 nsTRAN_ISimulateBehavioralModelVIEW_BehavioralSimulationISimTBIND_PostAbstractToAnnotatedPreSimulationTRAN_viewBehavioralTestbenchForAnnoTRAN_copyPostAbstractToAnnotatedPreSimulationVIEW_AnnotatedPreSimulationTBIND_PreToGenerateAnnotatedResultsFuseTRAN_ISimGenerateAnnotatedResultsRunFuseTRAN_copyPreToGenerateAnnotatedResultsFuseForTBWVIEW_AnnotatedResultsFuseTBIND_FuseToAnnotatedResultsISimTRAN_ISimGenerateAnnotatedResultsTRAN_copyFuseToAnnotatedResultsISimForTBWVIEW_AnnotatedResultsISimTBIND_AnnotatedToGenerateExpectedSimulationResultsISimTRAN_ISimGenerateExpectedSimulationResultsVIEW_ExpectedSimulationResultsISimTBINDEXT_InitialToCommon_FPGATRANEXT_compLibraries_FPGAVIEW_CommonDESPF_TRADITIONALPROP_PreferredLanguageVerilogPROP_SimulatorModelsim-SE MixedISE Simulator (VHDL/Verilog)Other MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-XE VHDLModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE VerilogModelsim-SE VHDLPROP_Synthesis_ToolPROP_Top_Level_Module_TypeVHDLPROP_DevSpeed-5-4PROP_DevPackagepq208fg456PROP_DevDevicexc3s50xc3s400xc3s1500lxc3s1500xc3s1000lxc3s1000xc3s200tq144ft256fg320PROP_ParSmartGuideFileNamewb_lpc_host_guide.ncdPROP_UseSmartGuidePROP_SynthTopModule|wb_lpc_hostNCD files (*.ncd)|*.ncdPROP_MapSmartGuideFileNamePROP_ISimSpecifySearchDirPROP_xstVeriIncludeDirPROP_PostSynthesisSimModelNamewb_lpc_host_synthesis.vPROP_SimModelTargetPROP_ISimSpecifyDefMacroAndValuePROP_ISimSpecifySearchDirectoryPROP_ISimValueRangeCheckPROP_ISimCompileForHdlDebugPROP_ISimIncreCompilationPROP_tbwPostParTestbenchNamewb_lpc_master_bench.timesim_tfwPROP_tbwTestbenchTargetLangPROP_PostParSimTopPROP_tbwPostMapTestbenchNamewb_lpc_master_bench.map_tfwPROP_PostMapSimTopPROP_tbwPostXlateTestbenchNamewb_lpc_master_bench.translate_tfwPROP_PostXlateSimTopPROP_PostParSimModelNamewb_lpc_host_timesim.vPROP_PostMapSimModelNamewb_lpc_host_map.vPROP_PostXlateSimModelNamewb_lpc_host_translate.vPROP_TopDesignUnitPROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3As RequiredPROPEXT_xilxBitgCfg_Rate_spartan3Default (6)PROPEXT_xilxSynthAddBufg_spartan3PROPEXT_xilxSynthMaxFanout_virtex2PROPEXT_SynthMultStyle_virtex2AutoPROPEXT_xilxMapGenInputK_virtex24PROP_MapRegDuplicationPROP_xilxMapTimingDrivenPackingPROP_MapLogicOptimizationPROP_MapPlacerCostTablePROP_MapExtraEffortNonePROP_MapEffortLevelMediumHighStandardContinue on ImpossibleNormalPROP_xilxBitgStart_Clk_MatchCyclePROP_xilxBitgCfg_DCMShutdownPROP_xilxBitgCfg_GenOpt_EnableCRCPROP_xilxBitgCfg_GenOpt_IEEE1532FilePROP_MapPowerActivityFilePROP_MapPowerReductionSAIF Files (*.saif)|*.saifVCD files (*.vcd)|*.vcdPROP_parSmartGuideFileNamePROP_mapSmartGuideFileNamePROP_xstUseSyncResetYesPROP_xstUseSyncSetPROP_xstUseClockEnablePROP_xilxSynthRegDuplicationPROP_xstOptimizeInsPrimtivesPROP_xstSlicePackingPROP_xstPackIORegisterPROP_xstMoveLastFfStagePROP_xilxSynthRegBalancingNoPROP_xstMoveFirstFfStagePROP_SynthLogicalShifterExtractPROP_SynthShiftRegExtractPROP_SynthEncoderExtractPROP_SynthDecoderExtractPROP_SynthMuxStylePROP_SynthExtractMuxMUXCYMUXFPROP_xstROMStylePROP_SynthExtractROMBlockDistributedPROP_SynthRAMStylePROP_SynthExtractRAMPROP_xstFsmStyleLUTPROP_xstCrossClockAnalysisPROP_xstSliceUtilRatioPROP_xstWriteTimingConstraintsPROP_xstCoresSearchDirPROP_xstReadCoresPROP_xstAsynToSyncPROP_xstBRAMUtilRatioPROP_xstAutoBRAMPackingPROP_xilxSynthGlobOptAllClockNetsPROP_CompxlibXlnxCoreLibPROP_impactConfigFileNamePROP_ImpactProjectFilePROP_AceActiveNamePROP_AutoGenFilePROP_primeTopLevelModulePROP_primeCorrelateOutputPROP_primeFlatternOutputNetlistPROP_primetimeBlockRamDataPROP_PreTrceTSIFilePROP_xilxPostTrceTSIFilePROP_PostTrceGenDatasheetPROP_PostTrceGenTimegroupsPROP_PreTrceGenDatasheetPROP_PreTrceGenTimegroupsPROP_xilxPostTrceStampPROP_PostTrceFastPathPROP_xilxPostTrceEndpointPathPROP_xilxPostTrceUncovPathPROP_xilxPostTrceSpeedAbsolute MinPROP_xilxPostTrceAdvAnaPROP_xilxPostTrceRptLimitPROP_xilxPostTrceRptError ReportPROP_PreTrceFastPathPROP_xilxPreTrceEndpointPathPROP_xilxPreTrceUncovPathPROP_xilxPreTrceSpeedPROP_xilxPreTrceAdvAnaPROP_xilxPreTrceRptLimitPROP_xilxPreTrceRptPROP_CurrentFloorplanFilePROP_xilxBitgCfg_GenOpt_MaskFilePROP_xilxBitgCfg_GenOpt_ReadBackPROP_xilxBitgCfg_GenOpt_LogicAllocFilePROP_xilxBitgReadBk_GenBitStrPROP_xilxBitgReadBk_SecEnable Readback and ReconfigurationPROP_xilxBitgStart_Clk_DriveDonePROP_xilxBitgStart_Clk_RelDLLDefault (NoWait)PROP_xilxBitgStart_Clk_WrtEnPROP_xilxBitgStart_Clk_EnOutDefault (5)PROP_xilxBitgStart_Clk_DoneDefault (4)PROP_xilxBitgStart_IntDonePROP_xilxBitgStart_ClkCCLKPROP_xilxBitgCfg_Code0xFFFFFFFFPROP_xilxBitgCfg_UnusedPull DownPROP_xilxBitgCfg_TMSPull UpPROP_xilxBitgCfg_TDOPROP_xilxBitgCfg_TDIPROP_xilxBitgCfg_TCKPROP_xilxBitgCfg_DonePROP_xilxBitgCfg_PgmPROP_xilxBitgCfg_M2PROP_xilxBitgCfg_M1PROP_xilxBitgCfg_M0PROP_xilxBitgCfg_ClkPROP_bitgen_otherCmdLineOptionsPROP_xilxBitgCfg_GenOpt_DbgBitStrPROP_xilxBitgCfg_GenOpt_CompressPROP_xilxBitgCfg_GenOpt_ASCIIFilePROP_xilxBitgCfg_GenOpt_BinaryFilePROP_xilxBitgCfg_GenOpt_BitFilePROP_xilxBitgCfg_GenOpt_DRCPROP_parMpprNodelistFilePROP_xilxPARstratNormal Place and RouteAll files (*)|*PROP_parMpprResultsDirectoryPROP_parMpprResultsToSavePROP_parMpprParIterationsPROP_mpprRsltToCopyPROP_par_otherCmdLineOptionsPROP_parPowerActivityFilePROP_parPowerReductionPROP_parGenSimModelPROP_parGenTimingRptPROP_parGenClkRegionRptPROP_parGenAsyDlyRptPROP_xilxPARuseBondedIOPROP_parTimingModePerformance EvaluationPROP_parIgnoreTimingConstraintsNon Timing DrivenPROP_parUseTimingConstraintsPROP_xilxPARplacerCostTablePROP_xilxPARextraEffortLevelPROP_xilxPARrouterEffortLevelPROP_xilxPARplacerEffortLevelPROP_xilxPAReffortLevelPROP_map_otherCmdLineOptionsPROP_xilxMapSliceLogicInUnusedBRAMsPROP_xilxMapPackfactorPROP_xilxMapDisableRegOrderingPROP_xilxMapPackRegIntoFor Inputs and OutputsPROP_mapUseRLOCConstraintsPROP_xilxMapReportDetailPROP_xilxMapCoverModeAreaPROP_xilxMapAllowLogicOptPROP_xilxMapReplicateLogicPROP_xilxMapTrimUnconnSigPROP_xilxNgdbldPresHierarchyPROP_xilxNgdbldURPROP_xilxNgdbldUnexpBlksPROP_xilxNgdbldIOPadsPROP_xilxNgdbldNTTypeTimestampPROP_ngdbuildUseLOCConstraintsPROP_mapTimingModePROP_mapIgnoreTimingConstraintsPROP_lockPinsUcfFilePROP_Enable_Incremental_MessagingPROP_Enable_Message_FilteringPROP_Enable_Message_CapturePROP_FitterReportFormatHTMLPROP_FlowDebugLevelPROP_UserConstraintEditorPreferenceConstraints EditorPROP_UserEditorCustomSettingPROP_UserEditorPreferenceISE Text EditorPROP_XplorerModeOffPROP_SimModelAutoInsertGlblModuleInNetlistPROP_SimModelGenMultiHierFilePROP_SimModelRetainHierarchyPROP_netgenPostSynthesisSimModelNamePROP_PostSynthSimModelName_synthesis.vPROP_SimModelIncUnisimInVerilogFilePROP_SimModelIncSimprimInVerilogFilePROP_xstSafeImplementPROP_SynthFsmEncodePROP_XPowerOtherXPowerOptsPROP_XPowerOptInputTclScriptPROP_XPowerOptLoadPCFFileDefaultPROP_XPowerOptLoadVCDFilePROP_XPowerOptOutputFilePROP_XPowerOptLoadXMLFilePROP_XPowerOptMaxNumberLinesPROP_XPowerOptVerboseRptPROP_XPowerOptAdvancedVerboseRptPROP_xstNetlistHierarchyAs OptimizedPROP_xilxSynthKeepHierarchyPROP_xilxNgdbldMacroPROP_xilxNgdbld_AULPROP_SynthXORCollapsePROP_ngdbuild_otherCmdLineOptionsPROP_impactPortAuto - defaultUSB 2USB 1LPT 3LPT 2LPT 1PROP_impactConfigModeDesktop ConfigurationSelect MAPSlave SerialBoundary ScanPROP_impactBaud5760038400192009600PROP_ibiswriterShowAllModelsPROP_ISimOtherCompilerOptions_parPROP_ISimOtherCompilerOptions_behavPROP_ISimCustomCompilationOrderFilePROP_ISimUseCustomCompilationOrderPROP_ISimLibSearchOrderFilePROP_ISimSpecifyDefMacroAndValueChkSyntaxPROP_isimSpecifyDefMacroAndValuePROP_ISimSpecifySearchDirectoryChkSyntaxPROP_isimSpecifySearchDirectoryPROP_isimValueRangeCheckPROP_ISimSDFTimingToBeReadSetup TimePROP_ISimVCDFileName_par_tbwxpower.vcdPROP_ISimGenVCDFile_par_tbwPROP_ISimUseCustomSimCmdFile_par_tbwPROP_ISimVCDFileName_par_tbPROP_ISimGenVCDFile_par_tbPROP_ISimUseCustomSimCmdFile_par_tbPROP_ISimStoreAllSignalTransitions_behav_tbwPROP_ISimUseCustomSimCmdFile_behav_tbwPROP_ISimStoreAllSignalTransitions_behav_tbPROP_ISimUseCustomSimCmdFile_behav_tbPROP_ISimStoreAllSignalTransitions_par_tbwPROP_ISimStoreAllSignalTransitions_par_tbPROP_ISimSimulationRunTime_behav_tbwPROP_ISimSimulationRun_behav_tbwPROP_ISimSimulationRunTime_behav_tbPROP_ISimSimulationRun_behav_tbPROP_ISimSimulationRunTime_par_tbwPROP_ISimSimulationRun_par_tbwPROP_ISimSimulationRunTime_par_tbPROP_ISimSimulationRun_par_tbPROP_isimCompileForHdlDebugPROP_isimIncreCompilationPROP_ISimCustomSimCmdFileName_gen_tbwPROP_ISimUseCustomSimCmdFile_gen_tbwPROP_ISimCustomSimCmdFileName_behav_tbwPROP_ISimCustomSimCmdFileName_behav_tbPROP_ISimCustomSimCmdFileName_par_tbwPROP_ISimCustomSimCmdFileName_par_tbPROP_ISimUutInstNameUUTPROP_xstEquivRegRemovalPROP_xilxSynthAddIObufPROP_SynthResSharingPROP_SynthCaseImplStylePROP_xstBusDelimiter<>PROP_xstHierarchySeparator/PROP_xstGenerateRTLNetlistPROP_xst_otherCmdLineOptionsPROP_xstVerilogMacrosPROP_xstGenericsParametersPROP_xstUserCompileListPROP_xstVerilog2001PROP_xstIniFilePROP_xstWorkDir./xstPROP_xstCaseMaintainPROP_xstLibSearchOrderPROP_xstUseSynthConstFilePROP_SynthConstraintsFileCST files (*.cst)|*.cstXCF files (*.xcf)|*.xcfPROP_SynthOptEffortPROP_SynthOptSpeedPROP_bencherPostParTestbenchNamePROP_bencherPostMapTestbenchNamePROP_bencherPostXlateTestbenchNamePROP_netgenPostParSimModelName_timesim.vPROP_netgenPostMapSimModelName_map.vPROP_netgenPostXlateSimModelName_translate.vPROP_SimModelNoEscapeSignalPROP_SimModelPathUsedInSdfAnnPROP_SimModelIncSdfAnnInVerilogFilePROP_SimModelIncUselibDirInVerilogFilePROP_SimModelRenTopLevModPROP_SimModelOtherNetgenOptsPROP_SimModelOutputExtIdentPROP_SimModelGenArchOnlyPROP_SimModelInsertBuffersPulseSwallowPROP_SimModelRenTopLevInstToPROP_SimModelGenerateTestbenchFilePROP_SimModelRenTopLevArchToStructurePROP_netgenRenameTopLevEntToPROP_SimModelRocPulseWidthPROP_SimModelBringOutGsrNetAsAPortPROP_SimModelGsrPortNameGSR_PORTPROP_SimModelTocPulseWidthPROP_SimModelBringOutGtsNetAsAPortPROP_SimModelGtsPortNameGTS_PORTPROP_ChangeDevSpeedPROP_CompxlibLangAllPROP_CompxlibSimPrimativesPROP_CompxlibUniSimLibPROP_CompxlibOtherCompxlibOptsPROP_CompxlibOverwriteLibOverwritePROP_CompxlibSimPathSearch in PathPROP_CompxlibOutputDir$XILINX//PROP_UserBrowsedStrategyFilesPROP_LastUnlockStatusPROP_LastAppliedStrategyXilinx Default (unlocked)PROP_LastAppliedGoalBalancedPROP_DesignNamePROP_PartitionForcePlacementPROP_PartitionForceTranslatePROP_PartitionForceSynthPROP_PartitionCreateDeletePROP_SmartGuideFileNamePROP_PostSynthSimTopPROP_BehavioralSimTopPK
369
!__OBJSTORE__/ProjectNavigatorGui/PK
370
 
371
PK
372
6__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTblModule|wb_lpc_hostwb_lpc_simwb_lpc_master_bench (tb_lpc_top.v)/wb_lpc_master_benchxc3s400-4fg456Design UtilitiesDESUT_VERILOGGenerate Programming FileImplement DesignSynthesize - XSTUser ConstraintsPK
373
__OBJSTORE__/SrcCtrl/PK
374
 
375
 __OBJSTORE__/_ProjRepoInternal_/PK
376
__OBJSTORE__/common/PK
377
'__OBJSTORE__/common/HierarchicalDesign/PK
378
 
379
add7__OBJSTORE__/common/HierarchicalDesign/HDProject_StrTbl
380
14/wb_lpc_hostTS_EXPANDEDTS_FRAGCOVEREDTS_PACKEDTS_ROUTEDTS_SYNTHESISwb_lpc_hostPK
381
";<<+__OBJSTORE__/common/__stored_object_table__(:PK
382
 
383
>5__OBJSTORE__/xreport/Gc_RvReportViewer-Current-ModulePK
384
5:<__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module_StrTblwb_lpc_hostphPK
385
֞1B__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-Factory-Defaultj
386
 
387
D  I__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-Factory-Default_StrTbl[ 
Tue, 05 Sep 2006 12:00:00 PST Unknown
PK
388
/[?__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-wb_dreq_hostk
389

 !"#$%&'()*+,-./0123456789:;<=>?-@ABC+DEF+GHIJK+LMNOPQRSTUVWXYZPK
390
 
391
/[A__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-wb_dreq_masterk
392

 !"#$%&'()*+,-./0123456789:;<=>?-@ABC+DEF+GHIJK+LMNOPQRSTUVWXYZPK
393
MMH__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-wb_dreq_master_StrTbl[ 
2008-03-02T11:53:34 wb_dreq_master 2008-03-02T11:53:34
PK
394
 
395

 !"#$%&'()*+,-./0123456789:;<=>?-@ABC+DEF+GHIJK+LMNOPQRSTUVWXYZPK
396
|3MMH__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-wb_dreq_periph_StrTbl[ 
2008-03-02T12:06:33 wb_dreq_periph 2008-03-02T12:06:33
PK
397
O+>__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-wb_lpc_hostp
398
 
399
Ǒ  E__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-wb_lpc_host_StrTbl` 
2008-07-21T14:53:39 wb_lpc_host 2008-03-02T12:06:39
PK
400

__REGISTRY__/PK
401
__REGISTRY__/Autonym/PK
402
 
403
 __REGISTRY__/HierarchicalDesign/PK
404
*__REGISTRY__/HierarchicalDesign/HDProject/PK
405
XR1__REGISTRY__/HierarchicalDesign/HDProject/regkeysCommandLine-Map
406
 
407
s
408
CommandLine-Ngdbuild
409
410
 
411
CommandLine-Par
412
413
s
414
 
415
416
s
417
Previous-NGD
418
 
419
s
420
Previous-NGM
421
422
 
423
Previous-Packed-NCD
424
425
s
426
 
427
428
s
429
PK
430
 
431
__REGISTRY__/ISimPlugin/PK
432
__REGISTRY__/ISimPlugin/regkeysPK
433
__REGISTRY__/ProjectNavigator/PK
434
 
435
10.1
436
s
437
sMigrationTypeKey
438
 
439
 
440
PK
441 14 hharte
!__REGISTRY__/ProjectNavigatorGui/PK
442 17 hharte
(__REGISTRY__/ProjectNavigatorGui/regkeysPK
443
 
444
__REGISTRY__/SrcCtrl/regkeysPK
445
__REGISTRY__/XSLTProcess/PK
446
q33 __REGISTRY__/XSLTProcess/regkeysClientMessageOutputFile
447
_xmsgs/XSLTProcess.xmsgs
448
s
449
PK

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.