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[/] [wb_sim_models/] [trunk/] [verilog/] [wb_mast_model.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.1.1.1 2001-07-26 08:22:36 rudi Exp $
//
//  $Date: 2001-07-26 08:22:36 $
//  $Revision: 1.1.1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//                        
 
/*
 
task mem_fill;
 
- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values.
 
 
task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data);
 
- Performs a single WISHBONE write
 
 
task wb_wr4( 32 bit address, 4 bit byte select, integer delay,
        32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
 
- Performs 4 consecutive WISHBONE writes
- Strobe is deasserted between writes for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay,
        integer count);
 
- Simular to wb_wr4, except it pwrforms "count" number of write cycles.
  The data is taken from the internal wr_bub[] memory.
- Strobe is deasserted between writes for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
task wb_rmw( 32 bit address, 4 bit byte select, integer delay,
        integer rcount, integer wcount);
 
- This task performs "rcount" read cycles, followed by wcount write cycles.
- read data is placed in to the internal rd_buf[] memory, write data is
  taken from the internal wr_buf[] memory.
- Strobe is deasserted between writes for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
task wb_wmr( 32 bit address, 4 bit byte select, integer delay,
        integer rcount, integer wcount);
 
- This task performs "wcount" write cycles, followed by "rcount" read cycles.
- read data is placed in to the internal rd_buf[] memory, write data is
  taken from the internal wr_buf[] memory.
- Strobe is deasserted between writes for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data);
 
- Performs a single WISHBONE write
 
 
task wb_rd4( 32 bit address, 4 bit byte select, integer delay,
        32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
 
- Performs 4 consecutive WISHBONE reads
- Strobe is deasserted between reads for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay,
        integer count);
 
- Simular to wb_rd4, except it pwrforms "count" number of read cycles.
  The data is read in to the internal rd_buf[] memory.
- Strobe is deasserted between reads for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
*/
 
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   rd_mem[mem_size:0];
reg     [31:0]   wr_mem[mem_size:0];
integer         rd_cnt;
integer         wr_cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        adr = 32'hxxxx_xxxx;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        rd_cnt = 0;
        wr_cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
task mem_fill;
 
integer n;
begin
rd_cnt = 0;
wr_cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        rd_mem[n] = $random;
        wr_mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
 
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
adr = 32'hxxxx_xxxx;
 
wr_cnt = wr_cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)   @(posedge clk);
#1;
we = 0;
sel = s;
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + rcount;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
 
wr_cnt = wr_cnt + wcount;
end
endtask
 
 
 
task wb_wmr;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
sel = 4'hx;
sel = s;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
wr_cnt = wr_cnt + wcount;
stb=0;
repeat(delay)   @(posedge clk);
#1;
 
sel = s;
we = 0;
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
rd_cnt = rd_cnt + rcount;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
 
cyc = 0;
stb = 0;
we  = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
end
endtask
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + count;
end
endtask
 
endmodule

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Subversion Repositories wb_sim_models

[/] [wb_sim_models/] [trunk/] [verilog/] [wb_mast_model.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2001 Rudolf Usselmann ////`
12			`//// rudi@asics.ws ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`// CVS Log`
36			`//`
37			`// $Id: wb_mast_model.v,v 1.1.1.1 2001-07-26 08:22:36 rudi Exp $`
38			`//`
39			`// $Date: 2001-07-26 08:22:36 $`
40			`// $Revision: 1.1.1.1 $`
41			`// $Author: rudi $`
42			`// $Locker: $`
43			`// $State: Exp $`
44			`//`
45			`// Change History:`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48			`//`
49			`//`
50			`//`
51			`//`
52
53			`/*`
54
55			`task mem_fill;`
56
57			`- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values.`
58
59
60			`task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data);`
61
62			`- Performs a single WISHBONE write`
63
64
65			`task wb_wr4( 32 bit address, 4 bit byte select, integer delay,`
66			`32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);`
67
68			`- Performs 4 consecutive WISHBONE writes`
69			`- Strobe is deasserted between writes for 'delay' number of cycles`
70			`(This simulates wait state insertion ...)`
71
72
73			`task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay,`
74			`integer count);`
75
76			`- Simular to wb_wr4, except it pwrforms "count" number of write cycles.`
77			`The data is taken from the internal wr_bub[] memory.`
78			`- Strobe is deasserted between writes for 'delay' number of cycles`
79			`(This simulates wait state insertion ...)`
80
81
82			`task wb_rmw( 32 bit address, 4 bit byte select, integer delay,`
83			`integer rcount, integer wcount);`
84
85			`- This task performs "rcount" read cycles, followed by wcount write cycles.`
86			`- read data is placed in to the internal rd_buf[] memory, write data is`
87			`taken from the internal wr_buf[] memory.`
88			`- Strobe is deasserted between writes for 'delay' number of cycles`
89			`(This simulates wait state insertion ...)`
90
91			`task wb_wmr( 32 bit address, 4 bit byte select, integer delay,`
92			`integer rcount, integer wcount);`
93
94			`- This task performs "wcount" write cycles, followed by "rcount" read cycles.`
95			`- read data is placed in to the internal rd_buf[] memory, write data is`
96			`taken from the internal wr_buf[] memory.`
97			`- Strobe is deasserted between writes for 'delay' number of cycles`
98			`(This simulates wait state insertion ...)`
99
100			`task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data);`
101
102			`- Performs a single WISHBONE write`
103
104
105			`task wb_rd4( 32 bit address, 4 bit byte select, integer delay,`
106			`32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);`
107
108			`- Performs 4 consecutive WISHBONE reads`
109			`- Strobe is deasserted between reads for 'delay' number of cycles`
110			`(This simulates wait state insertion ...)`
111
112
113			`task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay,`
114			`integer count);`
115
116			`- Simular to wb_rd4, except it pwrforms "count" number of read cycles.`
117			`The data is read in to the internal rd_buf[] memory.`
118			`- Strobe is deasserted between reads for 'delay' number of cycles`
119			`(This simulates wait state insertion ...)`
120
121			`*/`
122
123
124			`include "wb_model_defines.v"
125
126			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
127
128			`input clk, rst;`
129			`output [31:0] adr;`
130			`input [31:0] din;`
131			`output [31:0] dout;`
132			`output cyc, stb;`
133			`output [3:0] sel;`
134			`output we;`
135			`input ack, err, rty;`
136
137			`////////////////////////////////////////////////////////////////////`
138			`//`
139			`// Local Wires`
140			`//`
141
142			`parameter mem_size = 4096;`
143
144			`reg [31:0] adr;`
145			`reg [31:0] dout;`
146			`reg cyc, stb;`
147			`reg [3:0] sel;`
148			`reg we;`
149
150			`reg [31:0] rd_mem[mem_size:0];`
151			`reg [31:0] wr_mem[mem_size:0];`
152			`integer rd_cnt;`
153			`integer wr_cnt;`
154
155			`////////////////////////////////////////////////////////////////////`
156			`//`
157			`// Memory Logic`
158			`//`
159
160			`initial`
161			`begin`
162			`adr = 32'hxxxx_xxxx;`
163			`dout = 32'hxxxx_xxxx;`
164			`cyc = 0;`
165			`stb = 0;`
166			`sel = 4'hx;`
167			`we = 1'hx;`
168			`rd_cnt = 0;`
169			`wr_cnt = 0;`
170			`#1;`
171			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
172			`end`
173
174
175			`task mem_fill;`
176
177			`integer n;`
178			`begin`
179			`rd_cnt = 0;`
180			`wr_cnt = 0;`
181			`for(n=0;n<mem_size;n=n+1)`
182			`begin`
183			`rd_mem[n] = $random;`
184			`wr_mem[n] = $random;`
185			`end`
186			`end`
187			`endtask`
188
189			`////////////////////////////////////////////////////////////////////`
190			`//`
191			`// Write 1 Word Task`
192			`//`
193
194			`task wb_wr1;`
195			`input [31:0] a;`
196			`input [3:0] s;`
197			`input [31:0] d;`
198
199			`begin`
200
201			`@(posedge clk);`
202			`#1;`
203			`adr = a;`
204			`dout = d;`
205			`cyc = 1;`
206			`stb = 1;`
207			`we=1;`
208			`sel = s;`
209
210			`@(posedge clk);`
211			`while(~ack & ~err) @(posedge clk);`
212			`#1;`
213			`cyc=0;`
214			`stb=0;`
215			`adr = 32'hxxxx_xxxx;`
216			`dout = 32'hxxxx_xxxx;`
217			`we = 1'hx;`
218			`sel = 4'hx;`
219
220			`end`
221			`endtask`
222
223			`////////////////////////////////////////////////////////////////////`
224			`//`
225			`// Write 4 Words Task`
226			`//`
227
228			`task wb_wr4;`
229			`input [31:0] a;`
230			`input [3:0] s;`
231			`input delay;`
232			`input [31:0] d1;`
233			`input [31:0] d2;`
234			`input [31:0] d3;`
235			`input [31:0] d4;`
236
237			`integer delay;`
238
239			`begin`
240
241			`@(posedge clk);`
242			`#1;`
243			`cyc = 1;`
244			`sel = s;`
245
246			`repeat(delay)`
247			`begin`
248			`@(posedge clk);`
249			`#1;`
250			`end`
251			`adr = a;`
252			`dout = d1;`
253			`stb = 1;`
254			`we=1;`
255			`while(~ack & ~err) @(posedge clk);`
256			`#2;`
257			`stb=0;`
258			`we=1'bx;`
259			`dout = 32'hxxxx_xxxx;`
260			`adr = 32'hxxxx_xxxx;`
261
262			`repeat(delay)`
263			`begin`
264			`@(posedge clk);`
265			`#1;`
266			`end`
267			`stb=1;`
268			`adr = a+4;`
269			`dout = d2;`
270			`we=1;`
271			`@(posedge clk);`
272			`while(~ack & ~err) @(posedge clk);`
273			`#2;`
274			`stb=0;`
275			`we=1'bx;`
276			`dout = 32'hxxxx_xxxx;`
277			`adr = 32'hxxxx_xxxx;`
278
279			`repeat(delay)`
280			`begin`
281			`@(posedge clk);`
282			`#1;`
283			`end`
284			`stb=1;`
285			`adr = a+8;`
286			`dout = d3;`
287			`we=1;`
288			`@(posedge clk);`
289			`while(~ack & ~err) @(posedge clk);`
290			`#2;`
291			`stb=0;`
292			`we=1'bx;`
293			`dout = 32'hxxxx_xxxx;`
294			`adr = 32'hxxxx_xxxx;`
295
296			`repeat(delay)`
297			`begin`
298			`@(posedge clk);`
299			`#1;`
300			`end`
301			`stb=1;`
302			`adr = a+12;`
303			`dout = d4;`
304			`we=1;`
305			`@(posedge clk);`
306			`while(~ack & ~err) @(posedge clk);`
307			`#1;`
308			`stb=0;`
309			`cyc=0;`
310
311			`adr = 32'hxxxx_xxxx;`
312			`dout = 32'hxxxx_xxxx;`
313			`we = 1'hx;`
314			`sel = 4'hx;`
315
316			`end`
317			`endtask`
318
319
320			`task wb_wr_mult;`
321			`input [31:0] a;`
322			`input [3:0] s;`
323			`input delay;`
324			`input count;`
325
326			`integer delay;`
327			`integer count;`
328			`integer n;`
329
330			`begin`
331
332			`@(posedge clk);`
333			`#1;`
334			`cyc = 1;`
335
336			`for(n=0;n<count;n=n+1)`
337			`begin`
338			`repeat(delay)`
339			`begin`
340			`@(posedge clk);`
341			`#1;`
342			`end`
343			`adr = a + (n*4);`
344			`dout = wr_mem[n + wr_cnt];`
345			`stb = 1;`
346			`we=1;`
347			`sel = s;`
348			`if(n!=0) @(posedge clk);`
349			`while(~ack & ~err) @(posedge clk);`
350			`#2;`
351			`stb=0;`
352			`we=1'bx;`
353			`sel = 4'hx;`
354			`dout = 32'hxxxx_xxxx;`
355			`adr = 32'hxxxx_xxxx;`
356			`end`
357
358			`cyc=0;`
359			`adr = 32'hxxxx_xxxx;`
360
361			`wr_cnt = wr_cnt + count;`
362			`end`
363			`endtask`
364
365
366			`task wb_rmw;`
367			`input [31:0] a;`
368			`input [3:0] s;`
369			`input delay;`
370			`input rcount;`
371			`input wcount;`
372
373			`integer delay;`
374			`integer rcount;`
375			`integer wcount;`
376			`integer n;`
377
378			`begin`
379
380			`@(posedge clk);`
381			`#1;`
382			`cyc = 1;`
383			`we = 1'bx;`
384			`sel = 4'hx;`
385			`adr = 32'hxxxx_xxxx;`
386			`repeat(delay) @(posedge clk);`
387			`#1;`
388			`we = 0;`
389			`sel = s;`
390
391			`for(n=0;n<rcount-1;n=n+1)`
392			`begin`
393			`adr = a + (n*4);`
394			`stb = 1;`
395			`while(~ack & ~err) @(posedge clk);`
396			`rd_mem[n + rd_cnt] = din;`
397			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
398			`#2;`
399			`stb=0;`
400			`we = 1'hx;`
401			`sel = 4'hx;`
402			`adr = 32'hxxxx_xxxx;`
403			`repeat(delay)`
404			`begin`
405			`@(posedge clk);`
406			`#1;`
407			`end`
408			`we = 0;`
409			`sel = s;`
410			`end`
411
412			`adr = a+(n*4);`
413			`stb = 1;`
414			`@(posedge clk);`
415			`while(~ack & ~err) @(posedge clk);`
416			`rd_mem[n + rd_cnt] = din;`
417			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
418			`#1;`
419			`stb=0;`
420			`we = 1'hx;`
421			`sel = 4'hx;`
422			`adr = 32'hxxxx_xxxx;`
423
424			`rd_cnt = rd_cnt + rcount;`
425
426			`for(n=0;n<wcount;n=n+1)`
427			`begin`
428			`repeat(delay)`
429			`begin`
430			`@(posedge clk);`
431			`#1;`
432			`end`
433			`adr = a + (n*4);`
434			`dout = wr_mem[n + wr_cnt];`
435			`stb = 1;`
436			`we=1;`
437			`sel = s;`
438			`@(posedge clk);`
439			`while(~ack & ~err) @(posedge clk);`
440			`#2;`
441			`stb=0;`
442			`we=1'bx;`
443			`sel = 4'hx;`
444			`dout = 32'hxxxx_xxxx;`
445			`adr = 32'hxxxx_xxxx;`
446			`end`
447
448			`cyc=0;`
449			`stb=0;`
450			`we=1'bx;`
451			`sel = 4'hx;`
452			`dout = 32'hxxxx_xxxx;`
453			`adr = 32'hxxxx_xxxx;`
454
455			`wr_cnt = wr_cnt + wcount;`
456			`end`
457			`endtask`
458
459
460
461			`task wb_wmr;`
462			`input [31:0] a;`
463			`input [3:0] s;`
464			`input delay;`
465			`input rcount;`
466			`input wcount;`
467
468			`integer delay;`
469			`integer rcount;`
470			`integer wcount;`
471			`integer n;`
472
473			`begin`
474
475			`@(posedge clk);`
476			`#1;`
477			`cyc = 1;`
478			`we = 1'bx;`
479			`sel = 4'hx;`
480			`sel = s;`
481
482			`for(n=0;n<wcount;n=n+1)`
483			`begin`
484			`repeat(delay)`
485			`begin`
486			`@(posedge clk);`
487			`#1;`
488			`end`
489			`adr = a + (n*4);`
490			`dout = wr_mem[n + wr_cnt];`
491			`stb = 1;`
492			`we=1;`
493			`sel = s;`
494			`@(posedge clk);`
495			`while(~ack & ~err) @(posedge clk);`
496			`#2;`
497			`stb=0;`
498			`we=1'bx;`
499			`sel = 4'hx;`
500			`dout = 32'hxxxx_xxxx;`
501			`adr = 32'hxxxx_xxxx;`
502			`end`
503
504			`wr_cnt = wr_cnt + wcount;`
505			`stb=0;`
506			`repeat(delay) @(posedge clk);`
507			`#1;`
508
509			`sel = s;`
510			`we = 0;`
511			`for(n=0;n<rcount-1;n=n+1)`
512			`begin`
513			`adr = a + (n*4);`
514			`stb = 1;`
515			`while(~ack & ~err) @(posedge clk);`
516			`rd_mem[n + rd_cnt] = din;`
517			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
518			`#2;`
519			`stb=0;`
520			`we = 1'hx;`
521			`sel = 4'hx;`
522			`adr = 32'hxxxx_xxxx;`
523			`repeat(delay)`
524			`begin`
525			`@(posedge clk);`
526			`#1;`
527			`end`
528			`we = 0;`
529			`sel = s;`
530			`end`
531
532			`adr = a+(n*4);`
533			`stb = 1;`
534			`@(posedge clk);`
535			`while(~ack & ~err) @(posedge clk);`
536			`rd_mem[n + rd_cnt] = din;`
537			`rd_cnt = rd_cnt + rcount;`
538			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
539			`#1;`
540
541			`cyc = 0;`
542			`stb = 0;`
543			`we = 1'hx;`
544			`sel = 4'hx;`
545			`adr = 32'hxxxx_xxxx;`
546
547			`end`
548			`endtask`
549
550
551			`////////////////////////////////////////////////////////////////////`
552			`//`
553			`// Read 1 Word Task`
554			`//`
555
556			`task wb_rd1;`
557			`input [31:0] a;`
558			`input [3:0] s;`
559			`output [31:0] d;`
560
561			`begin`
562
563			`@(posedge clk);`
564			`#1;`
565			`adr = a;`
566			`cyc = 1;`
567			`stb = 1;`
568			`we = 0;`
569			`sel = s;`
570
571			`while(~ack & ~err) @(posedge clk);`
572			`d = din;`
573			`#1;`
574			`cyc=0;`
575			`stb=0;`
576			`adr = 32'hxxxx_xxxx;`
577			`dout = 32'hxxxx_xxxx;`
578			`we = 1'hx;`
579			`sel = 4'hx;`
580
581			`end`
582			`endtask`
583
584
585			`////////////////////////////////////////////////////////////////////`
586			`//`
587			`// Read 4 Words Task`
588			`//`
589
590
591			`task wb_rd4;`
592			`input [31:0] a;`
593			`input [3:0] s;`
594			`input delay;`
595			`output [31:0] d1;`
596			`output [31:0] d2;`
597			`output [31:0] d3;`
598			`output [31:0] d4;`
599
600			`integer delay;`
601			`begin`
602
603			`@(posedge clk);`
604			`#1;`
605			`cyc = 1;`
606			`we = 0;`
607			`sel = s;`
608			`repeat(delay) @(posedge clk);`
609
610			`adr = a;`
611			`stb = 1;`
612			`while(~ack & ~err) @(posedge clk);`
613			`d1 = din;`
614			`#2;`
615			`stb=0;`
616			`we = 1'hx;`
617			`sel = 4'hx;`
618			`adr = 32'hxxxx_xxxx;`
619			`repeat(delay)`
620			`begin`
621			`@(posedge clk);`
622			`#1;`
623			`end`
624			`we = 0;`
625			`sel = s;`
626
627			`adr = a+4;`
628			`stb = 1;`
629			`@(posedge clk);`
630			`while(~ack & ~err) @(posedge clk);`
631			`d2 = din;`
632			`#2;`
633			`stb=0;`
634			`we = 1'hx;`
635			`sel = 4'hx;`
636			`adr = 32'hxxxx_xxxx;`
637			`repeat(delay)`
638			`begin`
639			`@(posedge clk);`
640			`#1;`
641			`end`
642			`we = 0;`
643			`sel = s;`
644
645
646			`adr = a+8;`
647			`stb = 1;`
648			`@(posedge clk);`
649			`while(~ack & ~err) @(posedge clk);`
650			`d3 = din;`
651			`#2;`
652			`stb=0;`
653			`we = 1'hx;`
654			`sel = 4'hx;`
655			`adr = 32'hxxxx_xxxx;`
656			`repeat(delay)`
657			`begin`
658			`@(posedge clk);`
659			`#1;`
660			`end`
661			`we = 0;`
662			`sel = s;`
663
664			`adr = a+12;`
665			`stb = 1;`
666			`@(posedge clk);`
667			`while(~ack & ~err) @(posedge clk);`
668			`d4 = din;`
669			`#1;`
670			`stb=0;`
671			`cyc=0;`
672			`we = 1'hx;`
673			`sel = 4'hx;`
674			`adr = 32'hxxxx_xxxx;`
675			`end`
676			`endtask`
677
678
679			`task wb_rd_mult;`
680			`input [31:0] a;`
681			`input [3:0] s;`
682			`input delay;`
683			`input count;`
684
685			`integer delay;`
686			`integer count;`
687			`integer n;`
688
689			`begin`
690
691			`@(posedge clk);`
692			`#1;`
693			`cyc = 1;`
694			`we = 0;`
695			`sel = s;`
696			`repeat(delay) @(posedge clk);`
697
698			`for(n=0;n<count-1;n=n+1)`
699			`begin`
700			`adr = a + (n*4);`
701			`stb = 1;`
702			`while(~ack & ~err) @(posedge clk);`
703			`rd_mem[n + rd_cnt] = din;`
704			`#2;`
705			`stb=0;`
706			`we = 1'hx;`
707			`sel = 4'hx;`
708			`adr = 32'hxxxx_xxxx;`
709			`repeat(delay)`
710			`begin`
711			`@(posedge clk);`
712			`#1;`
713			`end`
714			`we = 0;`
715			`sel = s;`
716			`end`
717
718			`adr = a+(n*4);`
719			`stb = 1;`
720			`@(posedge clk);`
721			`while(~ack & ~err) @(posedge clk);`
722			`rd_mem[n + rd_cnt] = din;`
723			`#1;`
724			`stb=0;`
725			`cyc=0;`
726			`we = 1'hx;`
727			`sel = 4'hx;`
728			`adr = 32'hxxxx_xxxx;`
729
730			`rd_cnt = rd_cnt + count;`
731			`end`
732			`endtask`
733
734			`endmodule`