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[/] [wb_size_bridge/] [trunk/] [tb/] [models/] [wb_master_model.v] - Blame information for rev 6

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///////////////////////////////////////////////////////////////////////
////                                                               ////
////  WISHBONE rev.B2 Wishbone Master model                        ////
////                                                               ////
////                                                               ////
////  Author: Richard Herveille                                    ////
////          richard@asics.ws                                     ////
////          www.asics.ws                                         ////
////                                                               ////
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
////                                                               ////
//// Copyright (C) 2001 Richard Herveille                          ////
////                    richard@asics.ws                           ////
////                                                               ////
//// This source file may be used and distributed without          ////
//// restriction provided that this copyright statement is not     ////
//// removed from the file and that any derivative work contains   ////
//// the original copyright notice and the associated disclaimer.  ////
////                                                               ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/10ps
 
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
 
  //
  // parameters
  //
  parameter dwidth = 32;
  parameter awidth = 32;
 
  parameter log_level = 3;
 
  //
  // inputs & outputs
  //
  input                  clk, rst;
  output [awidth   -1:0]  adr;
  input  [dwidth   -1:0]  din;
  output [dwidth   -1:0]  dout;
  output                 cyc, stb;
  output                  we;
  output [dwidth/8 -1:0] sel;
  input                   ack, err, rty;
 
  //
  // variables
  //
  reg [awidth   -1:0] adr;
  reg [dwidth   -1:0] dout;
  reg                  cyc, stb;
  reg                  we;
  reg [dwidth/8 -1:0] sel;
 
  reg [dwidth   -1:0] q;
 
  integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
 
 
  //
  // module body
  //
 
  // check ack, err and rty assertion
  always@(ack or err or rty)
  begin
    case ({ack, err, rty})
      // ok-states
//      3'b000: // none asserted
//      3'b001: // only rty asserted
//      3'b010: // only err asserted
//      3'b100: // only ack asserted
 
      // fault-states
      3'b011: // oops, err and rty
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
        end
      3'b101: // oops, ack and rty
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
        end
      3'b110: // oops, ack and err
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
        end
      3'b111: // oops, ack, err and rty
        begin
          err_wb_cnt = err_wb_cnt +1;
          $display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
        end
    endcase
 
    if (err_wb_cnt > err_watchdog)
      begin
        $display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
        $stop;
      end
  end
 
  // initial settings
  initial
  begin
    //adr = 32'hxxxx_xxxx;
    //adr = 0;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    cyc  = 1'b0;
    stb  = 1'bx;
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
 
    err_tot_cnt = 0;
    err_cur_cnt = 0;
    err_wb_cnt  = 0;
    err_watchdog = 3;
 
    #1;
    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
  end
 
 
  ////////////////////////////
  //
  // Wishbone write cycle
  //
 
  task wb_write;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input [awidth -1:0] a;
    input [dwidth -1:0] d;
 
  begin
 
    if( log_level > 2 )
      $display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = d;
    stb  = 1'b1;
    we   = 1'b1;
    sel  = {dwidth/8{1'b1}};
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
 
  end
  endtask
 
  task wb_write_sel;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input [dwidth/8 -1:0] s;
    input [awidth   -1:0] a;
    input [dwidth   -1:0] d;
 
  begin
 
    if( log_level > 2 )
      $display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = d;
    stb  = 1'b1;
    we   = 1'b1;
    sel  = s;
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
 
  end
  endtask
 
  ////////////////////////////
  //
  // Wishbone read cycle
  //
 
  task wb_read;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input  [awidth -1:0]  a;
    output  [dwidth -1:0] d;
 
  begin
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = {dwidth{1'bx}};
    stb  = 1'b1;
    we   = 1'b0;
    sel  = {dwidth/8{1'b1}};
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
    d    = din;
 
    if( log_level > 2 )
      $display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );
  end
  endtask
 
  task wb_read_sel;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input  [dwidth/8 -1:0] s;
    input  [awidth   -1:0]  a;
    output  [dwidth   -1:0] d;
 
  begin
 
    // wait initial delay
    repeat(delay) @(posedge clk);
 
    #1;
    // assert cyc_signal
    cyc  = 1'b1;
    stb  = 1'b0;
 
    // wait for stb_assertion
    repeat(stb_delay) @(posedge clk);
 
    // assert wishbone signals
    adr  = a;
    dout = {dwidth{1'bx}};
    stb  = 1'b1;
    we   = 1'b0;
    sel  = s;
    @(posedge clk);
 
    // wait for acknowledge from slave
    // err is treated as normal ack
    // rty is ignored (thus retrying cycle)
    while(~ (ack || err)) @(posedge clk);
 
    // negate wishbone signals
    #1;
    cyc  = 1'b0;
    stb  = 1'bx;
    adr  = {awidth{1'bx}};
    dout = {dwidth{1'bx}};
    we   = 1'hx;
    sel  = {dwidth/8{1'bx}};
    d    = din;
 
    if( log_level > 2 )
      $display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
  end
  endtask
 
  ////////////////////////////
  //
  // Wishbone compare cycle
  // read data from location and compare with expected data
  //
 
  task wb_cmp;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input [awidth -1:0] a;
    input [dwidth -1:0] d_exp;
 
  begin
    wb_read (delay, stb_delay, a, q);
 
    if (d_exp !== q)
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
      end
 
    if (err_tot_cnt > err_watchdog)
      begin
        $display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
        $stop;
      end
  end
  endtask
 
 
  task wb_cmp_sel;
    input   delay;
    integer delay;
    input   stb_delay;
    integer stb_delay;
 
    input  [dwidth/8 -1:0] s;
    input [awidth -1:0] a;
    input [dwidth -1:0] d_exp;
 
  begin
    wb_read_sel (delay, stb_delay, s, a, q);
 
    if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);
      end
 
    if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);
      end
 
    if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);
      end
 
    if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);
      end
 
    if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);
      end
 
    if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);
      end
 
    if( (d_exp !== q) & s == 4'b1111 )
      begin
        err_tot_cnt = err_tot_cnt +1;
        err_cur_cnt = err_cur_cnt +1;
        $display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
      end
 
      case( s )
        4'b0001:  ;
        4'b0010:  ;
        4'b0100:  ;
        4'b1000:  ;
        4'b0011:  ;
        4'b1100:  ;
        4'b1111:  ;
        default:  $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );
      endcase
 
 
    if (err_tot_cnt > err_watchdog)
      begin
        $display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
        $stop;
      end
  end
  endtask
 
 
  ////////////////////////////
  //
  // Error counter handlers
  //
  task set_cur_err_cnt;
    input value;
  begin
    err_cur_cnt = value;
  end
  endtask
 
  task show_cur_err_cnt;
    $display("\nCurrent errors detected: %d\n", err_cur_cnt);
  endtask
 
  task show_tot_err_cnt;
    $display("\nTotal errors detected: %d\n", err_tot_cnt);
  endtask
 
 
  always @(posedge clk)
    if( err & (cyc == 1'b1) & (stb == 1'b1) )
      $display( "!!!- WB Bus Error at time %t. ", $time );
 
endmodule
 

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Subversion Repositories wb_size_bridge

[/] [wb_size_bridge/] [trunk/] [tb/] [models/] [wb_master_model.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	qaztronic	`///////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 Wishbone Master model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////`
11			`//// ////`
12			`///////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`///////////////////////////////////////////////////////////////////////`
37
38
39			`timescale 1ns/10ps
40
41
42			`module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);`
43
44			`//`
45			`// parameters`
46			`//`
47			`parameter dwidth = 32;`
48			`parameter awidth = 32;`
49
50			`parameter log_level = 3;`
51
52			`//`
53			`// inputs & outputs`
54			`//`
55			`input clk, rst;`
56			`output [awidth -1:0] adr;`
57			`input [dwidth -1:0] din;`
58			`output [dwidth -1:0] dout;`
59			`output cyc, stb;`
60			`output we;`
61			`output [dwidth/8 -1:0] sel;`
62			`input ack, err, rty;`
63
64			`//`
65			`// variables`
66			`//`
67			`reg [awidth -1:0] adr;`
68			`reg [dwidth -1:0] dout;`
69			`reg cyc, stb;`
70			`reg we;`
71			`reg [dwidth/8 -1:0] sel;`
72
73			`reg [dwidth -1:0] q;`
74
75			`integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;`
76
77
78			`//`
79			`// module body`
80			`//`
81
82			`// check ack, err and rty assertion`
83			`always@(ack or err or rty)`
84			`begin`
85			`case ({ack, err, rty})`
86			`// ok-states`
87			`// 3'b000: // none asserted`
88			`// 3'b001: // only rty asserted`
89			`// 3'b010: // only err asserted`
90			`// 3'b100: // only ack asserted`
91
92			`// fault-states`
93			`3'b011: // oops, err and rty`
94			`begin`
95			`err_wb_cnt = err_wb_cnt +1;`
96			`$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);`
97			`end`
98			`3'b101: // oops, ack and rty`
99			`begin`
100			`err_wb_cnt = err_wb_cnt +1;`
101			`$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);`
102			`end`
103			`3'b110: // oops, ack and err`
104			`begin`
105			`err_wb_cnt = err_wb_cnt +1;`
106			`$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);`
107			`end`
108			`3'b111: // oops, ack, err and rty`
109			`begin`
110			`err_wb_cnt = err_wb_cnt +1;`
111			`$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);`
112			`end`
113			`endcase`
114
115			`if (err_wb_cnt > err_watchdog)`
116			`begin`
117			`$display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);`
118			`$stop;`
119			`end`
120			`end`
121
122			`// initial settings`
123			`initial`
124			`begin`
125			`//adr = 32'hxxxx_xxxx;`
126			`//adr = 0;`
127			`adr = {awidth{1'bx}};`
128			`dout = {dwidth{1'bx}};`
129			`cyc = 1'b0;`
130			`stb = 1'bx;`
131			`we = 1'hx;`
132			`sel = {dwidth/8{1'bx}};`
133
134			`err_tot_cnt = 0;`
135			`err_cur_cnt = 0;`
136			`err_wb_cnt = 0;`
137			`err_watchdog = 3;`
138
139			`#1;`
140			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
141			`end`
142
143
144			`////////////////////////////`
145			`//`
146			`// Wishbone write cycle`
147			`//`
148
149			`task wb_write;`
150			`input delay;`
151			`integer delay;`
152			`input stb_delay;`
153			`integer stb_delay;`
154
155			`input [awidth -1:0] a;`
156			`input [dwidth -1:0] d;`
157
158			`begin`
159
160			`if( log_level > 2 )`
161			`$display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );`
162
163			`// wait initial delay`
164			`repeat(delay) @(posedge clk);`
165
166			`#1;`
167			`// assert cyc_signal`
168			`cyc = 1'b1;`
169			`stb = 1'b0;`
170
171			`// wait for stb_assertion`
172			`repeat(stb_delay) @(posedge clk);`
173
174			`// assert wishbone signals`
175			`adr = a;`
176			`dout = d;`
177			`stb = 1'b1;`
178			`we = 1'b1;`
179			`sel = {dwidth/8{1'b1}};`
180			`@(posedge clk);`
181
182			`// wait for acknowledge from slave`
183			`// err is treated as normal ack`
184			`// rty is ignored (thus retrying cycle)`
185			`while(~ (ack \|\| err)) @(posedge clk);`
186
187			`// negate wishbone signals`
188			`#1;`
189			`cyc = 1'b0;`
190			`stb = 1'bx;`
191			`adr = {awidth{1'bx}};`
192			`dout = {dwidth{1'bx}};`
193			`we = 1'hx;`
194			`sel = {dwidth/8{1'bx}};`
195
196			`end`
197			`endtask`
198
199			`task wb_write_sel;`
200			`input delay;`
201			`integer delay;`
202			`input stb_delay;`
203			`integer stb_delay;`
204
205			`input [dwidth/8 -1:0] s;`
206			`input [awidth -1:0] a;`
207			`input [dwidth -1:0] d;`
208
209			`begin`
210
211			`if( log_level > 2 )`
212			`$display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );`
213
214			`// wait initial delay`
215			`repeat(delay) @(posedge clk);`
216
217			`#1;`
218			`// assert cyc_signal`
219			`cyc = 1'b1;`
220			`stb = 1'b0;`
221
222			`// wait for stb_assertion`
223			`repeat(stb_delay) @(posedge clk);`
224
225			`// assert wishbone signals`
226			`adr = a;`
227			`dout = d;`
228			`stb = 1'b1;`
229			`we = 1'b1;`
230			`sel = s;`
231			`@(posedge clk);`
232
233			`// wait for acknowledge from slave`
234			`// err is treated as normal ack`
235			`// rty is ignored (thus retrying cycle)`
236			`while(~ (ack \|\| err)) @(posedge clk);`
237
238			`// negate wishbone signals`
239			`#1;`
240			`cyc = 1'b0;`
241			`stb = 1'bx;`
242			`adr = {awidth{1'bx}};`
243			`dout = {dwidth{1'bx}};`
244			`we = 1'hx;`
245			`sel = {dwidth/8{1'bx}};`
246
247			`end`
248			`endtask`
249
250			`////////////////////////////`
251			`//`
252			`// Wishbone read cycle`
253			`//`
254
255			`task wb_read;`
256			`input delay;`
257			`integer delay;`
258			`input stb_delay;`
259			`integer stb_delay;`
260
261			`input [awidth -1:0] a;`
262			`output [dwidth -1:0] d;`
263
264			`begin`
265
266			`// wait initial delay`
267			`repeat(delay) @(posedge clk);`
268
269			`#1;`
270			`// assert cyc_signal`
271			`cyc = 1'b1;`
272			`stb = 1'b0;`
273
274			`// wait for stb_assertion`
275			`repeat(stb_delay) @(posedge clk);`
276
277			`// assert wishbone signals`
278			`adr = a;`
279			`dout = {dwidth{1'bx}};`
280			`stb = 1'b1;`
281			`we = 1'b0;`
282			`sel = {dwidth/8{1'b1}};`
283			`@(posedge clk);`
284
285			`// wait for acknowledge from slave`
286			`// err is treated as normal ack`
287			`// rty is ignored (thus retrying cycle)`
288			`while(~ (ack \|\| err)) @(posedge clk);`
289
290			`// negate wishbone signals`
291			`#1;`
292			`cyc = 1'b0;`
293			`stb = 1'bx;`
294			`adr = {awidth{1'bx}};`
295			`dout = {dwidth{1'bx}};`
296			`we = 1'hx;`
297			`sel = {dwidth/8{1'bx}};`
298			`d = din;`
299
300			`if( log_level > 2 )`
301			`$display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );`
302			`end`
303			`endtask`
304
305			`task wb_read_sel;`
306			`input delay;`
307			`integer delay;`
308			`input stb_delay;`
309			`integer stb_delay;`
310
311			`input [dwidth/8 -1:0] s;`
312			`input [awidth -1:0] a;`
313			`output [dwidth -1:0] d;`
314
315			`begin`
316
317			`// wait initial delay`
318			`repeat(delay) @(posedge clk);`
319
320			`#1;`
321			`// assert cyc_signal`
322			`cyc = 1'b1;`
323			`stb = 1'b0;`
324
325			`// wait for stb_assertion`
326			`repeat(stb_delay) @(posedge clk);`
327
328			`// assert wishbone signals`
329			`adr = a;`
330			`dout = {dwidth{1'bx}};`
331			`stb = 1'b1;`
332			`we = 1'b0;`
333			`sel = s;`
334			`@(posedge clk);`
335
336			`// wait for acknowledge from slave`
337			`// err is treated as normal ack`
338			`// rty is ignored (thus retrying cycle)`
339			`while(~ (ack \|\| err)) @(posedge clk);`
340
341			`// negate wishbone signals`
342			`#1;`
343			`cyc = 1'b0;`
344			`stb = 1'bx;`
345			`adr = {awidth{1'bx}};`
346			`dout = {dwidth{1'bx}};`
347			`we = 1'hx;`
348			`sel = {dwidth/8{1'bx}};`
349			`d = din;`
350
351			`if( log_level > 2 )`
352			`$display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );`
353			`end`
354			`endtask`
355
356			`////////////////////////////`
357			`//`
358			`// Wishbone compare cycle`
359			`// read data from location and compare with expected data`
360			`//`
361
362			`task wb_cmp;`
363			`input delay;`
364			`integer delay;`
365			`input stb_delay;`
366			`integer stb_delay;`
367
368			`input [awidth -1:0] a;`
369			`input [dwidth -1:0] d_exp;`
370
371			`begin`
372			`wb_read (delay, stb_delay, a, q);`
373
374			`if (d_exp !== q)`
375			`begin`
376			`err_tot_cnt = err_tot_cnt +1;`
377			`err_cur_cnt = err_cur_cnt +1;`
378			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);`
379			`end`
380
381			`if (err_tot_cnt > err_watchdog)`
382			`begin`
383			`$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);`
384			`$stop;`
385			`end`
386			`end`
387			`endtask`
388
389
390			`task wb_cmp_sel;`
391			`input delay;`
392			`integer delay;`
393			`input stb_delay;`
394			`integer stb_delay;`
395
396			`input [dwidth/8 -1:0] s;`
397			`input [awidth -1:0] a;`
398			`input [dwidth -1:0] d_exp;`
399
400			`begin`
401			`wb_read_sel (delay, stb_delay, s, a, q);`
402
403			`if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )`
404			`begin`
405			`err_tot_cnt = err_tot_cnt +1;`
406			`err_cur_cnt = err_cur_cnt +1;`
407			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);`
408			`end`
409
410			`if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )`
411			`begin`
412			`err_tot_cnt = err_tot_cnt +1;`
413			`err_cur_cnt = err_cur_cnt +1;`
414			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);`
415			`end`
416
417			`if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )`
418			`begin`
419			`err_tot_cnt = err_tot_cnt +1;`
420			`err_cur_cnt = err_cur_cnt +1;`
421			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);`
422			`end`
423
424			`if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )`
425			`begin`
426			`err_tot_cnt = err_tot_cnt +1;`
427			`err_cur_cnt = err_cur_cnt +1;`
428			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);`
429			`end`
430
431			`if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )`
432			`begin`
433			`err_tot_cnt = err_tot_cnt +1;`
434			`err_cur_cnt = err_cur_cnt +1;`
435			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);`
436			`end`
437
438			`if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )`
439			`begin`
440			`err_tot_cnt = err_tot_cnt +1;`
441			`err_cur_cnt = err_cur_cnt +1;`
442			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);`
443			`end`
444
445			`if( (d_exp !== q) & s == 4'b1111 )`
446			`begin`
447			`err_tot_cnt = err_tot_cnt +1;`
448			`err_cur_cnt = err_cur_cnt +1;`
449			`$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);`
450			`end`
451
452			`case( s )`
453			`4'b0001: ;`
454			`4'b0010: ;`
455			`4'b0100: ;`
456			`4'b1000: ;`
457			`4'b0011: ;`
458			`4'b1100: ;`
459			`4'b1111: ;`
460			`default: $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );`
461			`endcase`
462
463
464			`if (err_tot_cnt > err_watchdog)`
465			`begin`
466			`$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);`
467			`$stop;`
468			`end`
469			`end`
470			`endtask`
471
472
473			`////////////////////////////`
474			`//`
475			`// Error counter handlers`
476			`//`
477			`task set_cur_err_cnt;`
478			`input value;`
479			`begin`
480			`err_cur_cnt = value;`
481			`end`
482			`endtask`
483
484			`task show_cur_err_cnt;`
485			`$display("\nCurrent errors detected: %d\n", err_cur_cnt);`
486			`endtask`
487
488			`task show_tot_err_cnt;`
489			`$display("\nTotal errors detected: %d\n", err_tot_cnt);`
490			`endtask`
491
492
493			`always @(posedge clk)`
494			`if( err & (cyc == 1'b1) & (stb == 1'b1) )`
495			`$display( "!!!- WB Bus Error at time %t. ", $time );`
496
497			`endmodule`
498