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[/] [wb_size_bridge/] [trunk/] [tb/] [models/] [wb_slave_model.v] - Blame information for rev 2

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module wb_slave_model(  clk_i, rst_i, dat_o, dat_i, adr_i,
                        cyc_i, stb_i, we_i, sel_i,
                        ack_o, err_o, rty_o );
 
  parameter DWIDTH    = 8;
  parameter AWIDTH    = 8;
  parameter ACK_DELAY = 2;
  parameter SLAVE_RAM_INIT = "wb_slave_model.txt";
 
  input                         clk_i;
  input                         rst_i;
  output [DWIDTH-1:0]           dat_o;
  input  [DWIDTH-1:0]           dat_i;
  input  [AWIDTH-1:0]           adr_i;
  input                         cyc_i;
  input                         stb_i;
  input                         we_i;
  input  [( (DWIDTH/8) - 1 ):0] sel_i;
  output                        ack_o;
  output                        err_o;
  output                        rty_o;
 
 
 
 
 
  // --------------------------------------------------------------------
  //  slave ram
  reg [7:0] ram[2**AWIDTH-1:0];
 
  initial
    $readmemh( SLAVE_RAM_INIT, ram );
 
  // --------------------------------------------------------------------
  //  
  generate
    case( DWIDTH )
      8:        begin
                  initial
                    $display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );
 
                  always @ (posedge clk_i)
                    if (we_i & cyc_i & stb_i & sel_i[0])
                      ram[adr_i] <= dat_i[7:0];
 
                  assign dat_o = ram[adr_i];
 
                end
 
      16:       begin
                  initial
                    $display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );
 
                  always @ (posedge clk_i)
                    if (we_i & cyc_i & stb_i & sel_i[0])
                      ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];
 
                  always @ (posedge clk_i)
                    if (we_i & cyc_i & stb_i & sel_i[1])
                      ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];
 
                  assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };
 
                end
 
      32:       begin
                  initial
                    begin
                      $display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
                      $display( "###- wb_slave_model(): Not yet supported " );
                      $stop();
                    end
                end
 
      default:  begin
                  localparam SLAVE_SIZE = -1;
                  initial
                    begin
                      $display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );
                      $stop();
                    end
                end
    endcase
  endgenerate
 
 
  // --------------------------------------------------------------------
  //  ack delay
  reg ack_delayed;
 
  initial
    ack_delayed = 1'b0;
 
  always @(posedge clk_i or cyc_i or stb_i)
    begin
      if(cyc_i & stb_i)
        begin
          ack_delayed = 1'b0;
          repeat(ACK_DELAY) @(posedge clk_i);
          if(cyc_i & stb_i)
            ack_delayed = 1'b1;
          else
            ack_delayed = 1'b0;
        end
      else
        ack_delayed = 1'b0;
    end
 
  // --------------------------------------------------------------------
  //  assign outputs  
  assign ack_o = ack_delayed;
  assign err_o = 1'b0;
  assign rty_o = 1'b0;
 
 
endmodule

Line No.	Rev	Author	Line
1	2	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5			`timescale 1ns/10ps
6
7
8			`module wb_slave_model( clk_i, rst_i, dat_o, dat_i, adr_i,`
9			`cyc_i, stb_i, we_i, sel_i,`
10			`ack_o, err_o, rty_o );`
11
12			`parameter DWIDTH = 8;`
13			`parameter AWIDTH = 8;`
14			`parameter ACK_DELAY = 2;`
15			`parameter SLAVE_RAM_INIT = "wb_slave_model.txt";`
16
17			`input clk_i;`
18			`input rst_i;`
19			`output [DWIDTH-1:0] dat_o;`
20			`input [DWIDTH-1:0] dat_i;`
21			`input [AWIDTH-1:0] adr_i;`
22			`input cyc_i;`
23			`input stb_i;`
24			`input we_i;`
25			`input [( (DWIDTH/8) - 1 ):0] sel_i;`
26			`output ack_o;`
27			`output err_o;`
28			`output rty_o;`
29
30
31
32
33
34			`// --------------------------------------------------------------------`
35			`// slave ram`
36			`reg [7:0] ram[2**AWIDTH-1:0];`
37
38			`initial`
39			`$readmemh( SLAVE_RAM_INIT, ram );`
40
41			`// --------------------------------------------------------------------`
42			`//`
43			`generate`
44			`case( DWIDTH )`
45			`8: begin`
46			`initial`
47			`$display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );`
48
49			`always @ (posedge clk_i)`
50			`if (we_i & cyc_i & stb_i & sel_i[0])`
51			`ram[adr_i] <= dat_i[7:0];`
52
53			`assign dat_o = ram[adr_i];`
54
55			`end`
56
57			`16: begin`
58			`initial`
59			`$display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );`
60
61			`always @ (posedge clk_i)`
62			`if (we_i & cyc_i & stb_i & sel_i[0])`
63			`ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];`
64
65			`always @ (posedge clk_i)`
66			`if (we_i & cyc_i & stb_i & sel_i[1])`
67			`ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];`
68
69			`assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };`
70
71			`end`
72
73			`32: begin`
74			`initial`
75			`begin`
76			`$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );`
77			`$display( "###- wb_slave_model(): Not yet supported " );`
78			`$stop();`
79			`end`
80			`end`
81
82			`default: begin`
83			`localparam SLAVE_SIZE = -1;`
84			`initial`
85			`begin`
86			`$display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );`
87			`$stop();`
88			`end`
89			`end`
90			`endcase`
91			`endgenerate`
92
93
94			`// --------------------------------------------------------------------`
95			`// ack delay`
96			`reg ack_delayed;`
97
98			`initial`
99			`ack_delayed = 1'b0;`
100
101			`always @(posedge clk_i or cyc_i or stb_i)`
102			`begin`
103			`if(cyc_i & stb_i)`
104			`begin`
105			`ack_delayed = 1'b0;`
106			`repeat(ACK_DELAY) @(posedge clk_i);`
107			`if(cyc_i & stb_i)`
108			`ack_delayed = 1'b1;`
109			`else`
110			`ack_delayed = 1'b0;`
111			`end`
112			`else`
113			`ack_delayed = 1'b0;`
114			`end`
115
116			`// --------------------------------------------------------------------`
117			`// assign outputs`
118			`assign ack_o = ack_delayed;`
119			`assign err_o = 1'b0;`
120			`assign rty_o = 1'b0;`
121
122
123			`endmodule`

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[/] [wb_size_bridge/] [trunk/] [tb/] [models/] [wb_slave_model.v] - Blame information for rev 2