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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/10ps
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module tb_dut(
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input tb_clk,
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input tb_rst
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);
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wire wb_hi_clk = tb_clk;
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wire wb_hi_rst = tb_rst;
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wire [31:0] wb_hi_dat_i, wb_hi_dat_o;
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wire [31:0] wb_hi_adr_o;
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wire wb_hi_cyc_o, wb_hi_stb_o;
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wire wb_hi_we_o;
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wire [ 3:0] wb_hi_sel_o;
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wire wb_hi_ack_i, wb_hi_err_i, wb_hi_rty_i;
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wire wb_lo_clk_o;
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wire wb_lo_rst_o;
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wire [15:0] wb_lo_dat_i, wb_lo_dat_o;
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wire [31:0] wb_lo_adr_o;
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wire wb_lo_cyc_o, wb_lo_stb_o;
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wire wb_lo_we_o;
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wire [1:0] wb_lo_sel_o;
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wire wb_lo_ack_i, wb_lo_err_i, wb_lo_rty_i;
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wire lo_byte_if_i;
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// --------------------------------------------------------------------
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// wb_hi_master_model
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wb_master_model wbm(
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.clk(wb_hi_clk),
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.rst(wb_hi_rst),
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.adr(wb_hi_adr_o),
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.din(wb_hi_dat_i),
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.dout(wb_hi_dat_o),
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.cyc(wb_hi_cyc_o),
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.stb(wb_hi_stb_o),
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.we(wb_hi_we_o),
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.sel(wb_hi_sel_o),
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.ack(wb_hi_ack_i),
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.err(wb_hi_err_i),
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.rty(wb_hi_rty_i)
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);
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// --------------------------------------------------------------------
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// wb_hi_size_bridge
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wb_size_bridge i_wb_size_bridge(
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.wb_hi_clk_i(wb_hi_clk),
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.wb_hi_rst_i(wb_hi_rst),
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.wb_hi_dat_o(wb_hi_dat_i),
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.wb_hi_dat_i(wb_hi_dat_o),
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.wb_hi_adr_i(wb_hi_adr_o),
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.wb_hi_cyc_i(wb_hi_cyc_o),
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.wb_hi_we_i(wb_hi_we_o),
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.wb_hi_stb_i(wb_hi_stb_o),
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.wb_hi_sel_i(wb_hi_sel_o),
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.wb_hi_ack_o(wb_hi_ack_i),
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.wb_hi_err_o(wb_hi_err_i),
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.wb_hi_rty_o(wb_hi_rty_i),
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.wb_lo_clk_o(wb_lo_clk_o),
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.wb_lo_rst_o(wb_lo_rst_o),
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.wb_lo_dat_o(wb_lo_dat_o),
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.wb_lo_dat_i(wb_lo_dat_i),
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.wb_lo_adr_o(wb_lo_adr_o),
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.wb_lo_cyc_o(wb_lo_cyc_o),
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.wb_lo_we_o(wb_lo_we_o),
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.wb_lo_stb_o(wb_lo_stb_o),
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.wb_lo_sel_o(wb_lo_sel_o),
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.wb_lo_ack_i(wb_lo_ack_i),
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.wb_lo_err_i(wb_lo_err_i),
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.wb_lo_rty_i(wb_lo_rty_i),
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.lo_byte_if_i(lo_byte_if_i)
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);
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// --------------------------------------------------------------------
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// wb_slave_model
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wire slave_08_bit_hit = (wb_lo_adr_o[31:24] == 8'h60) & wb_lo_cyc_o;
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wire [15:0] slave_08_bit_dat_o;
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wire [15:0] slave_16_bit_dat_o;
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assign wb_lo_dat_i[15:0] = slave_08_bit_hit ? slave_08_bit_dat_o : slave_16_bit_dat_o;
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wire slave_08_bit_ack_o;
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wire slave_08_bit_err_o;
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wire slave_08_bit_rty_o;
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wire slave_16_bit_ack_o;
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wire slave_16_bit_err_o;
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wire slave_16_bit_rty_o;
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assign wb_lo_ack_i = slave_08_bit_hit ? slave_08_bit_ack_o : slave_16_bit_ack_o;
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assign wb_lo_err_i = slave_08_bit_hit ? slave_08_bit_err_o : slave_16_bit_err_o;
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assign wb_lo_rty_i = slave_08_bit_hit ? slave_08_bit_rty_o : slave_16_bit_rty_o;
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wire slave_08_bit_cyc_i = wb_lo_cyc_o & slave_08_bit_hit;
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wire slave_08_bit_stb_i = wb_lo_stb_o & slave_08_bit_hit;
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wire slave_16_bit_cyc_i = wb_lo_cyc_o & ~slave_08_bit_hit;
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wire slave_16_bit_stb_i = wb_lo_stb_o & ~slave_08_bit_hit;
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assign lo_byte_if_i = slave_08_bit_hit;
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wb_slave_model #(.DWIDTH(8), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_08_bit.txt") )
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wb_slave_08_bit(
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.clk_i(wb_lo_clk_o),
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.rst_i(wb_lo_rst_o),
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.dat_o(slave_08_bit_dat_o[7:0]),
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.dat_i(wb_lo_dat_o[7:0]),
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.adr_i(wb_lo_adr_o[4:0]),
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.cyc_i(slave_08_bit_cyc_i),
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.stb_i(slave_08_bit_stb_i),
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.we_i(wb_lo_we_o),
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.sel_i(wb_lo_sel_o[0]),
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.ack_o(slave_08_bit_ack_o),
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.err_o(slave_08_bit_err_o),
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.rty_o(slave_08_bit_rty_o)
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);
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wb_slave_model #(.DWIDTH(16), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_16_bit.txt") )
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wb_slave_16_bit(
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.clk_i(wb_lo_clk_o),
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.rst_i(wb_lo_rst_o),
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.dat_o(slave_16_bit_dat_o),
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.dat_i(wb_lo_dat_o[15:0]),
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.adr_i(wb_lo_adr_o[4:0]),
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.cyc_i(slave_16_bit_cyc_i),
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.stb_i(slave_16_bit_stb_i),
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.we_i(wb_lo_we_o),
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.sel_i(wb_lo_sel_o),
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.ack_o(slave_16_bit_ack_o),
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.err_o(slave_16_bit_err_o),
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.rty_o(slave_16_bit_rty_o)
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);
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endmodule
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