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[/] [wb_tk/] [trunk/] [TestBench/] [wb_async_master_TB.vhd] - Blame information for rev 7

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library WB_TK;
use WB_TK.components.ALL;
 
entity wb_async_master_TB is
    generic (
        dat_width: positive := 8;
        adr_width: positive := 8;
        ab_rd_delay: positive := 2
    );
end wb_async_master_TB;
 
architecture xilinx of wb_async_master_TB is
    component wb_async_master_2
        generic (
            dat_width: positive := dat_width;
            adr_width: positive := adr_width;
            ab_rd_delay: positive := ab_rd_delay
        );
        port (
            wb_clk_i: in std_logic;
            wb_rst_i: in std_logic := '0';
 
            -- interface to wb slave devices
            wb_adr_o: out std_logic_vector (adr_width-1 downto 0);
            wb_sel_o: out std_logic_vector ((dat_width/8)-1 downto 0);
            wb_dat_i: in std_logic_vector (dat_width-1 downto 0);
            wb_dat_o: out std_logic_vector (dat_width-1 downto 0);
            wb_cyc_o: out std_logic;
            wb_ack_i: in std_logic;
            wb_err_i: in std_logic := '-';
            wb_rty_i: in std_logic := '-';
            wb_we_o: out std_logic;
            wb_stb_o: out std_logic;
 
            -- interface to the asyncronous master device
            ab_dat: inout std_logic_vector (dat_width-1 downto 0) := (others => 'Z');
            ab_adr: in std_logic_vector (adr_width-1 downto 0) := (others => 'U');
            ab_rd_n: in std_logic := '1';
            ab_wr_n: in std_logic := '1';
            ab_ce_n: in std_logic := '1';
            ab_byteen_n: in std_logic_vector ((dat_width/8)-1 downto 0);
            ab_wait_n: out std_logic; -- wait-state request 'open-drain' output
            ab_waiths: out std_logic  -- handshake-type totem-pole output
        );
    end component;
 
    signal wb_clk_i: std_logic;
    signal wb_rst_i: std_logic := '0';
 
    -- interface to wb slave devices
    signal wb_adr_o: std_logic_vector (adr_width-1 downto 0);
    signal wb_sel_o: std_logic_vector ((dat_width/8)-1 downto 0);
    signal wb_dat_i: std_logic_vector (dat_width-1 downto 0);
    signal wb_dat_o: std_logic_vector (dat_width-1 downto 0);
    signal wb_cyc_o: std_logic;
    signal wb_ack_i: std_logic;
    signal wb_err_i: std_logic := '-';
    signal wb_rty_i: std_logic := '-';
    signal wb_we_o: std_logic;
    signal wb_stb_o: std_logic;
 
    -- interface to asyncron master device
    signal ab_dat: std_logic_vector (dat_width-1 downto 0) := (others => 'Z');
    signal ab_adr: std_logic_vector (adr_width-1 downto 0) := (others => 'U');
    signal ab_rd_n: std_logic := '1';
    signal ab_wr_n: std_logic := '1';
    signal ab_ce_n: std_logic := '1';
    signal ab_byteen_n: std_logic_vector ((dat_width/8)-1 downto 0);
    signal ab_wait_n: std_logic;
    signal ab_waiths: std_logic;
    signal wait_mode: integer := 0;
    signal ab_wait: std_logic;
 
    procedure wait_for_cycle_end(
        signal ab_wait: in std_logic;
        wait_mode: in integer
    ) is begin
        if wait_mode = 0 then
            if ab_wait = '0' then
                wait until ab_wait /= '0';
            end if;
        elsif wait_mode = 1 then
            if ab_wait = '0' then
                wait until ab_wait = '1';
            end if;
        else
        end if;
    end wait_for_cycle_end;
 
    procedure wait_for_idle(
        signal ab_wait: in std_logic;
        wait_mode: in integer
    ) is begin
        if wait_mode = 0 then
            -- nothing to do in this case
        else
            if ab_wait = '1' then
                wait until ab_wait = '0';
            end if;
        end if;
    end wait_for_idle;
 
    procedure do_write(
        signal as_dat: inout std_logic_vector (dat_width-1 downto 0);
        signal as_adr: out std_logic_vector (adr_width-1 downto 0);
        signal as_rd_n: out std_logic;
        signal as_wr_n: out std_logic;
        signal as_ce_n: out std_logic;
        signal as_byteen_n: out std_logic_vector ((dat_width/8)-1 downto 0);
        signal as_wait: in std_logic;
 
        a_dat: in std_logic_vector(dat_width-1 downto 0);
        a_adr: in std_logic_vector(adr_width-1 downto 0);
        a_cycle_length: in time;
        a_setup_time: in time;
        a_wait_mode: in integer
    ) is begin
        wait_for_idle(as_wait,a_wait_mode);
        as_dat <= (others => 'X');
        as_adr <= (others => 'X');
        as_byteen_n <= (others => 'X');
        as_rd_n <= '1';
        as_wr_n <= '0';
        as_ce_n <= '0';
        wait for a_setup_time;
        as_dat <= a_dat;
        as_adr <= a_adr;
        as_byteen_n <= (others => '0');
        wait for a_cycle_length-a_setup_time;
        wait_for_cycle_end(as_wait,a_wait_mode);
        as_dat <= (others => 'Z');
        as_adr <= (others => 'U');
        as_byteen_n <= (others => 'U');
        as_rd_n <= '1';
        as_wr_n <= '1';
        as_ce_n <= '1';
    end do_write;
 
    procedure do_read(
        signal as_dat: inout std_logic_vector (dat_width-1 downto 0);
        signal as_adr: out std_logic_vector (adr_width-1 downto 0);
        signal as_rd_n: out std_logic;
        signal as_wr_n: out std_logic;
        signal as_ce_n: out std_logic;
        signal as_byteen_n: out std_logic_vector ((dat_width/8)-1 downto 0);
        signal as_wait: in std_logic;
 
        a_expected_dat: in std_logic_vector(dat_width-1 downto 0);
        a_adr: in std_logic_vector(adr_width-1 downto 0);
        a_cycle_length: in time;
        a_setup_time: in time;
        a_wait_mode: in integer
    ) is begin
        wait_for_idle(as_wait,a_wait_mode);
        as_dat <= "ZZZZZZZZ";
        as_adr <= (others => 'X');
        as_byteen_n <= (others => 'X');
        as_rd_n <= '0';
        as_wr_n <= '1';
        as_ce_n <= '0';
        wait for a_setup_time;
        as_adr <= a_adr;
        as_byteen_n <= (others => '0');
        wait for a_cycle_length-a_setup_time;
        wait_for_cycle_end(as_wait,a_wait_mode);
        for i in ab_dat'RANGE loop
            ASSERT (as_dat(i) = a_expected_dat(i)) report "Cannot read back data from bus!" severity error;
        end loop;
        wait for 12 ns;
        as_dat <= (others => 'Z');
        as_adr <= (others => 'U');
        as_byteen_n <= (others => 'U');
        as_rd_n <= '1';
        as_wr_n <= '1';
        as_ce_n <= '1';
    end do_read;
begin
    ab_wait <= ab_wait_n when wait_mode = 0 else ab_waiths;
 
    clk_gen: process
    begin
        wb_clk_i <= '1';
        wait for 25 ns;
        wb_clk_i <= '0';
        wait for 25 ns;
    end process;
 
    reset_gen: process
    begin
        wb_rst_i <= '1';
        wait for 100 ns;
        wb_rst_i <= '0';
                         wait;
    end process;
 
    ss_slave: process
    begin
        if wb_rst_i = '1' then
            wb_err_i <= '0';
            wb_rty_i <= '0';
            wb_ack_i <= '0';
            wb_dat_i <= (others => 'U');
        end if;
        wait until wb_clk_i'EVENT and wb_clk_i = '1';
        if wb_cyc_o = '1' then
            if wb_we_o = '1' then
                -- write cycle
                -- simulate 2 WS
                wb_ack_i <= '0';
                wb_dat_i <= (others => 'U');
                wait until wb_clk_i'EVENT and wb_clk_i = '1';
                wait until wb_clk_i'EVENT and wb_clk_i = '1';
                wb_ack_i <= '1';
                wait until wb_clk_i'EVENT and wb_clk_i = '1';
                wb_ack_i <= '0';
            else
                -- read cycle
                -- simulate 3 WS
                wb_dat_i <= (others => 'U');
                wb_ack_i <= '0';
                wait until wb_clk_i'EVENT and wb_clk_i = '1';
                wait until wb_clk_i'EVENT and wb_clk_i = '1';
                wait until wb_clk_i'EVENT and wb_clk_i = '1';
                wb_ack_i <= '1';
                wb_dat_i <= wb_adr_o(wb_dat_i'RANGE);
                wait until wb_clk_i'EVENT and wb_clk_i = '1';
                wb_dat_i <= (others => 'U');
                wb_ack_i <= '0';
            end if;
        end if;
    end process;
 
    as_master: process
    begin
        if (wb_rst_i = '1') then
            ab_adr <= (others => '0');
            ab_dat <= (others => 'Z');
            ab_rd_n <= '1';
            ab_wr_n <= '1';
            ab_ce_n <= '1';
            wait until wb_rst_i = '0';
        end if;
        wait for 210 ns;
 
        -- test1: normal write
        do_write(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "10000001",
            "01000001",
            202 ns,
            55 ns,
            wait_mode
        );
 
        wait for 300 ns;
 
        -- test2: normal read
        do_read(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "00000010",
            "00000010",
            202 ns,
            55 ns,
            wait_mode
        );
 
        wait for 55 ns;
 
        -- test3: normal write
        do_write(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "10010001",
            "01010001",
            402 ns,
            55 ns,
            wait_mode
        );
 
        wait for 300 ns;
 
        -- test4: normal read
        do_read(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "00010010",
            "00010010",
            502 ns,
            55 ns,
            wait_mode
        );
 
        wait for 55 ns;
 
        -- test5: normal write
        do_write(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "10000011",
            "01000011",
            202 ns,
            55 ns,
            wait_mode
        );
 
        wait for 55 ns;
        -- test4: overlapped read: should wait until posted write finishes
        do_read(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "00000100",
            "00000100",
            202 ns,
            55 ns,
            wait_mode
        );
 
        wait for 5 ns;
        -- test4: out-of-order read: should handled correctly without loosing sync
        do_read(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "00000100",
            "00000100",
            85 ns,
            55 ns,
            wait_mode
        );
        wait for 5 ns;
        -- test4: out-of-order read: should handled correctly without loosing sync
        do_read(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "00000100",
            "00000100",
            85 ns,
            55 ns,
            2 --wait_mode
        );
--        wait for 200 ns;
--        do_read(
--            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
--        
--            "00000100",
--            "00000100",
--            202 ns,
--            55 ns,
--            wait_mode
--        );
 
        wait for 200 ns;
 
        -- test5: normal write
        do_write(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "10000101",
            "01000101",
            202 ns,
            55 ns,
            wait_mode
        );
 
        wait for 55 ns;
        -- test5: overlapped write: should wait until posted write finishes
        do_write(
            ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,
 
            "10000110",
            "01000110",
            202 ns,
            55 ns,
            wait_mode
        );
 
        if wait_mode = 0 then
            wait for 450 ns;
            wait_mode <= 1;
            wait for 50 ns;
        else
            wait;
        end if;
    end process;
 
    UUT: wb_async_master_2
        port map (
            wb_clk_i   =>     wb_clk_i,
            wb_rst_i   =>     wb_rst_i,
 
            -- interfaceto wb slave devices
            wb_adr_o =>     wb_adr_o,
            wb_sel_o =>     wb_sel_o,
            wb_dat_i =>     wb_dat_i,
            wb_dat_o =>     wb_dat_o,
            wb_cyc_o =>     wb_cyc_o,
            wb_ack_i =>     wb_ack_i,
            wb_err_i =>     wb_err_i,
            wb_rty_i =>     wb_rty_i,
            wb_we_o  =>     wb_we_o,
            wb_stb_o =>     wb_stb_o,
 
            -- interfaceto asyncron master device
            ab_dat   =>     ab_dat,
            ab_adr   =>     ab_adr,
            ab_rd_n  =>     ab_rd_n,
            ab_wr_n  =>     ab_wr_n,
            ab_ce_n  =>     ab_ce_n,
            ab_byteen_n =>  ab_byteen_n,
            ab_wait_n   =>  ab_wait_n,
            ab_waiths   =>  ab_waiths
    );
end xilinx;
 

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Subversion Repositories wb_tk

[/] [wb_tk/] [trunk/] [TestBench/] [wb_async_master_TB.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	6	tantos	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`library WB_TK;`
7			`use WB_TK.components.ALL;`
8
9			`entity wb_async_master_TB is`
10			`generic (`
11			`dat_width: positive := 8;`
12			`adr_width: positive := 8;`
13			`ab_rd_delay: positive := 2`
14			`);`
15			`end wb_async_master_TB;`
16
17			`architecture xilinx of wb_async_master_TB is`
18			`component wb_async_master_2`
19			`generic (`
20			`dat_width: positive := dat_width;`
21			`adr_width: positive := adr_width;`
22			`ab_rd_delay: positive := ab_rd_delay`
23			`);`
24			`port (`
25			`wb_clk_i: in std_logic;`
26			`wb_rst_i: in std_logic := '0';`
27
28			`-- interface to wb slave devices`
29			`wb_adr_o: out std_logic_vector (adr_width-1 downto 0);`
30			`wb_sel_o: out std_logic_vector ((dat_width/8)-1 downto 0);`
31			`wb_dat_i: in std_logic_vector (dat_width-1 downto 0);`
32			`wb_dat_o: out std_logic_vector (dat_width-1 downto 0);`
33			`wb_cyc_o: out std_logic;`
34			`wb_ack_i: in std_logic;`
35			`wb_err_i: in std_logic := '-';`
36			`wb_rty_i: in std_logic := '-';`
37			`wb_we_o: out std_logic;`
38			`wb_stb_o: out std_logic;`
39
40			`-- interface to the asyncronous master device`
41			`ab_dat: inout std_logic_vector (dat_width-1 downto 0) := (others => 'Z');`
42			`ab_adr: in std_logic_vector (adr_width-1 downto 0) := (others => 'U');`
43			`ab_rd_n: in std_logic := '1';`
44			`ab_wr_n: in std_logic := '1';`
45			`ab_ce_n: in std_logic := '1';`
46			`ab_byteen_n: in std_logic_vector ((dat_width/8)-1 downto 0);`
47			`ab_wait_n: out std_logic; -- wait-state request 'open-drain' output`
48			`ab_waiths: out std_logic -- handshake-type totem-pole output`
49			`);`
50			`end component;`
51
52			`signal wb_clk_i: std_logic;`
53			`signal wb_rst_i: std_logic := '0';`
54
55			`-- interface to wb slave devices`
56			`signal wb_adr_o: std_logic_vector (adr_width-1 downto 0);`
57			`signal wb_sel_o: std_logic_vector ((dat_width/8)-1 downto 0);`
58			`signal wb_dat_i: std_logic_vector (dat_width-1 downto 0);`
59			`signal wb_dat_o: std_logic_vector (dat_width-1 downto 0);`
60			`signal wb_cyc_o: std_logic;`
61			`signal wb_ack_i: std_logic;`
62			`signal wb_err_i: std_logic := '-';`
63			`signal wb_rty_i: std_logic := '-';`
64			`signal wb_we_o: std_logic;`
65			`signal wb_stb_o: std_logic;`
66
67			`-- interface to asyncron master device`
68			`signal ab_dat: std_logic_vector (dat_width-1 downto 0) := (others => 'Z');`
69			`signal ab_adr: std_logic_vector (adr_width-1 downto 0) := (others => 'U');`
70			`signal ab_rd_n: std_logic := '1';`
71			`signal ab_wr_n: std_logic := '1';`
72			`signal ab_ce_n: std_logic := '1';`
73			`signal ab_byteen_n: std_logic_vector ((dat_width/8)-1 downto 0);`
74			`signal ab_wait_n: std_logic;`
75			`signal ab_waiths: std_logic;`
76			`signal wait_mode: integer := 0;`
77			`signal ab_wait: std_logic;`
78
79			`procedure wait_for_cycle_end(`
80			`signal ab_wait: in std_logic;`
81			`wait_mode: in integer`
82			`) is begin`
83			`if wait_mode = 0 then`
84			`if ab_wait = '0' then`
85			`wait until ab_wait /= '0';`
86			`end if;`
87			`elsif wait_mode = 1 then`
88			`if ab_wait = '0' then`
89			`wait until ab_wait = '1';`
90			`end if;`
91			`else`
92			`end if;`
93			`end wait_for_cycle_end;`
94
95			`procedure wait_for_idle(`
96			`signal ab_wait: in std_logic;`
97			`wait_mode: in integer`
98			`) is begin`
99			`if wait_mode = 0 then`
100			`-- nothing to do in this case`
101			`else`
102			`if ab_wait = '1' then`
103			`wait until ab_wait = '0';`
104			`end if;`
105			`end if;`
106			`end wait_for_idle;`
107
108			`procedure do_write(`
109			`signal as_dat: inout std_logic_vector (dat_width-1 downto 0);`
110			`signal as_adr: out std_logic_vector (adr_width-1 downto 0);`
111			`signal as_rd_n: out std_logic;`
112			`signal as_wr_n: out std_logic;`
113			`signal as_ce_n: out std_logic;`
114			`signal as_byteen_n: out std_logic_vector ((dat_width/8)-1 downto 0);`
115			`signal as_wait: in std_logic;`
116
117			`a_dat: in std_logic_vector(dat_width-1 downto 0);`
118			`a_adr: in std_logic_vector(adr_width-1 downto 0);`
119			`a_cycle_length: in time;`
120			`a_setup_time: in time;`
121			`a_wait_mode: in integer`
122			`) is begin`
123			`wait_for_idle(as_wait,a_wait_mode);`
124			`as_dat <= (others => 'X');`
125			`as_adr <= (others => 'X');`
126			`as_byteen_n <= (others => 'X');`
127			`as_rd_n <= '1';`
128			`as_wr_n <= '0';`
129			`as_ce_n <= '0';`
130			`wait for a_setup_time;`
131			`as_dat <= a_dat;`
132			`as_adr <= a_adr;`
133			`as_byteen_n <= (others => '0');`
134			`wait for a_cycle_length-a_setup_time;`
135			`wait_for_cycle_end(as_wait,a_wait_mode);`
136			`as_dat <= (others => 'Z');`
137			`as_adr <= (others => 'U');`
138			`as_byteen_n <= (others => 'U');`
139			`as_rd_n <= '1';`
140			`as_wr_n <= '1';`
141			`as_ce_n <= '1';`
142			`end do_write;`
143
144			`procedure do_read(`
145			`signal as_dat: inout std_logic_vector (dat_width-1 downto 0);`
146			`signal as_adr: out std_logic_vector (adr_width-1 downto 0);`
147			`signal as_rd_n: out std_logic;`
148			`signal as_wr_n: out std_logic;`
149			`signal as_ce_n: out std_logic;`
150			`signal as_byteen_n: out std_logic_vector ((dat_width/8)-1 downto 0);`
151			`signal as_wait: in std_logic;`
152
153			`a_expected_dat: in std_logic_vector(dat_width-1 downto 0);`
154			`a_adr: in std_logic_vector(adr_width-1 downto 0);`
155			`a_cycle_length: in time;`
156			`a_setup_time: in time;`
157			`a_wait_mode: in integer`
158			`) is begin`
159			`wait_for_idle(as_wait,a_wait_mode);`
160			`as_dat <= "ZZZZZZZZ";`
161			`as_adr <= (others => 'X');`
162			`as_byteen_n <= (others => 'X');`
163			`as_rd_n <= '0';`
164			`as_wr_n <= '1';`
165			`as_ce_n <= '0';`
166			`wait for a_setup_time;`
167			`as_adr <= a_adr;`
168			`as_byteen_n <= (others => '0');`
169			`wait for a_cycle_length-a_setup_time;`
170			`wait_for_cycle_end(as_wait,a_wait_mode);`
171			`for i in ab_dat'RANGE loop`
172			`ASSERT (as_dat(i) = a_expected_dat(i)) report "Cannot read back data from bus!" severity error;`
173			`end loop;`
174			`wait for 12 ns;`
175			`as_dat <= (others => 'Z');`
176			`as_adr <= (others => 'U');`
177			`as_byteen_n <= (others => 'U');`
178			`as_rd_n <= '1';`
179			`as_wr_n <= '1';`
180			`as_ce_n <= '1';`
181			`end do_read;`
182			`begin`
183			`ab_wait <= ab_wait_n when wait_mode = 0 else ab_waiths;`
184
185			`clk_gen: process`
186			`begin`
187			`wb_clk_i <= '1';`
188			`wait for 25 ns;`
189			`wb_clk_i <= '0';`
190			`wait for 25 ns;`
191			`end process;`
192
193			`reset_gen: process`
194			`begin`
195			`wb_rst_i <= '1';`
196			`wait for 100 ns;`
197			`wb_rst_i <= '0';`
198			`wait;`
199			`end process;`
200
201			`ss_slave: process`
202			`begin`
203			`if wb_rst_i = '1' then`
204			`wb_err_i <= '0';`
205			`wb_rty_i <= '0';`
206			`wb_ack_i <= '0';`
207			`wb_dat_i <= (others => 'U');`
208			`end if;`
209			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
210			`if wb_cyc_o = '1' then`
211			`if wb_we_o = '1' then`
212			`-- write cycle`
213			`-- simulate 2 WS`
214			`wb_ack_i <= '0';`
215			`wb_dat_i <= (others => 'U');`
216			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
217			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
218			`wb_ack_i <= '1';`
219			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
220			`wb_ack_i <= '0';`
221			`else`
222			`-- read cycle`
223			`-- simulate 3 WS`
224			`wb_dat_i <= (others => 'U');`
225			`wb_ack_i <= '0';`
226			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
227			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
228			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
229			`wb_ack_i <= '1';`
230			`wb_dat_i <= wb_adr_o(wb_dat_i'RANGE);`
231			`wait until wb_clk_i'EVENT and wb_clk_i = '1';`
232			`wb_dat_i <= (others => 'U');`
233			`wb_ack_i <= '0';`
234			`end if;`
235			`end if;`
236			`end process;`
237
238			`as_master: process`
239			`begin`
240			`if (wb_rst_i = '1') then`
241			`ab_adr <= (others => '0');`
242			`ab_dat <= (others => 'Z');`
243			`ab_rd_n <= '1';`
244			`ab_wr_n <= '1';`
245			`ab_ce_n <= '1';`
246			`wait until wb_rst_i = '0';`
247			`end if;`
248			`wait for 210 ns;`
249
250			`-- test1: normal write`
251			`do_write(`
252			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
253
254			`"10000001",`
255			`"01000001",`
256			`202 ns,`
257			`55 ns,`
258			`wait_mode`
259			`);`
260
261			`wait for 300 ns;`
262
263			`-- test2: normal read`
264			`do_read(`
265			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
266
267			`"00000010",`
268			`"00000010",`
269			`202 ns,`
270			`55 ns,`
271			`wait_mode`
272			`);`
273
274			`wait for 55 ns;`
275
276			`-- test3: normal write`
277			`do_write(`
278			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
279
280			`"10010001",`
281			`"01010001",`
282			`402 ns,`
283			`55 ns,`
284			`wait_mode`
285			`);`
286
287			`wait for 300 ns;`
288
289			`-- test4: normal read`
290			`do_read(`
291			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
292
293			`"00010010",`
294			`"00010010",`
295			`502 ns,`
296			`55 ns,`
297			`wait_mode`
298			`);`
299
300			`wait for 55 ns;`
301
302			`-- test5: normal write`
303			`do_write(`
304			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
305
306			`"10000011",`
307			`"01000011",`
308			`202 ns,`
309			`55 ns,`
310			`wait_mode`
311			`);`
312
313			`wait for 55 ns;`
314			`-- test4: overlapped read: should wait until posted write finishes`
315			`do_read(`
316			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
317
318			`"00000100",`
319			`"00000100",`
320			`202 ns,`
321			`55 ns,`
322			`wait_mode`
323			`);`
324
325			`wait for 5 ns;`
326			`-- test4: out-of-order read: should handled correctly without loosing sync`
327			`do_read(`
328			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
329
330			`"00000100",`
331			`"00000100",`
332			`85 ns,`
333			`55 ns,`
334			`wait_mode`
335			`);`
336			`wait for 5 ns;`
337			`-- test4: out-of-order read: should handled correctly without loosing sync`
338			`do_read(`
339			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
340
341			`"00000100",`
342			`"00000100",`
343			`85 ns,`
344			`55 ns,`
345			`2 --wait_mode`
346			`);`
347			`-- wait for 200 ns;`
348			`-- do_read(`
349			`-- ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
350			`--`
351			`-- "00000100",`
352			`-- "00000100",`
353			`-- 202 ns,`
354			`-- 55 ns,`
355			`-- wait_mode`
356			`-- );`
357
358			`wait for 200 ns;`
359
360			`-- test5: normal write`
361			`do_write(`
362			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
363
364			`"10000101",`
365			`"01000101",`
366			`202 ns,`
367			`55 ns,`
368			`wait_mode`
369			`);`
370
371			`wait for 55 ns;`
372			`-- test5: overlapped write: should wait until posted write finishes`
373			`do_write(`
374			`ab_dat,ab_adr,ab_rd_n,ab_wr_n,ab_ce_n,ab_byteen_n,ab_wait,`
375
376			`"10000110",`
377			`"01000110",`
378			`202 ns,`
379			`55 ns,`
380			`wait_mode`
381			`);`
382
383			`if wait_mode = 0 then`
384			`wait for 450 ns;`
385			`wait_mode <= 1;`
386			`wait for 50 ns;`
387			`else`
388			`wait;`
389			`end if;`
390			`end process;`
391
392			`UUT: wb_async_master_2`
393			`port map (`
394			`wb_clk_i => wb_clk_i,`
395			`wb_rst_i => wb_rst_i,`
396
397			`-- interfaceto wb slave devices`
398			`wb_adr_o => wb_adr_o,`
399			`wb_sel_o => wb_sel_o,`
400			`wb_dat_i => wb_dat_i,`
401			`wb_dat_o => wb_dat_o,`
402			`wb_cyc_o => wb_cyc_o,`
403			`wb_ack_i => wb_ack_i,`
404			`wb_err_i => wb_err_i,`
405			`wb_rty_i => wb_rty_i,`
406			`wb_we_o => wb_we_o,`
407			`wb_stb_o => wb_stb_o,`
408
409			`-- interfaceto asyncron master device`
410			`ab_dat => ab_dat,`
411			`ab_adr => ab_adr,`
412			`ab_rd_n => ab_rd_n,`
413			`ab_wr_n => ab_wr_n,`
414			`ab_ce_n => ab_ce_n,`
415			`ab_byteen_n => ab_byteen_n,`
416			`ab_wait_n => ab_wait_n,`
417			`ab_waiths => ab_waiths`
418			`);`
419			`end xilinx;`
420