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[/] [wb_tk/] [trunk/] [technology.vhd] - Blame information for rev 7

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--
--  Technology mapping library. Interface.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package technology is
        -- originaly in synopsys. Naming convention is changed to resolve potential name conflict.
        function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
        function to_integer(arg:std_logic_vector) return integer;
 
--      function add_one(inp : std_logic_vector) return std_logic_vector;
--      function sub_one(inp : std_logic_vector) return std_logic_vector;
        function is_zero(inp : std_logic_vector) return boolean;
        function sl(l: std_logic_vector; r: integer) return std_logic_vector;
        function sr(l: std_logic_vector; r: integer) return std_logic_vector;
--      function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;
--      function "-"(op_l, op_r: std_logic_vector) return std_logic_vector;
        function log2(inp : integer) return integer;
        function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer;
        function size2bits(inp : integer) return integer;
        function max2(a : integer; b: integer) return integer;
        function min2(a : integer; b: integer) return integer;
        function equ(a : std_logic_vector; b : integer) return boolean;
 
        component d_ff
                port (
                        d  :  in STD_LOGIC;
                        clk:  in STD_LOGIC;
                        ena:  in STD_LOGIC := '1';
                        clr:  in STD_LOGIC := '0';
                        pre:  in STD_LOGIC := '0';
                        q  :  out STD_LOGIC
                );
        end component;
        component spmem
                generic (
                        default_out     : std_logic := 'X';  -- Default output
                        default_content : std_logic := '0';  -- Simple initialization data
                        adr_width       : integer   := 3;
                        dat_width       : integer   := 8;
                        async_read      : boolean   := true
                );
                port (
                        stb_i :     std_logic;                                -- chip select
                        clk_i : in  std_logic;                                -- write clock
                        adr_i : in  std_logic_vector(adr_width -1 downto 0);  -- Address
                        dat_i : in  std_logic_vector(dat_width -1 downto 0);  -- input data
                        dat_o : out std_logic_vector(dat_width -1 downto 0);  -- Output Data
                        we_i  : in  std_logic;                                -- Read Write Enable
                        ack_o : out std_logic                                 -- Ready output
                );
        end component;
        component dpmem
            generic (
                default_out :     std_logic := 'X';  -- Default output
                default_content : std_logic := '0';  -- Simple initialization data
                adr_width   :     integer   := 3;
                dat_width   :     integer   := 8;
                async_read  :     boolean   := true
            );
            port (
                -- Signals for the port A
                a_clk_i : in  std_logic;                                -- Read clock
                a_stb_i : in  std_logic;                                -- Read port select
                a_we_i  : in  std_logic;                                -- Read port Write enable
                a_adr_i : in  std_logic_vector(adr_width -1 downto 0);  -- Read Address
                a_dat_i : in  std_logic_vector(dat_width -1 downto 0);  -- Input data
                a_dat_o : out std_logic_vector(dat_width -1 downto 0);  -- Output data
                a_ack_o : out std_logic;                                -- Read ready output
 
                -- Signals for the port B
                b_clk_i : in  std_logic;                                -- Write clock
                b_stb_i : in  std_logic;                                -- Write port select
                b_we_i  : in  std_logic;                                -- Write Enable
                b_adr_i : in  std_logic_vector(adr_width -1 downto 0);  -- Write Address
                b_dat_i : in  std_logic_vector(dat_width -1 downto 0);  -- Input data
                b_dat_o : out std_logic_vector(dat_width -1 downto 0);  -- Output data
                b_ack_o : out std_logic                                 -- Write ready output
            );
        end component;
        component fifo
                generic (
                        default_out :     std_logic := 'X';  -- Default output
                        default_content : std_logic := '0';  -- Simple initialization data
                        adr_width   :     integer   := 3;
                        dat_width   :     integer   := 8;
                        async_read  :     boolean   := true  -- Controls memory only. For FIFO logic clock is still needed.
                );
                port (
                        reset   : in  std_logic;                              -- System reset
 
                        r_clk_i : in  std_logic;                              -- Read clock
                        r_stb_i : in  std_logic;                              -- Read port select
                        r_we_i  : in  std_logic := '0';                       -- Read port Write enable (should be '0')
                        r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out
                        r_ack_o : out std_logic;                              -- Read ready output
 
                        w_clk_i : in  std_logic;                              -- Write clock
                        w_stb_i : in  std_logic;                              -- Write port select
                        w_we_i  : in  std_logic := '1';                       -- Write port write enable
                        w_dat_i : in  std_logic_vector(dat_width-1 downto 0); -- Data in
                        w_ack_o : out std_logic;                              -- Write ready output
 
                        full_o  : out std_logic;                              -- Full Flag (combinational)
                        empty_o : out std_logic;                              -- Empty flag (combinational)
                        used_o  : out std_logic_vector(adr_width downto 0)    -- number of data in the fifo (combinational)
                );
        end component;
end technology;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity spmem is
        generic (
                default_out     : std_logic := 'X';  -- Default output
                default_content : std_logic := '0';  -- Simple initialization data
                adr_width       : integer   := 3;
                dat_width       : integer   := 8;
                async_read      : boolean   := true
        );
        port (
                stb_i :     std_logic;                                -- chip select
                clk_i : in  std_logic;                                -- write clock
                adr_i : in  std_logic_vector(adr_width -1 downto 0);  -- Address
                dat_i : in  std_logic_vector(dat_width -1 downto 0);  -- input data
                dat_o : out std_logic_vector(dat_width -1 downto 0);  -- Output Data
                we_i  : in  std_logic;                                -- Read Write Enable
                ack_o : out std_logic                                 -- Ready output
        );
end spmem;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity dpmem is
    generic (
        default_out :     std_logic := 'X';  -- Default output
        default_content : std_logic := '0';  -- Simple initialization data
        adr_width   :     integer   := 3;
        dat_width   :     integer   := 8;
        async_read  :     boolean   := true
    );
    port (
        -- Signals for the port A
        a_clk_i : in  std_logic;                                -- Read clock
        a_stb_i : in  std_logic;                                -- Read port select
        a_we_i  : in  std_logic;                                -- Read port Write enable
        a_adr_i : in  std_logic_vector(adr_width -1 downto 0);  -- Read Address
        a_dat_i : in  std_logic_vector(dat_width -1 downto 0);  -- Input data
        a_dat_o : out std_logic_vector(dat_width -1 downto 0);  -- Output data
        a_ack_o : out std_logic;                                -- Read ready output
 
        -- Signals for the port B
        b_clk_i : in  std_logic;                                -- Write clock
        b_stb_i : in  std_logic;                                -- Write port select
        b_we_i  : in  std_logic;                                -- Write Enable
        b_adr_i : in  std_logic_vector(adr_width -1 downto 0);  -- Write Address
        b_dat_i : in  std_logic_vector(dat_width -1 downto 0);  -- Input data
        b_dat_o : out std_logic_vector(dat_width -1 downto 0);  -- Output data
        b_ack_o : out std_logic                                 -- Write ready output
    );
end dpmem;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity fifo is
        generic (
                default_out :     std_logic := 'X';  -- Default output
                default_content : std_logic := '0';  -- Simple initialization data
                adr_width   :     integer   := 3;
                dat_width   :     integer   := 8;
                async_read  :     boolean   := true  -- Controls memory only. For FIFO logic clock is still needed.
        );
        port (
                reset   : in  std_logic;                              -- System reset
 
                r_clk_i : in  std_logic;                              -- Read clock
                r_stb_i : in  std_logic;                              -- Read port select
                r_we_i  : in  std_logic := '0';                       -- Read port Write enable (should be '0')
                r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out
                r_ack_o : out std_logic;                              -- Read ready output
 
                w_clk_i : in  std_logic;                              -- Write clock
                w_stb_i : in  std_logic;                              -- Write port select
                w_we_i  : in  std_logic := '1';                       -- Write port write enable
                w_dat_i : in  std_logic_vector(dat_width-1 downto 0); -- Data in
                w_ack_o : out std_logic;                              -- Write ready output
 
                full_o  : out std_logic;                              -- Full Flag (combinational)
                empty_o : out std_logic;                              -- Empty flag (combinational)
                used_o  : out std_logic_vector(adr_width downto 0)    -- number of data in the fifo (combinational)
        );
end fifo;
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity d_ff is
        port (
                d  :  in STD_LOGIC;
                clk:  in STD_LOGIC;
                ena:  in STD_LOGIC := '1';
                clr:  in STD_LOGIC := '0';
                pre:  in STD_LOGIC := '0';
                q  :  out STD_LOGIC
        );
end d_ff;
 

Line No.	Rev	Author	Line
1	2	tantos	`--`
2	6	tantos	`-- Technology mapping library. Interface.`
3	2	tantos	`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7
8			`library IEEE;`
9			`use IEEE.std_logic_1164.all;`
10
11			`package technology is`
12	6	tantos	`-- originaly in synopsys. Naming convention is changed to resolve potential name conflict.`
13			`function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;`
14			`function to_integer(arg:std_logic_vector) return integer;`
15
16			`-- function add_one(inp : std_logic_vector) return std_logic_vector;`
17			`-- function sub_one(inp : std_logic_vector) return std_logic_vector;`
18	2	tantos	`function is_zero(inp : std_logic_vector) return boolean;`
19	6	tantos	`function sl(l: std_logic_vector; r: integer) return std_logic_vector;`
20			`function sr(l: std_logic_vector; r: integer) return std_logic_vector;`
21			`-- function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;`
22			`-- function "-"(op_l, op_r: std_logic_vector) return std_logic_vector;`
23	4	tantos	`function log2(inp : integer) return integer;`
24	5	tantos	`function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer;`
25	4	tantos	`function size2bits(inp : integer) return integer;`
26	6	tantos	`function max2(a : integer; b: integer) return integer;`
27	5	tantos	`function min2(a : integer; b: integer) return integer;`
28	4	tantos	`function equ(a : std_logic_vector; b : integer) return boolean;`
29	2	tantos
30	6	tantos	`component d_ff`
31			`port (`
32			`d : in STD_LOGIC;`
33			`clk: in STD_LOGIC;`
34			`ena: in STD_LOGIC := '1';`
35			`clr: in STD_LOGIC := '0';`
36			`pre: in STD_LOGIC := '0';`
37			`q : out STD_LOGIC`
38	2	tantos	`);`
39			`end component;`
40	6	tantos	`component spmem`
41			`generic (`
42			`default_out : std_logic := 'X'; -- Default output`
43			`default_content : std_logic := '0'; -- Simple initialization data`
44			`adr_width : integer := 3;`
45			`dat_width : integer := 8;`
46			`async_read : boolean := true`
47	2	tantos	`);`
48	6	tantos	`port (`
49			`stb_i : std_logic; -- chip select`
50			`clk_i : in std_logic; -- write clock`
51			`adr_i : in std_logic_vector(adr_width -1 downto 0); -- Address`
52			`dat_i : in std_logic_vector(dat_width -1 downto 0); -- input data`
53			`dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output Data`
54			`we_i : in std_logic; -- Read Write Enable`
55			`ack_o : out std_logic -- Ready output`
56	2	tantos	`);`
57			`end component;`
58	6	tantos	`component dpmem`
59			`generic (`
60			`default_out : std_logic := 'X'; -- Default output`
61			`default_content : std_logic := '0'; -- Simple initialization data`
62			`adr_width : integer := 3;`
63			`dat_width : integer := 8;`
64			`async_read : boolean := true`
65			`);`
66			`port (`
67			`-- Signals for the port A`
68			`a_clk_i : in std_logic; -- Read clock`
69			`a_stb_i : in std_logic; -- Read port select`
70			`a_we_i : in std_logic; -- Read port Write enable`
71			`a_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Read Address`
72			`a_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data`
73			`a_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data`
74			`a_ack_o : out std_logic; -- Read ready output`
75	2	tantos
76	6	tantos	`-- Signals for the port B`
77			`b_clk_i : in std_logic; -- Write clock`
78			`b_stb_i : in std_logic; -- Write port select`
79			`b_we_i : in std_logic; -- Write Enable`
80			`b_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Write Address`
81			`b_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data`
82			`b_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data`
83			`b_ack_o : out std_logic -- Write ready output`
84			`);`
85			`end component;`
86			`component fifo`
87			`generic (`
88			`default_out : std_logic := 'X'; -- Default output`
89			`default_content : std_logic := '0'; -- Simple initialization data`
90			`adr_width : integer := 3;`
91			`dat_width : integer := 8;`
92			`async_read : boolean := true -- Controls memory only. For FIFO logic clock is still needed.`
93			`);`
94			`port (`
95			`reset : in std_logic; -- System reset`
96	2	tantos
97	6	tantos	`r_clk_i : in std_logic; -- Read clock`
98			`r_stb_i : in std_logic; -- Read port select`
99			`r_we_i : in std_logic := '0'; -- Read port Write enable (should be '0')`
100			`r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out`
101			`r_ack_o : out std_logic; -- Read ready output`
102	2	tantos
103	6	tantos	`w_clk_i : in std_logic; -- Write clock`
104			`w_stb_i : in std_logic; -- Write port select`
105			`w_we_i : in std_logic := '1'; -- Write port write enable`
106			`w_dat_i : in std_logic_vector(dat_width-1 downto 0); -- Data in`
107			`w_ack_o : out std_logic; -- Write ready output`
108	4	tantos
109	6	tantos	`full_o : out std_logic; -- Full Flag (combinational)`
110			`empty_o : out std_logic; -- Empty flag (combinational)`
111			`used_o : out std_logic_vector(adr_width downto 0) -- number of data in the fifo (combinational)`
112			`);`
113	2	tantos	`end component;`
114	6	tantos	`end technology;`
115	2	tantos
116	4	tantos	`library IEEE;`
117			`use IEEE.std_logic_1164.all;`
118	2	tantos
119	6	tantos	`entity spmem is`
120	4	tantos	`generic (`
121	6	tantos	`default_out : std_logic := 'X'; -- Default output`
122			`default_content : std_logic := '0'; -- Simple initialization data`
123			`adr_width : integer := 3;`
124			`dat_width : integer := 8;`
125			`async_read : boolean := true`
126	4	tantos	`);`
127			`port (`
128	6	tantos	`stb_i : std_logic; -- chip select`
129			`clk_i : in std_logic; -- write clock`
130			`adr_i : in std_logic_vector(adr_width -1 downto 0); -- Address`
131			`dat_i : in std_logic_vector(dat_width -1 downto 0); -- input data`
132			`dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output Data`
133			`we_i : in std_logic; -- Read Write Enable`
134			`ack_o : out std_logic -- Ready output`
135	4	tantos	`);`
136	6	tantos	`end spmem;`
137	4	tantos
138	6	tantos	`library IEEE;`
139			`use IEEE.std_logic_1164.all;`
140	4	tantos
141	6	tantos	`entity dpmem is`
142			`generic (`
143			`default_out : std_logic := 'X'; -- Default output`
144			`default_content : std_logic := '0'; -- Simple initialization data`
145			`adr_width : integer := 3;`
146			`dat_width : integer := 8;`
147			`async_read : boolean := true`
148			`);`
149			`port (`
150			`-- Signals for the port A`
151			`a_clk_i : in std_logic; -- Read clock`
152			`a_stb_i : in std_logic; -- Read port select`
153			`a_we_i : in std_logic; -- Read port Write enable`
154			`a_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Read Address`
155			`a_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data`
156			`a_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data`
157			`a_ack_o : out std_logic; -- Read ready output`
158	4	tantos
159	6	tantos	`-- Signals for the port B`
160			`b_clk_i : in std_logic; -- Write clock`
161			`b_stb_i : in std_logic; -- Write port select`
162			`b_we_i : in std_logic; -- Write Enable`
163			`b_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Write Address`
164			`b_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data`
165			`b_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data`
166			`b_ack_o : out std_logic -- Write ready output`
167			`);`
168			`end dpmem;`
169	4	tantos
170	2	tantos	`library IEEE;`
171			`use IEEE.std_logic_1164.all;`
172
173	6	tantos	`entity fifo is`
174	4	tantos	`generic (`
175	6	tantos	`default_out : std_logic := 'X'; -- Default output`
176			`default_content : std_logic := '0'; -- Simple initialization data`
177			`adr_width : integer := 3;`
178			`dat_width : integer := 8;`
179			`async_read : boolean := true -- Controls memory only. For FIFO logic clock is still needed.`
180	4	tantos	`);`
181			`port (`
182	6	tantos	`reset : in std_logic; -- System reset`
183	4	tantos
184	6	tantos	`r_clk_i : in std_logic; -- Read clock`
185			`r_stb_i : in std_logic; -- Read port select`
186			`r_we_i : in std_logic := '0'; -- Read port Write enable (should be '0')`
187			`r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out`
188			`r_ack_o : out std_logic; -- Read ready output`
189	4	tantos
190	6	tantos	`w_clk_i : in std_logic; -- Write clock`
191			`w_stb_i : in std_logic; -- Write port select`
192			`w_we_i : in std_logic := '1'; -- Write port write enable`
193			`w_dat_i : in std_logic_vector(dat_width-1 downto 0); -- Data in`
194			`w_ack_o : out std_logic; -- Write ready output`
195
196			`full_o : out std_logic; -- Full Flag (combinational)`
197			`empty_o : out std_logic; -- Empty flag (combinational)`
198			`used_o : out std_logic_vector(adr_width downto 0) -- number of data in the fifo (combinational)`
199	4	tantos	`);`
200	6	tantos	`end fifo;`
201	4	tantos
202
203			`library IEEE;`
204			`use IEEE.std_logic_1164.all;`
205
206	2	tantos	`entity d_ff is`
207	6	tantos	`port (`
208			`d : in STD_LOGIC;`
209			`clk: in STD_LOGIC;`
210			`ena: in STD_LOGIC := '1';`
211			`clr: in STD_LOGIC := '0';`
212			`pre: in STD_LOGIC := '0';`
213			`q : out STD_LOGIC`
214	2	tantos	`);`
215			`end d_ff;`
216

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[/] [wb_tk/] [trunk/] [technology.vhd] - Blame information for rev 7