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tantos |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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tantos |
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tantos |
entity wb_async_master is
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generic (
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dat_width: positive := 16;
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adr_width: positive := 20;
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ab_rd_delay: positive := 1
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);
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port (
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wb_clk_i: in std_logic;
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wb_rst_i: in std_logic := '0';
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4 |
tantos |
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6 |
tantos |
-- interface to wb slave devices
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wb_adr_o: out std_logic_vector (adr_width-1 downto 0);
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wb_sel_o: out std_logic_vector ((dat_width/8)-1 downto 0);
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wb_dat_i: in std_logic_vector (dat_width-1 downto 0);
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wb_dat_o: out std_logic_vector (dat_width-1 downto 0);
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wb_cyc_o: out std_logic;
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wb_ack_i: in std_logic;
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wb_err_i: in std_logic := '-';
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wb_rty_i: in std_logic := '-';
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wb_we_o: out std_logic;
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wb_stb_o: out std_logic;
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tantos |
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tantos |
-- interface to the asyncronous master device
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ab_dat: inout std_logic_vector (dat_width-1 downto 0) := (others => 'Z');
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ab_adr: in std_logic_vector (adr_width-1 downto 0) := (others => 'U');
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ab_rd_n: in std_logic := '1';
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ab_wr_n: in std_logic := '1';
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ab_ce_n: in std_logic := '1';
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ab_byteen_n: in std_logic_vector ((dat_width/8)-1 downto 0);
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ab_wait_n: out std_logic; -- wait-state request 'open-drain' output
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ab_waiths: out std_logic -- handshake-type totem-pole output
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tantos |
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tantos |
);
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tantos |
end wb_async_master;
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tantos |
architecture xilinx of wb_async_master is
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constant ab_wr_delay: positive := 2;
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-- delay lines for rd/wr edge detection
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signal rd_delay_rst: std_logic;
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signal rd_delay: std_logic_vector(ab_rd_delay downto 0);
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signal wr_delay: std_logic_vector(ab_wr_delay downto 0);
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-- one-cycle long pulses upon rd/wr edges
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signal ab_wr_pulse: std_logic;
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signal ab_rd_pulse: std_logic;
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-- one-cycle long pulse to latch address for writes
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signal ab_wr_latch_pulse: std_logic;
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-- WB data input register
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signal wb_dat_reg: std_logic_vector (dat_width-1 downto 0);
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-- internal copies of WB signals for feedback
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signal wb_cyc_l: std_logic;
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signal wb_we_l: std_logic;
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-- Comb. logic for active cycles
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signal ab_rd: std_logic;
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signal ab_wr: std_logic;
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signal ab_active: std_logic;
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-- internal copies of wait signals for feedback
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signal ab_wait_n_rst: std_logic;
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signal ab_wait_n_l: std_logic;
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signal ab_waiths_l: std_logic;
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signal ab_wait_n_l_delayed: std_logic;
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signal ab_waiths_l_delayed: std_logic;
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-- active when WB slave terminates the cycle (for any reason)
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signal wb_ack: std_logic;
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-- signals a scheduled or commencing posted write
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signal write_in_progress: std_logic;
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tantos |
begin
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tantos |
ab_rd <= (not ab_ce_n) and (not ab_rd_n) and ab_wr_n;
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ab_wr <= (not ab_ce_n) and (not ab_wr_n) and ab_rd_n;
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ab_active <= not ab_ce_n;
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tantos |
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tantos |
wb_ack <= wb_cyc_l and (wb_ack_i or wb_err_i or wb_rty_i);
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tantos |
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tantos |
write_in_progress_gen: process
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begin
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if (wb_rst_i = '1') then
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write_in_progress <= '0';
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end if;
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wait until wb_clk_i'EVENT and wb_clk_i = '1';
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if ab_wr = '0' and wr_delay(wr_delay'HIGH) = '1' then
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write_in_progress <= '1';
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end if;
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if wb_ack = '1' then
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write_in_progress <= '0';
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end if;
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end process;
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tantos |
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tantos |
-- Registers addr/data lines.
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reg_bus_lines: process
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begin
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if (wb_rst_i = '1') then
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wb_adr_o <= (others => '-');
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wb_sel_o <= (others => '-');
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wb_dat_o <= (others => '-');
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wb_dat_reg <= (others => '0');
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end if;
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wait until wb_clk_i'EVENT and wb_clk_i = '1';
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-- Store and sycnronize data and address lines if no (posted) write
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-- is in progress and there is an active asyncronous bus cycle.
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-- We store addresses for reads at the same time we sample the data so setup and hold
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-- times are the same.
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if (ab_wr = '1' or ab_rd_pulse = '1') and (write_in_progress = '0' or wb_ack = '1') then
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wb_adr_o <= ab_adr;
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for i in wb_sel_o'RANGE loop
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wb_sel_o(i) <= not ab_byteen_n(i);
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end loop;
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end if;
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if (ab_wr = '1') and (write_in_progress = '0' or wb_ack = '1') then
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wb_dat_o <= ab_dat;
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end if;
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tantos |
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tantos |
-- en-register data input at the end of a read cycle
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if wb_ack = '1' then
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if wb_we_l = '0' then
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-- read cycle completed, store the result
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wb_dat_reg <= wb_dat_i;
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end if;
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end if;
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end process;
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-- Registers asycn bus control lines for sync edge detection.
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async_bus_wr_ctrl : process(wb_rst_i,wb_clk_i)
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begin
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if (wb_rst_i = '1') then
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wr_delay <= (others => '0');
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-- end if;
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-- Post-layout simulation shows glitches on the output that violates setup times.
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-- Clock on the other edge to solve this issue
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-- elsif wb_clk_i'EVENT and wb_clk_i = '1' then
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elsif wb_clk_i'EVENT and wb_clk_i = '0' then
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-- wait until wb_clk_i'EVENT and wb_clk_i = '1';
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-- wait until wb_clk_i'EVENT and wb_clk_i = '0';
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-- delayed signals will be used in edge-detection
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for i in wr_delay'HIGH downto 1 loop
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wr_delay(i) <= wr_delay(i-1);-- and ab_rd;
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end loop;
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wr_delay(0) <= ab_wr;
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end if;
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end process;
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rd_delay_rst <= wb_rst_i or not ab_rd;
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async_bus_rd_ctrl : process(rd_delay_rst,wb_clk_i)
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begin
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if (rd_delay_rst = '1') then
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rd_delay <= (others => '0');
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-- Post-layout simulation shows glitches on the output that violates setup times.
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-- Clock on the other edge to solve this issue
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-- elsif wb_clk_i'EVENT and wb_clk_i = '1' then
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elsif wb_clk_i'EVENT and wb_clk_i = '0' then
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-- a sync-reset shift-register to delay read signal
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for i in rd_delay'HIGH downto 1 loop
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rd_delay(i) <= rd_delay(i-1) and ab_rd;
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end loop;
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if (wb_cyc_l = '1') then
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rd_delay(0) <= rd_delay(0);
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else
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rd_delay(0) <= ab_rd and not write_in_progress;
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end if;
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end if;
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end process;
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-- will be one for one cycle at the proper end of the async cycle
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ab_wr_pulse <= wr_delay(wr_delay'HIGH) and not wr_delay(wr_delay'HIGH-1);
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ab_wr_latch_pulse <= not wr_delay(wr_delay'HIGH) and wr_delay(wr_delay'HIGH-1);
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ab_rd_pulse <= not rd_delay(rd_delay'HIGH) and rd_delay(rd_delay'HIGH-1);
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-- Generates WishBone control signals
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wb_ctrl_gen: process
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begin
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if (wb_rst_i = '1') then
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wb_stb_o <= '0';
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wb_cyc_l <= '0';
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wb_we_l <= '0';
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end if;
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wait until wb_clk_i'EVENT and wb_clk_i = '1';
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-- if wb_ack = '1' then
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if wb_ack = '1' and ab_wr_pulse = '0' and ab_rd_pulse = '0' then
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wb_stb_o <= '0';
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wb_cyc_l <= '0';
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wb_we_l <= '0';
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end if;
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if ab_wr_pulse = '1' or ab_rd_pulse = '1' then
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wb_stb_o <= '1';
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wb_cyc_l <= '1';
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wb_we_l <= ab_wr_pulse;
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end if;
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end process;
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-- Generate asyncronous wait signal
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ab_wait_n_rst <= wb_rst_i or not ab_active;
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a_wait_n_gen: process(ab_wait_n_rst, wb_clk_i)
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begin
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if (ab_wait_n_rst = '1') then
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ab_wait_n_l <= '1';
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elsif wb_clk_i'EVENT and wb_clk_i = '1' then
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-- At the beginning of a read cycle, move wait low
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if ab_wait_n_l = '1' and ab_rd = '1' and rd_delay(0) = '0' then
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ab_wait_n_l <= '0';
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end if;
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-- At the beginning of any cycle, if the ss-master part is busy, wait
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if (ab_wait_n_l = '1' and (ab_rd = '1' or ab_wr = '1')) and
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(wb_cyc_l = '1')
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then
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ab_wait_n_l <= '0';
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end if;
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-- At the end of an ss-master cycle, remove wait
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if wb_ack = '1' and (
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(wb_we_l = '1' and ab_rd = '0') or -- no pending read
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wb_we_l = '0') -- was a read operation
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then
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ab_wait_n_l <= '1';
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end if;
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end if;
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end process;
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-- Generate handshake-type wait signal
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a_waiths_gen: process(wb_rst_i,wb_clk_i)
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begin
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if (wb_rst_i = '1') then
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ab_waiths_l <= '0';
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elsif wb_clk_i'EVENT and wb_clk_i = '1' then
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-- Write handling
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if wb_cyc_l = '0' and ab_wr = '1' then
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ab_waiths_l <= '1';
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end if;
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if wb_ack = '1' and ab_waiths_l = '1' then
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ab_waiths_l <= '0';
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end if;
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-- Read handling
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if wb_ack = '1' and ab_rd = '1' then
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ab_waiths_l <= '1';
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end if;
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if wb_cyc_l = '0' and ab_rd = '0' and ab_wr = '0' and wr_delay(wr_delay'HIGH) = '0'
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then
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ab_waiths_l <= '0';
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end if;
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end if;
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end process;
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-- connect local signals to external pins
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wb_cyc_o <= wb_cyc_l;
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wb_we_o <= wb_we_l;
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-- ab_wait_n <= '0' when ab_wait_n_l = '0' else '1';
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ab_dat <= wb_dat_reg when ab_rd = '1' else (others => 'Z');
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-- On post-layout simulation it turned out that the data is not stable upon
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-- the raising edge of these wait signals. So we delay the raising edge with one-half clock
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delay_wait: process(wb_clk_i)
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begin
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if wb_clk_i'EVENT and wb_clk_i = '0' then
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ab_wait_n_l_delayed <= ab_wait_n_l;
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ab_waiths_l_delayed <= ab_waiths_l;
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end if;
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end process;
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ab_wait_n <= ab_wait_n_l and ab_wait_n_l_delayed;
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ab_waiths <= ab_waiths_l and ab_waiths_l_delayed;
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-- ab_dat_gen: process(wb_clk_i,wb_rst_i)
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-- begin
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-- if (wb_rst_i = '1') then
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-- ab_dat <= (others => 'Z');
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-- elsif wb_clk_i'EVENT and wb_clk_i = '1' then
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-- if (ab_rd = '1') then
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-- ab_dat <= wb_dat_reg;
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-- else
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-- ab_dat <= (others => 'Z');
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-- end if;
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-- end if;
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-- end process;
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end xilinx;
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