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<!--# include virtual="/ssi/ssi_start.shtml" -->
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<link REL="stylesheet" TYPE="text/css" HREF="/people/tantos/styles.css">
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<h1>WisboneTK</h1>
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<h2>Single-port RAM</h2>
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<h3>Description</h3>
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The <strong>Single-port RAM</strong> is a small, fast, on-chip RAM implementation utilizing the embedded RAM blocks
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available in many FPGA architectures. Although it can be paramerized to arbitrary size and width it won't fit into
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a physical device if larger than a few K-bits. If you need larger memories for your design consider using an
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external memory chip and interfacing it to the Wishbone bus with one of the many interface circuits available.
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Also you can consider using another Wishbone-compatible single- and dual-ported RAM implementation by
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<a href="mailto:khatib@ieee.org_NOSPAM">Jamil Khatib</a> which you can find
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<a href="/cores/memory_cores/">here</a>.
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The core is 100% Wishbone compatible with the <a href="wb_extensions.shtml">WishboneTK extensions</a>.
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The core allows zero-wait-state operation.
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<h3>Wishbone datasheet</h3>
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<table border>
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<tr><th>Description</th><th>Specification</th></tr>
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<tr><td>General Description </td><td>Single-port RAM</td></tr>
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<tr><td>Supported cycles </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw</td></tr>
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<tr><td>Data port size </td><td>variable</td></tr>
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<tr><td>Data port granularity </td><td>same as port size</td></tr>
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<tr><td>Data port maximum operand size </td><td>same as data port size</td></tr>
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<tr><td>Data transfer ordering </td><td>n/a</td></tr>
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<tr><td>Data transfer sequencing </td><td>n/a</td></tr>
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<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>
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<table>
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<tr><th>Signal name</th><th>Wishbone equiv.</th></tr>
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<tr><td>CLK_I </td><td>CLK_I</td></tr>
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<tr><td>CYC_I </td><td>CYC_I</td></tr>
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<tr><td>STB_I </td><td>STB_I</td></tr>
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<tr><td>WE_I </td><td>WE_I </td></tr>
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<tr><td>ACK_O </td><td>ACK_O</td></tr>
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<tr><td>ADR_I(..) </td><td>ADR_I()</td></tr>
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<tr><td>DAT_I(..) </td><td>DAT_I()</td></tr>
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<tr><td>DAT_O(..) </td><td>DAT_O()</td></tr>
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</table>
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</table>
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<h3>Parameter description</h3>
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<table border>
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<tr><th>Parameter name</th><th>Description</th></tr>
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<tr><td>data_width</td><td>Data bus width</td></tr>
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<tr><td>addr_width</td><td>Address bus width</td></tr>
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</table>
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<h3>Signal description</h3>
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<table border>
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<tr><th>Signal name</th><th>Description</th></tr>
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<tr><td>CLK_I </td><td>Wishbone clock signal</td></tr>
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<tr><td>CYC_I </td><td>Wishbone active cycle indication signal. High value indicates an active Wishbone cycle on the bus</td></tr>
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<tr><td>STB_I </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
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<tr><td>WE_I </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
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<tr><td>ACK_O </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
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<tr><td>ACK_OI </td><td>WhisboneTK acknowledge chain input signal</td></tr>
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<tr><td>ADR_I(addr_width-1..0) </td><td>Wishbone address bus signals</td></tr>
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<tr><td>DAT_I(data_width-1..0) </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
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<tr><td>DAT_O(data_width-1..0) </td><td>Wishbone data bus output (to master direction) signals</td></tr>
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<tr><td>DAT_OI(data_width-1..0) </td><td>WhisboneTK data bus chain input signal</td></tr>
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</td></tr></table>
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<h2>Author & Maintainer</h2>
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<p>
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<a href="/people/tantos">Andras Tantos</a>
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