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[/] [wb_uart/] [trunk/] [src/] [uart_transmitter.vhd] - Blame information for rev 7

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1 7 federico.a
--
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-- UART transmitter
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--
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-- Author:   Sebastian Witt
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-- Date:     27.01.2008
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-- Version:  1.0
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--
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the
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-- Free Software  Foundation, Inc., 59 Temple Place, Suite 330,
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-- Boston, MA  02111-1307  USA
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--
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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-- Serial UART transmitter
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entity uart_transmitter is
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    port (
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        CLK         : in std_logic;                             -- Clock
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        RST         : in std_logic;                             -- Reset
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        TXCLK       : in std_logic;                             -- Transmitter clock (2x baudrate)
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        TXSTART     : in std_logic;                             -- Start transmitter
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        CLEAR       : in std_logic;                             -- Clear transmitter state
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        WLS         : in std_logic_vector(1 downto 0);          -- Word length select
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        STB         : in std_logic;                             -- Number of stop bits
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        PEN         : in std_logic;                             -- Parity enable
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        EPS         : in std_logic;                             -- Even parity select
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        SP          : in std_logic;                             -- Stick parity
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        BC          : in std_logic;                             -- Break control
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        DIN         : in std_logic_vector(7 downto 0);          -- Input data
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        TXFINISHED  : out std_logic;                            -- Transmitter operation finished
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        SOUT        : out std_logic                             -- Transmitter output
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    );
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end uart_transmitter;
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architecture rtl of uart_transmitter is
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    -- FSM
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    type state_type is (IDLE, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PAR, STOP, STOP2);
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    signal CState, NState : state_type;
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    -- Signals
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    signal iTx2         : std_logic;        -- Next TX step
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    signal iSout        : std_logic;        -- Transmitter output
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    signal iParity      : std_logic;        -- Parity
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    signal iFinished    : std_logic;        -- TX finished
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begin
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    -- Transmitter FSM update process
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    TX_PROC: process (RST, CLK)
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    begin
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        if (RST = '1') then
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            CState <= IDLE;
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            iTx2   <= '0';
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        elsif (CLK'event and CLK='1') then
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            if (TXCLK = '1') then           -- TX clock
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                if (iTx2 = '0') then        -- Two TX clocks per step
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                    CState <= NState;       -- Next step
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                    iTx2 <= '1';
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                else
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                    if ((WLS = "00") and (STB = '1') and CState = STOP2) then
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                        CState <= NState;   -- 1.5 stop bits for 5 bit word mode
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                        iTx2 <= '1';
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                    else
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                        CState <= CState;   -- First TX clock, wait
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                        iTx2 <= '0';
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                    end if;
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                end if;
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            end if;
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        end if;
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    end process;
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    -- Transmitter FSM
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    TX_FSM: process (CState, TXSTART, DIN, WLS, PEN, SP, EPS, STB, iParity)
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    begin
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        -- Defaults
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        NState      <= IDLE;
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        iSout       <= '1';
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        case CState is
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            when IDLE   =>  if (TXSTART = '1') then
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                                NState <= START;
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                            end if;
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            when START  =>  iSout  <= '0';
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                            NState <= BIT0;
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            when BIT0   =>  iSout  <= DIN(0);
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                            NState <= BIT1;
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            when BIT1   =>  iSout  <= DIN(1);
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                            NState <= BIT2;
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            when BIT2   =>  iSout  <= DIN(2);
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                            NState <= BIT3;
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            when BIT3   =>  iSout  <= DIN(3);
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                            NState <= BIT4;
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            when BIT4   =>  iSout  <= DIN(4);
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                            if (WLS = "00") then            -- 5 bits
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                                if (PEN = '1') then
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                                    NState <= PAR;          -- Parity enabled
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                                else
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                                    NState <= STOP;         -- No parity
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                                end if;
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                            else
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                                NState <= BIT5;
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                            end if;
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            when BIT5   =>  iSout  <= DIN(5);
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                            if (WLS = "01") then            -- 6 bits
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                                if (PEN = '1') then
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                                    NState <= PAR;          -- Parity enabled
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                                else
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                                    NState <= STOP;         -- No parity
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                                end if;
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                            else
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                                NState <= BIT6;
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                            end if;
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            when BIT6   =>  iSout  <= DIN(6);
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                            if (WLS = "10") then            -- 7 bits
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                                if (PEN = '1') then
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                                    NState <= PAR;          -- Parity enabled
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                                else
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                                    NState <= STOP;         -- No parity
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                                end if;
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                            else
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                                NState <= BIT7;
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                            end if;
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            when BIT7   =>  iSout  <= DIN(7);
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                            if (PEN = '1') then
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                                NState <= PAR;              -- Parity enabled
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                            else
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                                NState <= STOP;             -- No parity
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                            end if;
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            when PAR    =>  if (SP = '1') then              -- Sticky parity
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                                if (EPS = '1') then
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                                    iSout <= '0';           -- Even parity -> cleared
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                                else
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                                    iSout <= '1';           -- Odd parity  -> set
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                                end if;
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                            else
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                                if (EPS = '1') then
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                                    iSout <= iParity;       -- Even parity
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                                else
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                                    iSout <= not iParity;   -- Odd parity
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                                end if;
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                            end if;
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                            NState <= STOP;
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            when STOP   =>  if (STB = '1') then             -- 2 stop bits
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                                NState <= STOP2;
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                            else
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                                if (TXSTART = '1') then     -- Next transmission
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                                    NState <= START;
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                                end if;
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                            end if;
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            when STOP2  =>  if (TXSTART = '1') then         -- Next transmission
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                                NState <= START;
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                            end if;
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            when others =>  null;
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        end case;
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    end process;
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    -- Parity generation
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    TX_PAR: process (DIN, WLS)
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        variable iP40, iP50, iP60, iP70 : std_logic;
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    begin
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        iP40 := DIN(4) xor DIN(3) xor DIN(2) xor DIN(1) xor DIN(0);
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        iP50 := DIN(5) xor iP40;
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        iP60 := DIN(6) xor iP50;
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        iP70 := DIN(7) xor iP60;
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        case WLS is
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            when "00"   => iParity <= iP40;
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            when "01"   => iParity <= iP50;
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            when "10"   => iParity <= iP60;
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            when others => iParity <= iP70;
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        end case;
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    end process;
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    -- Signal TX finished on STOP bit transmission
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    TX_FIN: process (CLK, RST)
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        variable iLast : std_logic;
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    begin
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        if (RST = '1') then
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            iFinished <= '0';
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            iLast := '0';
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        elsif (CLK'event and CLK = '1') then
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            iFinished <= '0';
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            if (iLast = '0' and CState = STOP) then
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                iFinished <= '1';
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            end if;
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            if (CState = STOP) then
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                iLast := '1';
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            else
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                iLast := '0';
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            end if;
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        end if;
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    end process;
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    -- Output signals
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    SOUT       <= iSout when BC = '0' else '0';
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    TXFINISHED <= iFinished;
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end rtl;
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