OpenCores
URL https://opencores.org/ocsvn/wb_uart/wb_uart/trunk

Subversion Repositories wb_uart

[/] [wb_uart/] [trunk/] [src/] [wb8_uart_package.vhd] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 federico.a
--
2
-- Package for UART testing
3
--
4
-- Author:  Federico Aglietti, www.ipdesign.eu
5
-- Version: 2.0
6
-- Date:    30.08.2009
7
-- WishBone 8-bit bus compliant
8
--
9
-- Author:  Sebastian Witt
10
-- Version: 1.0
11
-- Date:    31.01.2008
12
--
13
-- This code is free software; you can redistribute it and/or
14
-- modify it under the terms of the GNU Lesser General Public
15
-- License as published by the Free Software Foundation; either
16
-- version 2.1 of the License, or (at your option) any later version.
17
--
18
-- This code is distributed in the hope that it will be useful,
19
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
20
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
21
-- Lesser General Public License for more details.
22
--
23
-- You should have received a copy of the GNU Lesser General Public
24
-- License along with this library; if not, write to the
25
-- Free Software  Foundation, Inc., 59 Temple Place, Suite 330,
26
-- Boston, MA  02111-1307  USA
27
--
28
 
29
LIBRARY IEEE;
30
USE IEEE.std_logic_1164.all;
31
USE std.textio.all;
32
USE work.txt_util.all;
33
 
34
 
35
package uart_package is
36
    constant CYCLE  : time := 30 ns;
37
 
38
    -- UART register addresses
39
    constant A_RBR  : std_logic_vector(2 downto 0) := "000";
40
    constant A_DLL  : std_logic_vector(2 downto 0) := "000";
41
    constant A_THR  : std_logic_vector(2 downto 0) := "000";
42
    constant A_DLM  : std_logic_vector(2 downto 0) := "001";
43
    constant A_IER  : std_logic_vector(2 downto 0) := "001";
44
    constant A_IIR  : std_logic_vector(2 downto 0) := "010";
45
    constant A_FCR  : std_logic_vector(2 downto 0) := "010";
46
    constant A_LCR  : std_logic_vector(2 downto 0) := "011";
47
    constant A_MCR  : std_logic_vector(2 downto 0) := "100";
48
    constant A_LSR  : std_logic_vector(2 downto 0) := "101";
49
    constant A_MSR  : std_logic_vector(2 downto 0) := "110";
50
    constant A_SCR  : std_logic_vector(2 downto 0) := "111";
51
 
52
    -- UART input interface
53
    type uart_in_t is record
54
        WB_CYC      : std_logic;
55
        WB_STB      : std_logic;
56
        WB_WE       : std_logic;
57
        WB_ADR      : std_logic_vector(31 downto 0);
58
        WB_DIN      : std_logic_vector(7 downto 0);
59
    end record;
60
 
61
    type uart_out_t is record
62
        WB_ACK      : std_logic;
63
        WB_DOUT     : std_logic_vector(7 downto 0);
64
    end record;
65
 
66
    -- Write to UART
67
    procedure uart_write (signal clk: in std_logic;
68
                          signal ui : out uart_in_t;
69
                          signal uo : in  uart_out_t;
70
                          addr      : in std_logic_vector (2 downto 0);
71
                          data      : in std_logic_vector (7 downto 0);
72
                          file log  : TEXT
73
                         );
74
 
75
    -- Read from UART
76
    procedure uart_read  (signal clk: in std_logic;
77
                          signal ui : out uart_in_t;
78
                          signal uo : in  uart_out_t;
79
                          addr      : in std_logic_vector(2 downto 0);
80
                          ret       : out std_logic_vector(7 downto 0);
81
                          file log  : TEXT
82
                         );
83
 
84
    -- Compare two std_logig_vectors (handles don't-care)
85
    function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean;
86
 
87
end uart_package;
88
 
89
package body uart_package is
90
    -- Write to UART
91
    procedure uart_write (signal clk: in std_logic;signal ui: out uart_in_t;signal uo: in  uart_out_t;addr: in std_logic_vector (2 downto 0);data: in std_logic_vector (7 downto 0);file log: TEXT) is
92
    begin
93
        wait until CLK'event and CLK='1';
94
        print (log, "UART write: 0x" & hstr(addr) & " : 0x" & hstr(data));
95
--        wait for cycle;
96
        ui.WB_ADR  <= "00000000000000000000000000000"&addr;
97
        ui.WB_DIN  <= data;
98
        ui.WB_CYC  <= '1';
99
        ui.WB_STB  <= '1';
100
        ui.WB_WE   <= '1';
101
        wait until uo.WB_ACK'event and uo.WB_ACK='1';
102
        wait until CLK'event and CLK='1';
103
--        wait for cycle/2;
104
        ui.WB_WE   <= '0';
105
        ui.WB_CYC  <= '0';
106
        ui.WB_STB  <= '0';
107
        ui.WB_DIN <= (others => '0');
108
    end uart_write;
109
 
110
    -- Read from UART
111
    procedure uart_read(signal clk: in std_logic;signal ui : out uart_in_t;signal uo: in  uart_out_t;addr: in std_logic_vector(2 downto 0);ret: out std_logic_vector(7 downto 0);file log: TEXT) is
112
      variable data : std_logic_vector(7 downto 0);
113
    begin
114
        wait until CLK'event and CLK='1';
115
--        wait for cycle;
116
        ui.WB_ADR    <= "00000000000000000000000000000"&addr;
117
        ui.WB_CYC    <= '1';
118
        ui.WB_STB    <= '1';
119
        --wait until uo.WB_ACK'event and uo.WB_ACK='1';
120
        wait until CLK'event and CLK='1' and uo.WB_ACK='1';
121
            data:= uo.WB_DOUT;
122
        print (log, "UART read:  0x" & hstr(addr) & " : 0x" & hstr(data));
123
        --wait for cycle/2;
124
        ui.WB_WE  <= '0';
125
        ui.WB_CYC <= '0';
126
        ui.WB_STB <= '0';
127
        ui.WB_DIN <= (others => '0');
128
        ret:= data;
129
    end uart_read;
130
 
131
    -- Compare two std_logig_vectors (handles don't-care)
132
    function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean is
133
        variable i : natural;
134
    begin
135
        for i in d1'range loop
136
            if (not (d1(i)='-' or d2(i)='-')) then
137
                if (d1(i)/=d2(i)) then
138
                    return false;
139
                end if;
140
            end if;
141
        end loop;
142
        return true;
143
    end compare;
144
 
145
end uart_package;
146
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.