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//                              -*- Mode: Verilog -*-
// Filename        : wb_master.v
// Description     : Wishbone Master Behavorial
// Author          : Winefred Washington
// Created On      : Thu Jan 11 21:18:41 2001
// Last Modified By: .
// Last Modified On: .
// Update Count    : 0
// Status          : Unknown, Use with caution!
 
//        Description                   Specification
// General Description:            8, 16, 32-bit WISHBONE Master
// Supported cycles:               MASTER, READ/WRITE
//                                 MASTER, BLOCK READ/WRITE
//                                 MASTER, RMW
// Data port, size:                8, 16, 32-bit
// Data port, granularity          8-bit
// Data port, Max. operand size    32-bit
// Data transfer ordering:         little endian
// Data transfer sequencing:       undefined
//
 
module WB_MASTER32(CLK_I, RST_I, TAG_I, TAG_O,
                   ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);
 
   input                CLK_I;
   input                RST_I;
   input [3:0]           TAG_I;
   output [3:0]  TAG_O;
   input                ACK_I;
   output [31:0]         ADR_O;
   output               CYC_O;
   input [31:0]  DAT_I;
   output [31:0]         DAT_O;
   input                ERR_I;
   input                RTY_I;
   output [3:0]  SEL_O;
   output               STB_O;
   output               WE_O;
 
   reg [31:0]            ADR_O;
   reg [3:0]             SEL_O;
   reg                  CYC_O;
   reg                  STB_O;
   reg                  WE_O;
   reg [31:0]            DAT_O;
 
   wire [15:0]           mem_sizes;      // determines the data width of an address range
   reg [31:0]            write_burst_buffer[0:7];
   reg [31:0]            read_burst_buffer[0:7];
 
   reg                  GO;
   integer              cycle_end;
   integer              address;
   integer              data;
   integer              selects;
   integer              write_flag;
 
   //
   // mem_sizes determines the data widths of memory space
   // The memory space is divided into eight regions. Each
   // region is controlled by a two bit field.
   //
   //    Bits
   //    00 = 8 bit memory space
   //    01 = 16 bit 
   //    10 = 32 bit
   //    11 = 64 bit (not supported in this model
   //
 
   assign               mem_sizes = 16'b00_01_10_11_00_01_10_11;
 
   function [1:0] data_width;
      input [31:0] adr;
      begin
         casex (adr[31:29])
           3'b000: data_width = mem_sizes[15:14];
           3'b001: data_width = mem_sizes[13:12];
           3'b010: data_width = mem_sizes[11:10];
           3'b011: data_width = mem_sizes[9:8];
           3'b100: data_width = mem_sizes[7:6];
           3'b101: data_width = mem_sizes[5:4];
           3'b110: data_width = mem_sizes[3:2];
           3'b111: data_width = mem_sizes[1:0];
           3'bxxx: data_width = 2'bxx;
         endcase // casex (adr[31:29])
      end
   endfunction
 
   always @(posedge CLK_I or posedge RST_I)
     begin
        if (RST_I)
          begin
             GO = 1'b0;
          end
     end
 
   // read single
   task rd;
      input [31:0] adr;
      output [31:0] result;
 
      begin
         cycle_end = 1;
         address = adr;
         selects = 255;
         write_flag = 0;
 
         GO <= 1;
         @(posedge CLK_I);
         GO <= 0;
 
         // wait for cycle to start
         while (~CYC_O)
           @(posedge CLK_I);
 
         // wait for cycle to end
         while (CYC_O)
           @(posedge CLK_I);
 
         result = data;
 
      end
   endtask // read
 
   task wr;
      input [31:0] adr;
      input [31:0] dat;
      input [3:0] sel;
      begin
         cycle_end = 1;
         address = adr;
         selects = sel;
         write_flag = 1;
         data = dat;
 
         GO <= 1;
         @(posedge CLK_I);
         GO <= 0;
 
         // wait for cycle to start
         while (~CYC_O)
           @(posedge CLK_I);
 
         // wait for cycle to end
         while (CYC_O)
           @(posedge CLK_I);
      end
   endtask // wr
 
   // block read
   task blkrd;
      input [31:0] adr;
      input end_flag;
      output [31:0] result;
 
      begin
         write_flag = 0;
         cycle_end = end_flag;
         address = adr;
         GO <= 1;
         @(posedge CLK_I);
         GO <= 0;
 
         while (~(ACK_I & STB_O))
           @(posedge CLK_I);
 
         result = data;
      end
   endtask // blkrd
 
   // block write
   task blkwr;
      input [31:0] adr;
      input [31:0] dat;
      input [3:0] sel;
      input end_flag;
      begin
         write_flag = 1;
         cycle_end = end_flag;
         address = adr;
         data = dat;
         selects = sel;
         GO <= 1;
         @(posedge CLK_I);
         GO <= 0;
 
         while (~(ACK_I & STB_O))
           @(posedge CLK_I);
 
      end
   endtask // blkwr
 
   // RMW
   task rmw;
      input [31:0] adr;
      input [31:0] dat;
      input [3:0] sel;
      output [31:0] result;
 
      begin
         // read phase
         write_flag = 0;
         cycle_end = 0;
         address = adr;
         GO <= 1;
         @(posedge CLK_I);
         GO <= 0;
 
         while (~(ACK_I & STB_O))
           @(posedge CLK_I);
 
         result = data;
 
         // write phase
         write_flag = 1;
         address = adr;
         selects = sel;
         GO <= 1;
         data <= dat;
         cycle_end <= 1;
         @(posedge CLK_I);
         GO <= 0;
 
         while (~(ACK_I & STB_O))
           @(posedge CLK_I);
 
      end
   endtask // rmw
 
   always @(posedge CLK_I)
     begin
        if (RST_I)
          ADR_O <= 32'h0000_0000;
        else
          ADR_O <= address;
     end
 
   always @(posedge CLK_I)
     begin
        if (RST_I | ERR_I | RTY_I)
          CYC_O <= 1'b0;
        else if ((cycle_end == 1) & ACK_I)
          CYC_O <= 1'b0;
        else if (GO | CYC_O)
          CYC_O <= 1'b1;
     end
 
   // stb control
   always @(posedge CLK_I)
     begin
        if (RST_I | ERR_I | RTY_I)
          STB_O <= 1'b0;
        else if (STB_O & ACK_I)
          STB_O <= 1'b0;
        else if (GO | STB_O)
          STB_O <= 1'b1;
     end
 
   // selects & data
   always @(posedge CLK_I)
     begin
        if (write_flag == 0) begin
           SEL_O <= 4'b1111;
           if (STB_O & ACK_I)
             data <= DAT_I;
        end
        else begin
           case (data_width(address))
             2'b00: begin
                SEL_O <= {3'b000, selects[0]};
                DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]};
             end
             2'b01: begin
                SEL_O <= {2'b00, selects[1:0]};
                DAT_O <= {data[15:0], data[15:0]};
             end
             2'b10: begin
                SEL_O <= selects;
                DAT_O <= data;
             end
           endcase
        end
     end
 
   always @(posedge CLK_I)
     begin
        if (RST_I)
          WE_O <= 1'b0;
        else if (GO)
          WE_O <= write_flag;
     end
 
endmodule
 
 
 
 
 

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[/] [wb_verilog/] [trunk/] [wb_master.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	4	wwashingto	`// -- Mode: Verilog --`
2			`// Filename : wb_master.v`
3			`// Description : Wishbone Master Behavorial`
4			`// Author : Winefred Washington`
5			`// Created On : Thu Jan 11 21:18:41 2001`
6			`// Last Modified By: .`
7			`// Last Modified On: .`
8			`// Update Count : 0`
9			`// Status : Unknown, Use with caution!`
10
11			`// Description Specification`
12			`// General Description: 8, 16, 32-bit WISHBONE Master`
13			`// Supported cycles: MASTER, READ/WRITE`
14			`// MASTER, BLOCK READ/WRITE`
15			`// MASTER, RMW`
16			`// Data port, size: 8, 16, 32-bit`
17			`// Data port, granularity 8-bit`
18			`// Data port, Max. operand size 32-bit`
19			`// Data transfer ordering: little endian`
20			`// Data transfer sequencing: undefined`
21			`//`
22
23			`module WB_MASTER32(CLK_I, RST_I, TAG_I, TAG_O,`
24			`ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);`
25
26			`input CLK_I;`
27			`input RST_I;`
28			`input [3:0] TAG_I;`
29			`output [3:0] TAG_O;`
30			`input ACK_I;`
31			`output [31:0] ADR_O;`
32			`output CYC_O;`
33			`input [31:0] DAT_I;`
34			`output [31:0] DAT_O;`
35			`input ERR_I;`
36			`input RTY_I;`
37			`output [3:0] SEL_O;`
38			`output STB_O;`
39			`output WE_O;`
40
41			`reg [31:0] ADR_O;`
42			`reg [3:0] SEL_O;`
43			`reg CYC_O;`
44			`reg STB_O;`
45			`reg WE_O;`
46			`reg [31:0] DAT_O;`
47
48			`wire [15:0] mem_sizes; // determines the data width of an address range`
49			`reg [31:0] write_burst_buffer[0:7];`
50			`reg [31:0] read_burst_buffer[0:7];`
51
52			`reg GO;`
53			`integer cycle_end;`
54			`integer address;`
55			`integer data;`
56			`integer selects;`
57			`integer write_flag;`
58
59			`//`
60			`// mem_sizes determines the data widths of memory space`
61			`// The memory space is divided into eight regions. Each`
62			`// region is controlled by a two bit field.`
63			`//`
64			`// Bits`
65			`// 00 = 8 bit memory space`
66			`// 01 = 16 bit`
67			`// 10 = 32 bit`
68			`// 11 = 64 bit (not supported in this model`
69			`//`
70
71			`assign mem_sizes = 16'b00_01_10_11_00_01_10_11;`
72
73			`function [1:0] data_width;`
74			`input [31:0] adr;`
75			`begin`
76			`casex (adr[31:29])`
77			`3'b000: data_width = mem_sizes[15:14];`
78			`3'b001: data_width = mem_sizes[13:12];`
79			`3'b010: data_width = mem_sizes[11:10];`
80			`3'b011: data_width = mem_sizes[9:8];`
81			`3'b100: data_width = mem_sizes[7:6];`
82			`3'b101: data_width = mem_sizes[5:4];`
83			`3'b110: data_width = mem_sizes[3:2];`
84			`3'b111: data_width = mem_sizes[1:0];`
85			`3'bxxx: data_width = 2'bxx;`
86			`endcase // casex (adr[31:29])`
87			`end`
88			`endfunction`
89
90			`always @(posedge CLK_I or posedge RST_I)`
91			`begin`
92			`if (RST_I)`
93			`begin`
94			`GO = 1'b0;`
95			`end`
96			`end`
97
98			`// read single`
99			`task rd;`
100			`input [31:0] adr;`
101			`output [31:0] result;`
102
103			`begin`
104			`cycle_end = 1;`
105			`address = adr;`
106			`selects = 255;`
107			`write_flag = 0;`
108
109			`GO <= 1;`
110			`@(posedge CLK_I);`
111			`GO <= 0;`
112
113			`// wait for cycle to start`
114			`while (~CYC_O)`
115			`@(posedge CLK_I);`
116
117			`// wait for cycle to end`
118			`while (CYC_O)`
119			`@(posedge CLK_I);`
120
121			`result = data;`
122
123			`end`
124			`endtask // read`
125
126			`task wr;`
127			`input [31:0] adr;`
128			`input [31:0] dat;`
129			`input [3:0] sel;`
130			`begin`
131			`cycle_end = 1;`
132			`address = adr;`
133			`selects = sel;`
134			`write_flag = 1;`
135			`data = dat;`
136
137			`GO <= 1;`
138			`@(posedge CLK_I);`
139			`GO <= 0;`
140
141			`// wait for cycle to start`
142			`while (~CYC_O)`
143			`@(posedge CLK_I);`
144
145			`// wait for cycle to end`
146			`while (CYC_O)`
147			`@(posedge CLK_I);`
148			`end`
149			`endtask // wr`
150
151			`// block read`
152			`task blkrd;`
153			`input [31:0] adr;`
154			`input end_flag;`
155			`output [31:0] result;`
156
157			`begin`
158			`write_flag = 0;`
159			`cycle_end = end_flag;`
160			`address = adr;`
161			`GO <= 1;`
162			`@(posedge CLK_I);`
163			`GO <= 0;`
164
165			`while (~(ACK_I & STB_O))`
166			`@(posedge CLK_I);`
167
168			`result = data;`
169			`end`
170			`endtask // blkrd`
171
172			`// block write`
173			`task blkwr;`
174			`input [31:0] adr;`
175			`input [31:0] dat;`
176			`input [3:0] sel;`
177			`input end_flag;`
178			`begin`
179			`write_flag = 1;`
180			`cycle_end = end_flag;`
181			`address = adr;`
182			`data = dat;`
183			`selects = sel;`
184			`GO <= 1;`
185			`@(posedge CLK_I);`
186			`GO <= 0;`
187
188			`while (~(ACK_I & STB_O))`
189			`@(posedge CLK_I);`
190
191			`end`
192			`endtask // blkwr`
193
194			`// RMW`
195			`task rmw;`
196			`input [31:0] adr;`
197			`input [31:0] dat;`
198			`input [3:0] sel;`
199			`output [31:0] result;`
200
201			`begin`
202			`// read phase`
203			`write_flag = 0;`
204			`cycle_end = 0;`
205			`address = adr;`
206			`GO <= 1;`
207			`@(posedge CLK_I);`
208			`GO <= 0;`
209
210			`while (~(ACK_I & STB_O))`
211			`@(posedge CLK_I);`
212
213			`result = data;`
214
215			`// write phase`
216			`write_flag = 1;`
217			`address = adr;`
218			`selects = sel;`
219			`GO <= 1;`
220			`data <= dat;`
221			`cycle_end <= 1;`
222			`@(posedge CLK_I);`
223			`GO <= 0;`
224
225			`while (~(ACK_I & STB_O))`
226			`@(posedge CLK_I);`
227
228			`end`
229			`endtask // rmw`
230
231			`always @(posedge CLK_I)`
232			`begin`
233			`if (RST_I)`
234			`ADR_O <= 32'h0000_0000;`
235			`else`
236			`ADR_O <= address;`
237			`end`
238
239			`always @(posedge CLK_I)`
240			`begin`
241			`if (RST_I \| ERR_I \| RTY_I)`
242			`CYC_O <= 1'b0;`
243			`else if ((cycle_end == 1) & ACK_I)`
244			`CYC_O <= 1'b0;`
245			`else if (GO \| CYC_O)`
246			`CYC_O <= 1'b1;`
247			`end`
248
249			`// stb control`
250			`always @(posedge CLK_I)`
251			`begin`
252			`if (RST_I \| ERR_I \| RTY_I)`
253			`STB_O <= 1'b0;`
254			`else if (STB_O & ACK_I)`
255			`STB_O <= 1'b0;`
256			`else if (GO \| STB_O)`
257			`STB_O <= 1'b1;`
258			`end`
259
260			`// selects & data`
261			`always @(posedge CLK_I)`
262			`begin`
263			`if (write_flag == 0) begin`
264			`SEL_O <= 4'b1111;`
265			`if (STB_O & ACK_I)`
266			`data <= DAT_I;`
267			`end`
268			`else begin`
269			`case (data_width(address))`
270			`2'b00: begin`
271			`SEL_O <= {3'b000, selects[0]};`
272			`DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]};`
273			`end`
274			`2'b01: begin`
275			`SEL_O <= {2'b00, selects[1:0]};`
276			`DAT_O <= {data[15:0], data[15:0]};`
277			`end`
278			`2'b10: begin`
279			`SEL_O <= selects;`
280			`DAT_O <= data;`
281			`end`
282			`endcase`
283			`end`
284			`end`
285
286			`always @(posedge CLK_I)`
287			`begin`
288			`if (RST_I)`
289			`WE_O <= 1'b0;`
290			`else if (GO)`
291			`WE_O <= write_flag;`
292			`end`
293
294			`endmodule`
295
296
297
298
299