1 |
2 |
tantos |
library ieee,exemplar;
|
2 |
|
|
use ieee.std_logic_1164.all;
|
3 |
|
|
use exemplar.exemplar_1164.all;
|
4 |
|
|
|
5 |
|
|
entity vga_chip_tb is
|
6 |
|
|
-- Generic declarations of the tested unit
|
7 |
|
|
generic(
|
8 |
|
|
v_mem_width : POSITIVE := 16;
|
9 |
|
|
fifo_size : POSITIVE := 256;
|
10 |
|
|
v_addr_width : POSITIVE := 20 );
|
11 |
|
|
end vga_chip_tb;
|
12 |
|
|
|
13 |
|
|
architecture TB of vga_chip_tb is
|
14 |
|
|
-- Component declaration of the tested unit
|
15 |
|
|
component vga_chip
|
16 |
|
|
port (
|
17 |
|
|
clk_i: in std_logic;
|
18 |
|
|
clk_en: in std_logic := '1';
|
19 |
|
|
rst_i: in std_logic := '0';
|
20 |
|
|
|
21 |
|
|
-- CPU bus interface
|
22 |
|
|
dat_i: in std_logic_vector (8-1 downto 0);
|
23 |
|
|
dat_oi: in std_logic_vector (8-1 downto 0);
|
24 |
|
|
dat_o: out std_logic_vector (8-1 downto 0);
|
25 |
|
|
cyc_i: in std_logic;
|
26 |
|
|
ack_o: out std_logic;
|
27 |
|
|
ack_oi: in std_logic;
|
28 |
|
|
we_i: in std_logic;
|
29 |
|
|
vmem_stb_i: in std_logic;
|
30 |
|
|
reg_stb_i: in std_logic;
|
31 |
|
|
adr_i: in std_logic_vector (20 downto 0);
|
32 |
|
|
|
33 |
|
|
-- video memory SRAM interface
|
34 |
|
|
s_data : inout std_logic_vector((16-1) downto 0);
|
35 |
|
|
s_addr : out std_logic_vector((20-1) downto 0);
|
36 |
|
|
s_oen : out std_logic;
|
37 |
|
|
s_wrhn : out std_logic;
|
38 |
|
|
s_wrln : out std_logic;
|
39 |
|
|
s_cen : out std_logic;
|
40 |
|
|
|
41 |
|
|
-- sync blank and video signal outputs
|
42 |
|
|
h_sync: out std_logic;
|
43 |
|
|
h_blank: out std_logic;
|
44 |
|
|
v_sync: out std_logic;
|
45 |
|
|
v_blank: out std_logic;
|
46 |
|
|
h_tc: out std_logic;
|
47 |
|
|
v_tc: out std_logic;
|
48 |
|
|
blank: out std_logic;
|
49 |
|
|
video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
|
50 |
|
|
);
|
51 |
|
|
end component;
|
52 |
|
|
|
53 |
|
|
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
|
54 |
|
|
signal clk_i : std_logic;
|
55 |
|
|
signal clk_en : std_logic;
|
56 |
|
|
signal rst_i : std_logic;
|
57 |
|
|
signal dat_i : std_logic_vector(7 downto 0);
|
58 |
|
|
signal dat_oi : std_logic_vector(7 downto 0);
|
59 |
|
|
signal cyc_i : std_logic;
|
60 |
|
|
signal ack_oi : std_logic;
|
61 |
|
|
signal we_i : std_logic;
|
62 |
|
|
signal vmem_stb_i : std_logic;
|
63 |
|
|
signal reg_stb_i : std_logic;
|
64 |
|
|
signal adr_i : std_logic_vector(v_addr_width downto 0);
|
65 |
|
|
signal s_data : std_logic_vector((v_mem_width-1) downto 0);
|
66 |
|
|
-- Observed signals - signals mapped to the output ports of tested entity
|
67 |
|
|
signal dat_o : std_logic_vector(7 downto 0);
|
68 |
|
|
signal ack_o : std_logic;
|
69 |
|
|
signal s_addr : std_logic_vector((v_addr_width-1) downto 0);
|
70 |
|
|
signal s_oen : std_logic;
|
71 |
|
|
signal s_wrhn : std_logic;
|
72 |
|
|
signal s_wrln : std_logic;
|
73 |
|
|
signal s_cen : std_logic;
|
74 |
|
|
signal h_sync : std_logic;
|
75 |
|
|
signal h_blank : std_logic;
|
76 |
|
|
signal v_sync : std_logic;
|
77 |
|
|
signal v_blank : std_logic;
|
78 |
|
|
signal h_tc : std_logic;
|
79 |
|
|
signal v_tc : std_logic;
|
80 |
|
|
signal blank : std_logic;
|
81 |
|
|
signal video_out : std_logic_vector(7 downto 0);
|
82 |
|
|
|
83 |
|
|
constant reg_total0 : std_logic_vector(v_addr_width downto 0) := "000000000000000000000";
|
84 |
|
|
constant reg_total1 : std_logic_vector(v_addr_width downto 0) := "000000000000000000001";
|
85 |
|
|
constant reg_total2 : std_logic_vector(v_addr_width downto 0) := "000000000000000000010";
|
86 |
|
|
constant reg_fifo_treshold : std_logic_vector(v_addr_width downto 0) := "000000000000000000011";
|
87 |
|
|
constant reg_hbs : std_logic_vector(v_addr_width downto 0) := "000000000000000000100";
|
88 |
|
|
constant reg_hss : std_logic_vector(v_addr_width downto 0) := "000000000000000000101";
|
89 |
|
|
constant reg_hse : std_logic_vector(v_addr_width downto 0) := "000000000000000000110";
|
90 |
|
|
constant reg_htotal : std_logic_vector(v_addr_width downto 0) := "000000000000000000111";
|
91 |
|
|
constant reg_vbs : std_logic_vector(v_addr_width downto 0) := "000000000000000001000";
|
92 |
|
|
constant reg_vss : std_logic_vector(v_addr_width downto 0) := "000000000000000001001";
|
93 |
|
|
constant reg_vse : std_logic_vector(v_addr_width downto 0) := "000000000000000001010";
|
94 |
|
|
constant reg_vtotal : std_logic_vector(v_addr_width downto 0) := "000000000000000001011";
|
95 |
|
|
constant reg_pps : std_logic_vector(v_addr_width downto 0) := "000000000000000001100";
|
96 |
|
|
constant reg_ws : std_logic_vector(v_addr_width downto 0) := "000000000000000001101";
|
97 |
|
|
constant reg_bpp : std_logic_vector(v_addr_width downto 0) := "000000000000000001110";
|
98 |
|
|
|
99 |
|
|
constant val_total0 : std_logic_vector(7 downto 0) := "00001111";
|
100 |
|
|
constant val_total1 : std_logic_vector(7 downto 0) := "00000000";
|
101 |
|
|
constant val_total2 : std_logic_vector(7 downto 0) := "00000000";
|
102 |
|
|
constant val_fifo_treshold : std_logic_vector(7 downto 0) := "00000011";
|
103 |
|
|
constant val_hbs : std_logic_vector(7 downto 0) := "00000111";
|
104 |
|
|
constant val_hss : std_logic_vector(7 downto 0) := "00001000";
|
105 |
|
|
constant val_hse : std_logic_vector(7 downto 0) := "00001001";
|
106 |
|
|
constant val_htotal : std_logic_vector(7 downto 0) := "00001010";
|
107 |
|
|
constant val_vbs : std_logic_vector(7 downto 0) := "00000001";
|
108 |
|
|
constant val_vss : std_logic_vector(7 downto 0) := "00000010";
|
109 |
|
|
constant val_vse : std_logic_vector(7 downto 0) := "00000011";
|
110 |
|
|
constant val_vtotal : std_logic_vector(7 downto 0) := "00000100";
|
111 |
|
|
constant val_pps : std_logic_vector(7 downto 0) := "00000001";
|
112 |
|
|
constant val_ws : std_logic_vector(7 downto 0) := "00010010";
|
113 |
|
|
-- constant val_bpp : std_logic_vector(7 downto 0) := "00000001";
|
114 |
|
|
constant val_bpp : std_logic_vector(7 downto 0) := "00000011";
|
115 |
|
|
|
116 |
|
|
-- Add your code here ...
|
117 |
|
|
|
118 |
|
|
procedure chk_val(
|
119 |
|
|
signal clk_i: in STD_LOGIC;
|
120 |
|
|
signal adr_i: out STD_LOGIC_VECTOR(v_addr_width downto 0);
|
121 |
|
|
signal dat_o: in STD_LOGIC_VECTOR(7 downto 0);
|
122 |
|
|
signal dat_i: out STD_LOGIC_VECTOR(7 downto 0);
|
123 |
|
|
signal we_i: out STD_LOGIC;
|
124 |
|
|
signal cyc_i: out std_logic;
|
125 |
|
|
signal stb_i: out STD_LOGIC;
|
126 |
|
|
signal ack_o: in STD_LOGIC;
|
127 |
|
|
constant addr: in STD_LOGIC_VECTOR(v_addr_width downto 0);
|
128 |
|
|
constant data: in STD_LOGIC_VECTOR(7 downto 0)
|
129 |
|
|
) is
|
130 |
|
|
begin
|
131 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
132 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
133 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
134 |
|
|
adr_i <= addr;
|
135 |
|
|
dat_i <= (others => '0');
|
136 |
|
|
cyc_i <= '1';
|
137 |
|
|
stb_i <= '1';
|
138 |
|
|
we_i <= '0';
|
139 |
|
|
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
|
140 |
|
|
assert dat_o = data report "Value does not match!" severity ERROR;
|
141 |
|
|
adr_i <= (others => '0');
|
142 |
|
|
stb_i <= '0';
|
143 |
|
|
cyc_i <= '0';
|
144 |
|
|
end procedure;
|
145 |
|
|
|
146 |
|
|
procedure write_val(
|
147 |
|
|
signal clk_i: in STD_LOGIC;
|
148 |
|
|
signal adr_i: out STD_LOGIC_VECTOR(v_addr_width downto 0);
|
149 |
|
|
signal dat_o: in STD_LOGIC_VECTOR(7 downto 0);
|
150 |
|
|
signal dat_i: out STD_LOGIC_VECTOR(7 downto 0);
|
151 |
|
|
signal we_i: out STD_LOGIC;
|
152 |
|
|
signal cyc_i: out std_logic;
|
153 |
|
|
signal stb_i: out STD_LOGIC;
|
154 |
|
|
signal ack_o: in STD_LOGIC;
|
155 |
|
|
constant addr: in STD_LOGIC_VECTOR(v_addr_width downto 0);
|
156 |
|
|
constant data: in STD_LOGIC_VECTOR(7 downto 0)
|
157 |
|
|
) is
|
158 |
|
|
begin
|
159 |
|
|
adr_i <= (others => '0');
|
160 |
|
|
dat_i <= (others => '0');
|
161 |
|
|
stb_i <= '0';
|
162 |
|
|
we_i <= '0';
|
163 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
164 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
165 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
166 |
|
|
adr_i <= addr;
|
167 |
|
|
dat_i <= data;
|
168 |
|
|
cyc_i <= '1';
|
169 |
|
|
stb_i <= '1';
|
170 |
|
|
we_i <= '1';
|
171 |
|
|
wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
|
172 |
|
|
adr_i <= (others => '0');
|
173 |
|
|
dat_i <= (others => '0');
|
174 |
|
|
cyc_i <= '0';
|
175 |
|
|
stb_i <= '0';
|
176 |
|
|
we_i <= '0';
|
177 |
|
|
end procedure;
|
178 |
|
|
begin
|
179 |
|
|
|
180 |
|
|
-- Unit Under Test port map
|
181 |
|
|
UUT : vga_chip
|
182 |
|
|
port map (
|
183 |
|
|
clk_i => clk_i,
|
184 |
|
|
clk_en => clk_en,
|
185 |
|
|
rst_i => rst_i,
|
186 |
|
|
dat_i => dat_i,
|
187 |
|
|
dat_oi => dat_oi,
|
188 |
|
|
dat_o => dat_o,
|
189 |
|
|
cyc_i => cyc_i,
|
190 |
|
|
ack_o => ack_o,
|
191 |
|
|
ack_oi => ack_oi,
|
192 |
|
|
we_i => we_i,
|
193 |
|
|
vmem_stb_i => vmem_stb_i,
|
194 |
|
|
reg_stb_i => reg_stb_i,
|
195 |
|
|
adr_i => adr_i,
|
196 |
|
|
s_data => s_data,
|
197 |
|
|
s_addr => s_addr,
|
198 |
|
|
s_oen => s_oen,
|
199 |
|
|
s_wrhn => s_wrhn,
|
200 |
|
|
s_wrln => s_wrln,
|
201 |
|
|
s_cen => s_cen,
|
202 |
|
|
h_sync => h_sync,
|
203 |
|
|
h_blank => h_blank,
|
204 |
|
|
v_sync => v_sync,
|
205 |
|
|
v_blank => v_blank,
|
206 |
|
|
h_tc => h_tc,
|
207 |
|
|
v_tc => v_tc,
|
208 |
|
|
blank => blank,
|
209 |
|
|
video_out => video_out
|
210 |
|
|
);
|
211 |
|
|
|
212 |
|
|
-- Add your stimulus here ...
|
213 |
|
|
|
214 |
|
|
clk_en <= '1';
|
215 |
|
|
-- Add your stimulus here ...
|
216 |
|
|
clock: process is
|
217 |
|
|
begin
|
218 |
|
|
wait for 25 ns;
|
219 |
|
|
clk_i <= '1';
|
220 |
|
|
wait for 25 ns;
|
221 |
|
|
clk_i <= '0';
|
222 |
|
|
end process;
|
223 |
|
|
|
224 |
|
|
ack_oi <= '0';
|
225 |
|
|
dat_oi <= (others => '0');
|
226 |
|
|
|
227 |
|
|
setup: process is
|
228 |
|
|
begin
|
229 |
|
|
we_i <= '0';
|
230 |
|
|
reg_stb_i <= '0';
|
231 |
|
|
vmem_stb_i <= '0';
|
232 |
|
|
rst_i <= '1';
|
233 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
234 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
235 |
|
|
rst_i <= '0';
|
236 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
237 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
238 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
239 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
240 |
|
|
|
241 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
|
242 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
|
243 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
|
244 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
|
245 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
|
246 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
|
247 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
|
248 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
|
249 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
|
250 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
|
251 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
|
252 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
|
253 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
|
254 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
|
255 |
|
|
write_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
|
256 |
|
|
|
257 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
258 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
259 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
260 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
261 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
262 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
263 |
|
|
wait until clk_i'EVENT and clk_i = '1';
|
264 |
|
|
|
265 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total0 ,val_total0);
|
266 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total1 ,val_total1);
|
267 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_total2 ,val_total2);
|
268 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_fifo_treshold ,val_fifo_treshold);
|
269 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hbs ,val_hbs);
|
270 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hss ,val_hss);
|
271 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_hse ,val_hse);
|
272 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_htotal ,val_htotal);
|
273 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vbs ,val_vbs);
|
274 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vss ,val_vss);
|
275 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vse ,val_vse);
|
276 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_vtotal ,val_vtotal);
|
277 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_pps ,val_pps);
|
278 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_ws ,val_ws);
|
279 |
|
|
chk_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,reg_stb_i,ack_o,reg_bpp ,val_bpp);
|
280 |
|
|
|
281 |
|
|
wait;
|
282 |
|
|
end process;
|
283 |
|
|
|
284 |
|
|
s_ram: process is
|
285 |
|
|
begin
|
286 |
|
|
wait on s_data,s_addr,s_oen,s_wrhn,s_wrln,s_cen;
|
287 |
|
|
if (s_cen = '0') then
|
288 |
|
|
if (s_oen = '0') then
|
289 |
|
|
s_data <= s_addr(v_mem_width-1 downto 0);
|
290 |
|
|
elsif (s_wrhn = '0' or s_wrln = '0') then
|
291 |
|
|
if (s_wrhn = '0') then
|
292 |
|
|
else
|
293 |
|
|
end if;
|
294 |
|
|
else
|
295 |
|
|
s_data <= (others => 'Z');
|
296 |
|
|
end if;
|
297 |
|
|
end if;
|
298 |
|
|
end process;
|
299 |
|
|
|
300 |
|
|
end TB;
|
301 |
|
|
|
302 |
|
|
configuration TB_vga_chip of vga_chip_tb is
|
303 |
|
|
for TB
|
304 |
|
|
for UUT : vga_chip
|
305 |
|
|
use entity work.vga_chip(vga_chip);
|
306 |
|
|
end for;
|
307 |
|
|
end for;
|
308 |
|
|
end TB_vga_chip;
|
309 |
|
|
|