URL https://opencores.org/ocsvn/wb_vga/wb_vga/trunk

Subversion Repositories wb_vga

[/] [wb_vga/] [trunk/] [wb_tk/] [TestBench/] [wb_out_reg_TB.vhd] - Blame information for rev 8

Details | Compare with Previous | View Log


--
-- A test bench for 32-bit access
--
 
library ieee,wb_tk;
use ieee.std_logic_1164.all;
use wb_tk.technology.all;
use wb_tk.wb_test.all;
 
entity wb_out_reg_tb_32 is
        -- Generic declarations of the tested unit
        generic(
                width : POSITIVE := 16;
                bus_width : POSITIVE := 32;
                offset : INTEGER := 4 );
end wb_out_reg_tb_32;
 
architecture TB of wb_out_reg_tb_32 is
        -- Component declaration of the tested unit
        component wb_out_reg
                generic(
                        width : POSITIVE := width;
                        bus_width : POSITIVE := bus_width;
                        offset : INTEGER := offset );
                port (
                        clk_i: in std_logic;
                        rst_i: in std_logic;
                        rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
 
                cyc_i: in std_logic := '1';
                        stb_i: in std_logic;
                sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
                        we_i: in std_logic;
                        ack_o: out std_logic;
                        ack_oi: in std_logic := '-';
                adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
                        dat_i: in std_logic_vector (bus_width-1 downto 0);
                        dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
                        dat_o: out std_logic_vector (bus_width-1 downto 0);
                        q: out std_logic_vector (width-1 downto 0)
                );
        end component;
 
        -- Stimulus signals - signals mapped to the input and inout ports of tested entity
        signal adr_i : std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
        signal clk_i : std_logic;
        signal rst_i : std_logic;
        signal rst_val : std_logic_vector((width-1) downto 0) := (others => '0');
        signal cyc_i : std_logic;
        signal stb_i : std_logic;
        signal sel_i : std_logic_vector(((bus_width/8)-1) downto 0) := (others => '1');
        signal we_i : std_logic;
        signal ack_oi : std_logic;
        signal dat_i : std_logic_vector((bus_width-1) downto 0);
        signal dat_oi : std_logic_vector((bus_width-1) downto 0);
        -- Observed signals - signals mapped to the output ports of tested entity
        signal ack_o : std_logic;
        signal dat_o : std_logic_vector((bus_width-1) downto 0);
        signal q : std_logic_vector((width-1) downto 0);
 
        -- Add your code here ...
 
begin
        rst_val <= (others => '0');
        ack_oi <= 'U';
        dat_oi <= (others => 'U');
 
        -- Unit Under Test port map
        UUT : wb_out_reg
                port map
                        (clk_i => clk_i,
                        rst_i => rst_i,
                        rst_val => rst_val,
                        cyc_i => cyc_i,
                        stb_i => stb_i,
                        sel_i => sel_i,
                        we_i => we_i,
                        ack_o => ack_o,
                        ack_oi => ack_oi,
                        adr_i => adr_i,
                        dat_i => dat_i,
                        dat_oi => dat_oi,
                        dat_o => dat_o,
                        q => q );
 
        clk: process is
        begin
                clk_i <= '0';
                wait for 25ns;
                clk_i <= '1';
                wait for 25ns;
        end process;
 
        reset: process is
        begin
                rst_i <= '1';
                wait for 150ns;
                rst_i <= '0';
                wait;
        end process;
 
        master: process is
        begin
                we_i <= '0';
                cyc_i <= '0';
                stb_i <= '0';
                adr_i <= (others => '0');
                dat_i <= (others => '0');
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
 
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","00000000000000000000000000000000");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","00000000000000000000000000000000");
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","11111111111111111111111111111111");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","11111111111111111111111111111111");
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","01110110010101000011001000010000");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","01110110010101000011001000010000");
 
                sel_i <= add_one(sel_i);
--              if (sel_i = "1111") then wait; end if;
        end process;
end TB;
 
configuration TB_wb_out_reg_32 of wb_out_reg_tb_32 is
        for TB
                for UUT : wb_out_reg
                        use entity work.wb_out_reg(wb_out_reg);
                end for;
        end for;
end TB_wb_out_reg_32;
 
 
 
--
-- A test bench for 16-bit access
--
 
 
library ieee,wb_tk;
use ieee.std_logic_1164.all;
use wb_tk.technology.all;
use wb_tk.wb_test.all;
 
entity wb_out_reg_tb_16 is
        -- Generic declarations of the tested unit
        generic(
                width : POSITIVE := 16;
                bus_width : POSITIVE := 16;
                offset : INTEGER := 4 );
end wb_out_reg_tb_16;
 
architecture TB of wb_out_reg_tb_16 is
        -- Component declaration of the tested unit
        component wb_out_reg
                generic(
                        width : POSITIVE := width;
                        bus_width : POSITIVE := bus_width;
                        offset : INTEGER := offset );
                port (
                        clk_i: in std_logic;
                        rst_i: in std_logic;
                        rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
 
                cyc_i: in std_logic := '1';
                        stb_i: in std_logic;
                sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
                        we_i: in std_logic;
                        ack_o: out std_logic;
                        ack_oi: in std_logic := '-';
                        adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0');
                        dat_i: in std_logic_vector (bus_width-1 downto 0);
                        dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
                        dat_o: out std_logic_vector (bus_width-1 downto 0);
                        q: out std_logic_vector (width-1 downto 0)
                );
        end component;
 
        signal adr_i : std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0');
        -- Stimulus signals - signals mapped to the input and inout ports of tested entity
        signal clk_i : std_logic;
        signal rst_i : std_logic;
        signal rst_val : std_logic_vector((width-1) downto 0) := (others => '0');
        signal cyc_i : std_logic;
        signal stb_i : std_logic;
        signal sel_i : std_logic_vector(((bus_width/8)-1) downto 0) := (others => '1');
        signal we_i : std_logic;
        signal ack_oi : std_logic;
        signal dat_i : std_logic_vector((bus_width-1) downto 0);
        signal dat_oi : std_logic_vector((bus_width-1) downto 0);
        -- Observed signals - signals mapped to the output ports of tested entity
        signal ack_o : std_logic;
        signal dat_o : std_logic_vector((bus_width-1) downto 0);
        signal q : std_logic_vector((width-1) downto 0);
 
        -- Add your code here ...
 
begin
        rst_val <= (others => '0');
        ack_oi <= 'U';
        dat_oi <= (others => 'U');
 
        -- Unit Under Test port map
        UUT : wb_out_reg
                port map
                        (clk_i => clk_i,
                        rst_i => rst_i,
                        rst_val => rst_val,
                        cyc_i => cyc_i,
                        stb_i => stb_i,
                        sel_i => sel_i,
                        we_i => we_i,
                        ack_o => ack_o,
                        ack_oi => ack_oi,
                        adr_i => adr_i,
                        dat_i => dat_i,
                        dat_oi => dat_oi,
                        dat_o => dat_o,
                        q => q );
 
        clk: process is
        begin
                clk_i <= '0';
                wait for 25ns;
                clk_i <= '1';
                wait for 25ns;
        end process;
 
        reset: process is
        begin
                rst_i <= '1';
                wait for 150ns;
                rst_i <= '0';
                wait;
        end process;
 
        master: process is
        begin
                we_i <= '0';
                cyc_i <= '0';
                stb_i <= '0';
                adr_i <= (others => '0');
                dat_i <= (others => '0');
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
                wait until clk_i'EVENT and clk_i = '1';
 
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0000000000000000");
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0000000000000000");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0000000000000000");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0000000000000000");
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","1111111111111111");
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","1111111111111111");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","1111111111111111");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","1111111111111111");
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0111011001010100");
                wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0011001000010000");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0111011001010100");
                rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0011001000010000");
 
                sel_i <= add_one(sel_i);
        end process;
end TB;
 
configuration TB_wb_out_reg_16 of wb_out_reg_tb_16 is
        for TB
                for UUT : wb_out_reg
                        use entity work.wb_out_reg(wb_out_reg);
                end for;
        end for;
end TB_wb_out_reg_16;

Browse

Tools

Subversion Repositories wb_vga

[/] [wb_vga/] [trunk/] [wb_tk/] [TestBench/] [wb_out_reg_TB.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	7	tantos	`--`
2			`-- A test bench for 32-bit access`
3			`--`
4
5			`library ieee,wb_tk;`
6			`use ieee.std_logic_1164.all;`
7			`use wb_tk.technology.all;`
8			`use wb_tk.wb_test.all;`
9
10			`entity wb_out_reg_tb_32 is`
11			`-- Generic declarations of the tested unit`
12			`generic(`
13			`width : POSITIVE := 16;`
14			`bus_width : POSITIVE := 32;`
15			`offset : INTEGER := 4 );`
16			`end wb_out_reg_tb_32;`
17
18			`architecture TB of wb_out_reg_tb_32 is`
19			`-- Component declaration of the tested unit`
20			`component wb_out_reg`
21			`generic(`
22			`width : POSITIVE := width;`
23			`bus_width : POSITIVE := bus_width;`
24			`offset : INTEGER := offset );`
25			`port (`
26			`clk_i: in std_logic;`
27			`rst_i: in std_logic;`
28			`rst_val: std_logic_vector(width-1 downto 0) := (others => '0');`
29
30			`cyc_i: in std_logic := '1';`
31			`stb_i: in std_logic;`
32			`sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');`
33			`we_i: in std_logic;`
34			`ack_o: out std_logic;`
35			`ack_oi: in std_logic := '-';`
36			`adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');`
37			`dat_i: in std_logic_vector (bus_width-1 downto 0);`
38			`dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');`
39			`dat_o: out std_logic_vector (bus_width-1 downto 0);`
40			`q: out std_logic_vector (width-1 downto 0)`
41			`);`
42			`end component;`
43
44			`-- Stimulus signals - signals mapped to the input and inout ports of tested entity`
45			`signal adr_i : std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');`
46			`signal clk_i : std_logic;`
47			`signal rst_i : std_logic;`
48			`signal rst_val : std_logic_vector((width-1) downto 0) := (others => '0');`
49			`signal cyc_i : std_logic;`
50			`signal stb_i : std_logic;`
51			`signal sel_i : std_logic_vector(((bus_width/8)-1) downto 0) := (others => '1');`
52			`signal we_i : std_logic;`
53			`signal ack_oi : std_logic;`
54			`signal dat_i : std_logic_vector((bus_width-1) downto 0);`
55			`signal dat_oi : std_logic_vector((bus_width-1) downto 0);`
56			`-- Observed signals - signals mapped to the output ports of tested entity`
57			`signal ack_o : std_logic;`
58			`signal dat_o : std_logic_vector((bus_width-1) downto 0);`
59			`signal q : std_logic_vector((width-1) downto 0);`
60
61			`-- Add your code here ...`
62
63			`begin`
64			`rst_val <= (others => '0');`
65			`ack_oi <= 'U';`
66			`dat_oi <= (others => 'U');`
67
68			`-- Unit Under Test port map`
69			`UUT : wb_out_reg`
70			`port map`
71			`(clk_i => clk_i,`
72			`rst_i => rst_i,`
73			`rst_val => rst_val,`
74			`cyc_i => cyc_i,`
75			`stb_i => stb_i,`
76			`sel_i => sel_i,`
77			`we_i => we_i,`
78			`ack_o => ack_o,`
79			`ack_oi => ack_oi,`
80			`adr_i => adr_i,`
81			`dat_i => dat_i,`
82			`dat_oi => dat_oi,`
83			`dat_o => dat_o,`
84			`q => q );`
85
86			`clk: process is`
87			`begin`
88			`clk_i <= '0';`
89			`wait for 25ns;`
90			`clk_i <= '1';`
91			`wait for 25ns;`
92			`end process;`
93
94			`reset: process is`
95			`begin`
96			`rst_i <= '1';`
97			`wait for 150ns;`
98			`rst_i <= '0';`
99			`wait;`
100			`end process;`
101
102			`master: process is`
103			`begin`
104			`we_i <= '0';`
105			`cyc_i <= '0';`
106			`stb_i <= '0';`
107			`adr_i <= (others => '0');`
108			`dat_i <= (others => '0');`
109			`wait until clk_i'EVENT and clk_i = '1';`
110			`wait until clk_i'EVENT and clk_i = '1';`
111			`wait until clk_i'EVENT and clk_i = '1';`
112			`wait until clk_i'EVENT and clk_i = '1';`
113			`wait until clk_i'EVENT and clk_i = '1';`
114			`wait until clk_i'EVENT and clk_i = '1';`
115			`wait until clk_i'EVENT and clk_i = '1';`
116
117			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","00000000000000000000000000000000");`
118			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","00000000000000000000000000000000");`
119			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","11111111111111111111111111111111");`
120			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","11111111111111111111111111111111");`
121			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","01110110010101000011001000010000");`
122			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","01110110010101000011001000010000");`
123
124			`sel_i <= add_one(sel_i);`
125			`-- if (sel_i = "1111") then wait; end if;`
126			`end process;`
127			`end TB;`
128
129			`configuration TB_wb_out_reg_32 of wb_out_reg_tb_32 is`
130			`for TB`
131			`for UUT : wb_out_reg`
132			`use entity work.wb_out_reg(wb_out_reg);`
133			`end for;`
134			`end for;`
135			`end TB_wb_out_reg_32;`
136
137
138
139			`--`
140			`-- A test bench for 16-bit access`
141			`--`
142
143
144			`library ieee,wb_tk;`
145			`use ieee.std_logic_1164.all;`
146			`use wb_tk.technology.all;`
147			`use wb_tk.wb_test.all;`
148
149			`entity wb_out_reg_tb_16 is`
150			`-- Generic declarations of the tested unit`
151			`generic(`
152			`width : POSITIVE := 16;`
153			`bus_width : POSITIVE := 16;`
154			`offset : INTEGER := 4 );`
155			`end wb_out_reg_tb_16;`
156
157			`architecture TB of wb_out_reg_tb_16 is`
158			`-- Component declaration of the tested unit`
159			`component wb_out_reg`
160			`generic(`
161			`width : POSITIVE := width;`
162			`bus_width : POSITIVE := bus_width;`
163			`offset : INTEGER := offset );`
164			`port (`
165			`clk_i: in std_logic;`
166			`rst_i: in std_logic;`
167			`rst_val: std_logic_vector(width-1 downto 0) := (others => '0');`
168
169			`cyc_i: in std_logic := '1';`
170			`stb_i: in std_logic;`
171			`sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');`
172			`we_i: in std_logic;`
173			`ack_o: out std_logic;`
174			`ack_oi: in std_logic := '-';`
175			`adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0');`
176			`dat_i: in std_logic_vector (bus_width-1 downto 0);`
177			`dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');`
178			`dat_o: out std_logic_vector (bus_width-1 downto 0);`
179			`q: out std_logic_vector (width-1 downto 0)`
180			`);`
181			`end component;`
182
183			`signal adr_i : std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0');`
184			`-- Stimulus signals - signals mapped to the input and inout ports of tested entity`
185			`signal clk_i : std_logic;`
186			`signal rst_i : std_logic;`
187			`signal rst_val : std_logic_vector((width-1) downto 0) := (others => '0');`
188			`signal cyc_i : std_logic;`
189			`signal stb_i : std_logic;`
190			`signal sel_i : std_logic_vector(((bus_width/8)-1) downto 0) := (others => '1');`
191			`signal we_i : std_logic;`
192			`signal ack_oi : std_logic;`
193			`signal dat_i : std_logic_vector((bus_width-1) downto 0);`
194			`signal dat_oi : std_logic_vector((bus_width-1) downto 0);`
195			`-- Observed signals - signals mapped to the output ports of tested entity`
196			`signal ack_o : std_logic;`
197			`signal dat_o : std_logic_vector((bus_width-1) downto 0);`
198			`signal q : std_logic_vector((width-1) downto 0);`
199
200			`-- Add your code here ...`
201
202			`begin`
203			`rst_val <= (others => '0');`
204			`ack_oi <= 'U';`
205			`dat_oi <= (others => 'U');`
206
207			`-- Unit Under Test port map`
208			`UUT : wb_out_reg`
209			`port map`
210			`(clk_i => clk_i,`
211			`rst_i => rst_i,`
212			`rst_val => rst_val,`
213			`cyc_i => cyc_i,`
214			`stb_i => stb_i,`
215			`sel_i => sel_i,`
216			`we_i => we_i,`
217			`ack_o => ack_o,`
218			`ack_oi => ack_oi,`
219			`adr_i => adr_i,`
220			`dat_i => dat_i,`
221			`dat_oi => dat_oi,`
222			`dat_o => dat_o,`
223			`q => q );`
224
225			`clk: process is`
226			`begin`
227			`clk_i <= '0';`
228			`wait for 25ns;`
229			`clk_i <= '1';`
230			`wait for 25ns;`
231			`end process;`
232
233			`reset: process is`
234			`begin`
235			`rst_i <= '1';`
236			`wait for 150ns;`
237			`rst_i <= '0';`
238			`wait;`
239			`end process;`
240
241			`master: process is`
242			`begin`
243			`we_i <= '0';`
244			`cyc_i <= '0';`
245			`stb_i <= '0';`
246			`adr_i <= (others => '0');`
247			`dat_i <= (others => '0');`
248			`wait until clk_i'EVENT and clk_i = '1';`
249			`wait until clk_i'EVENT and clk_i = '1';`
250			`wait until clk_i'EVENT and clk_i = '1';`
251			`wait until clk_i'EVENT and clk_i = '1';`
252			`wait until clk_i'EVENT and clk_i = '1';`
253			`wait until clk_i'EVENT and clk_i = '1';`
254			`wait until clk_i'EVENT and clk_i = '1';`
255
256			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0000000000000000");`
257			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0000000000000000");`
258			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0000000000000000");`
259			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0000000000000000");`
260			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","1111111111111111");`
261			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","1111111111111111");`
262			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","1111111111111111");`
263			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","1111111111111111");`
264			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0111011001010100");`
265			`wr_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0011001000010000");`
266			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"1","0111011001010100");`
267			`rd_val(clk_i, adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,"0","0011001000010000");`
268
269			`sel_i <= add_one(sel_i);`
270			`end process;`
271			`end TB;`
272
273			`configuration TB_wb_out_reg_16 of wb_out_reg_tb_16 is`
274			`for TB`
275			`for UUT : wb_out_reg`
276			`use entity work.wb_out_reg(wb_out_reg);`
277			`end for;`
278			`end for;`
279			`end TB_wb_out_reg_16;`