URL https://opencores.org/ocsvn/wb_vga/wb_vga/trunk

Subversion Repositories wb_vga

[/] [wb_vga/] [trunk/] [wb_tk/] [technology.vhd] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log


--
--  Technology mapping library. ALTERA edition.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
 
library IEEE;
use IEEE.std_logic_1164.all;
library exemplar;
use exemplar.exemplar_1164.all;
 
package technology is
        function add_one(inp : std_logic_vector) return std_logic_vector;
        function is_zero(inp : std_logic_vector) return boolean;
    function sl(l: std_logic_vector; r: integer) return std_logic_vector;
--      procedure inc(data : inout std_logic_vector);
    function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;
        function log2(inp : integer) return integer;
        function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer;
        function size2bits(inp : integer) return integer;
        function max(a : integer; b: integer) return integer;
        function min2(a : integer; b: integer) return integer;
        function equ(a : std_logic_vector; b : integer) return boolean;
 
        component d_ff is
                port (  d  :  in STD_LOGIC;
                                clk:  in STD_LOGIC;
                        ena:  in STD_LOGIC := '1';
                        clr:  in STD_LOGIC := '0';
                        pre:  in STD_LOGIC := '0';
                                q  :  out STD_LOGIC
                );
        end component;
        component fifo is
                generic (fifo_width : positive;
                                 used_width : positive;
                                 fifo_depth : positive
                );
                port (d_in : in std_logic_vector(fifo_width-1 downto 0);
                          clk : in std_logic;
                          wr : in std_logic;
                          rd : in std_logic;
                          a_clr : in std_logic := '0';
                          s_clr : in std_logic := '0';
                          d_out : out std_logic_vector(fifo_width-1 downto 0);
                          used : out std_logic_vector(used_width-1 downto 0);
                          full : out std_logic;
                          empty : out std_logic
                );
        end component;
end technology;
 
library IEEE;
use IEEE.std_logic_1164.all;
library exemplar;
use exemplar.exemplar_1164.all;
library synopsys;
use synopsys.std_logic_arith.all;
 
package body technology is
    function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
        begin
                return exemplar_1164."+"(op_l, op_r);
        end;
 
        function add_one(inp : std_logic_vector) return std_logic_vector is
                variable one: std_logic_vector(inp'RANGE) := (others => '0');
        begin
                one(0) := '1';
                return exemplar_1164."+"(inp,one);
        end;
 
        function is_zero(inp : std_logic_vector) return boolean is
                variable zero: std_logic_vector(inp'RANGE) := (others => '0');
        begin
                return (inp = zero);
        end;
 
    function sl(l: std_logic_vector; r: integer) return std_logic_vector is
    begin
        return exemplar_1164.sl(l,r);
    end;
--      procedure inc(data : inout std_logic_vector) is
--      begin
--              data := addone(data);
--      end;
        function max(a : integer; b: integer) return integer is
        begin
            if (a > b) then return a; end if;
            return b;
        end;
 
        function min2(a : integer; b: integer) return integer is
        begin
            if (a < b) then return a; end if;
            return b;
        end;
 
        function log2(inp : integer) return integer is
        begin
                if (inp < 1) then return 0; end if;
                if (inp < 2) then return 0; end if;
                if (inp < 4) then return 1; end if;
                if (inp < 8) then return 2; end if;
                if (inp < 16) then return 3; end if;
                if (inp < 32) then return 4; end if;
                if (inp < 64) then return 5; end if;
                if (inp < 128) then return 6; end if;
                if (inp < 256) then return 7; end if;
                if (inp < 512) then return 8; end if;
                if (inp < 1024) then return 9; end if;
                if (inp < 2048) then return 10; end if;
                if (inp < 4096) then return 11; end if;
                if (inp < 8192) then return 12; end if;
                if (inp < 16384) then return 13; end if;
                if (inp < 32768) then return 14; end if;
                if (inp < 65538) then return 15; end if;
                return 16;
        end;
 
        function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is
        begin
            if (in_bus = out_bus) then return 0; end if;
            if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if;
            if (in_bus > out_bus) then return log2(in_bus/out_bus); end if;
        end;
 
        function size2bits(inp : integer) return integer is
        begin
                if (inp < 1) then return 1; end if;
                if (inp < 2) then return 1; end if;
                if (inp < 4) then return 2; end if;
                if (inp < 8) then return 3; end if;
                if (inp < 16) then return 4; end if;
                if (inp < 32) then return 5; end if;
                if (inp < 64) then return 6; end if;
                if (inp < 128) then return 7; end if;
                if (inp < 256) then return 8; end if;
                if (inp < 512) then return 9; end if;
                if (inp < 1024) then return 10; end if;
                if (inp < 2048) then return 11; end if;
                if (inp < 4096) then return 12; end if;
                if (inp < 8192) then return 13; end if;
                if (inp < 16384) then return 14; end if;
                if (inp < 32768) then return 15; end if;
                if (inp < 65538) then return 16; end if;
                return 17;
        end;
 
        function equ(a : std_logic_vector; b : integer) return boolean is
                variable b_s : std_logic_vector(a'RANGE);
        begin
                b_s := CONV_STD_LOGIC_VECTOR(b,a'HIGH+1);
                return (a = b_s);
        end;
 
end package body technology;
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library exemplar;
use exemplar.exemplar_1164.all;
 
library lpm;
use lpm.all;
 
entity fifo is
        generic (fifo_width : positive;
                         used_width : positive;
                         fifo_depth : positive
        );
        port (d_in : in std_logic_vector(fifo_width-1 downto 0);
                  clk : in std_logic;
                  wr : in std_logic;
                  rd : in std_logic;
                  a_clr : in std_logic := '0';
                  s_clr : in std_logic := '0';
                  d_out : out std_logic_vector(fifo_width-1 downto 0);
                  used : out std_logic_vector(used_width-1 downto 0);
                  full : out std_logic;
                  empty : out std_logic
        );
end fifo;
 
architecture altera of fifo is
        component lpm_fifo
                generic (LPM_WIDTH : positive;
                                 LPM_WIDTHU : positive;
                                 LPM_NUMWORDS : positive;
                                 LPM_SHOWAHEAD : string := "OFF";
                                 LPM_TYPE : string := "LPM_FIFO";
                                 LPM_HINT : string := "UNUSED");
                port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                          CLOCK : in std_logic;
                          WRREQ : in std_logic;
                          RDREQ : in std_logic;
                          ACLR : in std_logic;
                          SCLR : in std_logic;
                          Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
                          USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
                          FULL : out std_logic;
                          EMPTY : out std_logic);
        end component;
begin
        altera_fifo: lpm_fifo
                generic map (
                        LPM_WIDTH => fifo_width,
                        LPM_WIDTHU => used_width,
                        LPM_NUMWORDS => fifo_depth,
                        LPM_SHOWAHEAD => "OFF",
                        LPM_TYPE => "LPM_FIFO",
                        LPM_HINT => "UNUSED"
                )
                port map (
                        DATA => d_in,
                        CLOCK => clk,
                        WRREQ => wr,
                        RDREQ => rd,
                        ACLR => a_clr,
                        SCLR => s_clr,
                        Q => d_out,
                        USEDW => used,
                        FULL => full,
                        EMPTY => empty
                );
end altera;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library exemplar;
use exemplar.exemplar_1164.all;
 
library lpm;
use lpm.all;
 
entity ram is
        generic (
                data_width : positive;
                addr_width : positive
        );
        port (
                clk : in std_logic;
                we : in std_logic;
                addr : in std_logic_vector(addr_width-1 downto 0);
                d_in : in std_logic_vector(data_width-1 downto 0);
                d_out : out std_logic_vector(data_width-1 downto 0)
        );
end ram;
 
architecture altera of ram is
        component lpm_ram_dp
                generic (
                        lpm_width: positive;
                        lpm_widthad: positive;
                        lpm_numwords: natural := 0;
                        lpm_type: string := "lpm_ram_dp";
                        lpm_indata: string := "REGISTERED";
                        lpm_outdata: string := "UNREGISTERED";
                        lpm_rdaddress_control: string := "REGISTERED";
                        lpm_wraddress_control: string := "REGISTERED";
                        lpm_file: string := "UNUSED";
                        lpm_hint: string := "UNUSED"
                );
                port (
                        rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0);
                        rdclock, wrclock: in std_logic := '0';
                        rden, rdclken, wrclken: in std_logic := '1';
                        wren: in std_logic;
                        data: in std_logic_vector(lpm_width-1 downto 0);
                        q: out std_logic_vector(lpm_width-1 downto 0)
                );
        end component;
begin
        altera_ram: lpm_ram_dp
                generic map (
                        lpm_width => data_width,
                        lpm_widthad => addr_width,
                        lpm_numwords => 2 ** addr_width,
                        lpm_type => "lpm_ram_dp",
                        lpm_indata => "REGISTERED",
                        lpm_wraddress_control => "REGISTERED",
                        lpm_outdata => "UNREGISTERED",
                        lpm_rdaddress_control => "UNREGISTERED",
                        lpm_file => "UNUSED",
                        lpm_hint => "UNUSED"
                )
                port map (
--                      rdclock => clk,
                        rdclken => '1',
                        rdaddress => addr,
                        q => d_out,
                        rden => '1',
 
                        wrclock => clk,
                        wrclken => '1',
                        wraddress => addr,
                        data => d_in,
                        wren => we
                );
end altera;
 
 
 
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library exemplar;
use exemplar.exemplar_1164.all;
 
library lpm;
use lpm.all;
 
entity dpram is
        generic (
                data_width : positive;
                addr_width : positive
        );
        port (
                clk : in std_logic;
 
                r_d_out : out std_logic_vector(data_width-1 downto 0);
                r_rd : in std_logic;
                r_clk_en : in std_logic;
                r_addr : in std_logic_vector(addr_width-1 downto 0);
 
                w_d_in : in std_logic_vector(data_width-1 downto 0);
                w_wr : in std_logic;
                w_clk_en : in std_logic;
                w_addr : in std_logic_vector(addr_width-1 downto 0)
        );
end dpram;
 
architecture altera of dpram is
        component lpm_ram_dp
                generic (
                        lpm_width: positive;
                        lpm_widthad: positive;
                        lpm_numwords: natural := 0;
                        lpm_type: string := "lpm_ram_dp";
                        lpm_indata: string := "REGISTERED";
                        lpm_outdata: string := "UNREGISTERED";
                        lpm_rdaddress_control: string := "REGISTERED";
                        lpm_wraddress_control: string := "REGISTERED";
                        lpm_file: string := "UNUSED";
                        lpm_hint: string := "UNUSED"
                );
                port (
                        rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0);
                        rdclock, wrclock: in std_logic := '0';
                        rden, rdclken, wrclken: in std_logic := '1';
                        wren: in std_logic;
                        data: in std_logic_vector(lpm_width-1 downto 0);
                        q: out std_logic_vector(lpm_width-1 downto 0)
                );
        end component;
begin
        altera_ram: lpm_ram_dp
                generic map (
                        lpm_width => data_width,
                        lpm_widthad => addr_width,
                        lpm_numwords => 2 ** addr_width,
                        lpm_type => "lpm_ram_dp",
                        lpm_indata => "REGISTERED",
                        lpm_wraddress_control => "REGISTERED",
                        lpm_outdata => "UNREGISTERED",
                        lpm_rdaddress_control => "UNREGISTERED",
                        lpm_file => "UNUSED",
                        lpm_hint => "UNUSED"
                )
                port map (
--                      rdclock => clk,
                        rdclken => r_clk_en,
                        rdaddress => r_addr,
                        q => r_d_out,
                        rden => r_rd,
 
                        wrclock => clk,
                        wrclken => w_clk_en,
                        wraddress => w_addr,
                        data => w_d_in,
                        wren => w_wr
                );
end altera;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
library altera_exemplar;
use altera_exemplar.all;
 
entity d_ff is
        port (  d  :  in STD_LOGIC;
                        clk:  in STD_LOGIC;
                ena:  in STD_LOGIC := '1';
                clr:  in STD_LOGIC := '0';
                pre:  in STD_LOGIC := '0';
                        q  :  out STD_LOGIC
        );
end d_ff;
 
architecture altera of d_ff is
        component dffe
        port (  D  :  in STD_LOGIC;
                        CLK:  in STD_LOGIC;
                ENA:  in STD_LOGIC;
                CLRN: in STD_LOGIC;
                PRN:  in STD_LOGIC;
                        Q  :  out STD_LOGIC);
        end component;
        signal clrn,prn: std_logic;
begin
        clrn <= not clr;
        prn <= not pre;
        ff: dffe port map (
                D => d,
                CLK => clk,
                ENA => ena,
                CLRN => clrn,
                PRN => prn,
                Q => q
        );
end altera;
 
-- Sythetizer library. Contains STD_LOGIC arithmetics
 

Browse

Tools

Subversion Repositories wb_vga

[/] [wb_vga/] [trunk/] [wb_tk/] [technology.vhd] - Blame information for rev 10

Line No.	Rev	Author	Line
1	7	tantos	`--`
2			`-- Technology mapping library. ALTERA edition.`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7
8			`library IEEE;`
9			`use IEEE.std_logic_1164.all;`
10			`library exemplar;`
11			`use exemplar.exemplar_1164.all;`
12
13			`package technology is`
14			`function add_one(inp : std_logic_vector) return std_logic_vector;`
15			`function is_zero(inp : std_logic_vector) return boolean;`
16			`function sl(l: std_logic_vector; r: integer) return std_logic_vector;`
17			`-- procedure inc(data : inout std_logic_vector);`
18			`function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;`
19			`function log2(inp : integer) return integer;`
20			`function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer;`
21			`function size2bits(inp : integer) return integer;`
22			`function max(a : integer; b: integer) return integer;`
23			`function min2(a : integer; b: integer) return integer;`
24			`function equ(a : std_logic_vector; b : integer) return boolean;`
25
26			`component d_ff is`
27			`port ( d : in STD_LOGIC;`
28			`clk: in STD_LOGIC;`
29			`ena: in STD_LOGIC := '1';`
30			`clr: in STD_LOGIC := '0';`
31			`pre: in STD_LOGIC := '0';`
32			`q : out STD_LOGIC`
33			`);`
34			`end component;`
35			`component fifo is`
36			`generic (fifo_width : positive;`
37			`used_width : positive;`
38			`fifo_depth : positive`
39			`);`
40			`port (d_in : in std_logic_vector(fifo_width-1 downto 0);`
41			`clk : in std_logic;`
42			`wr : in std_logic;`
43			`rd : in std_logic;`
44			`a_clr : in std_logic := '0';`
45			`s_clr : in std_logic := '0';`
46			`d_out : out std_logic_vector(fifo_width-1 downto 0);`
47			`used : out std_logic_vector(used_width-1 downto 0);`
48			`full : out std_logic;`
49			`empty : out std_logic`
50			`);`
51			`end component;`
52			`end technology;`
53
54			`library IEEE;`
55			`use IEEE.std_logic_1164.all;`
56			`library exemplar;`
57			`use exemplar.exemplar_1164.all;`
58			`library synopsys;`
59			`use synopsys.std_logic_arith.all;`
60
61			`package body technology is`
62			`function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is`
63			`begin`
64			`return exemplar_1164."+"(op_l, op_r);`
65			`end;`
66
67			`function add_one(inp : std_logic_vector) return std_logic_vector is`
68			`variable one: std_logic_vector(inp'RANGE) := (others => '0');`
69			`begin`
70			`one(0) := '1';`
71			`return exemplar_1164."+"(inp,one);`
72			`end;`
73
74			`function is_zero(inp : std_logic_vector) return boolean is`
75			`variable zero: std_logic_vector(inp'RANGE) := (others => '0');`
76			`begin`
77			`return (inp = zero);`
78			`end;`
79
80			`function sl(l: std_logic_vector; r: integer) return std_logic_vector is`
81			`begin`
82			`return exemplar_1164.sl(l,r);`
83			`end;`
84			`-- procedure inc(data : inout std_logic_vector) is`
85			`-- begin`
86			`-- data := addone(data);`
87			`-- end;`
88			`function max(a : integer; b: integer) return integer is`
89			`begin`
90			`if (a > b) then return a; end if;`
91			`return b;`
92			`end;`
93
94			`function min2(a : integer; b: integer) return integer is`
95			`begin`
96			`if (a < b) then return a; end if;`
97			`return b;`
98			`end;`
99
100			`function log2(inp : integer) return integer is`
101			`begin`
102			`if (inp < 1) then return 0; end if;`
103			`if (inp < 2) then return 0; end if;`
104			`if (inp < 4) then return 1; end if;`
105			`if (inp < 8) then return 2; end if;`
106			`if (inp < 16) then return 3; end if;`
107			`if (inp < 32) then return 4; end if;`
108			`if (inp < 64) then return 5; end if;`
109			`if (inp < 128) then return 6; end if;`
110			`if (inp < 256) then return 7; end if;`
111			`if (inp < 512) then return 8; end if;`
112			`if (inp < 1024) then return 9; end if;`
113			`if (inp < 2048) then return 10; end if;`
114			`if (inp < 4096) then return 11; end if;`
115			`if (inp < 8192) then return 12; end if;`
116			`if (inp < 16384) then return 13; end if;`
117			`if (inp < 32768) then return 14; end if;`
118			`if (inp < 65538) then return 15; end if;`
119			`return 16;`
120			`end;`
121
122			`function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is`
123			`begin`
124			`if (in_bus = out_bus) then return 0; end if;`
125			`if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if;`
126			`if (in_bus > out_bus) then return log2(in_bus/out_bus); end if;`
127			`end;`
128
129			`function size2bits(inp : integer) return integer is`
130			`begin`
131			`if (inp < 1) then return 1; end if;`
132			`if (inp < 2) then return 1; end if;`
133			`if (inp < 4) then return 2; end if;`
134			`if (inp < 8) then return 3; end if;`
135			`if (inp < 16) then return 4; end if;`
136			`if (inp < 32) then return 5; end if;`
137			`if (inp < 64) then return 6; end if;`
138			`if (inp < 128) then return 7; end if;`
139			`if (inp < 256) then return 8; end if;`
140			`if (inp < 512) then return 9; end if;`
141			`if (inp < 1024) then return 10; end if;`
142			`if (inp < 2048) then return 11; end if;`
143			`if (inp < 4096) then return 12; end if;`
144			`if (inp < 8192) then return 13; end if;`
145			`if (inp < 16384) then return 14; end if;`
146			`if (inp < 32768) then return 15; end if;`
147			`if (inp < 65538) then return 16; end if;`
148			`return 17;`
149			`end;`
150
151			`function equ(a : std_logic_vector; b : integer) return boolean is`
152			`variable b_s : std_logic_vector(a'RANGE);`
153			`begin`
154			`b_s := CONV_STD_LOGIC_VECTOR(b,a'HIGH+1);`
155			`return (a = b_s);`
156			`end;`
157
158			`end package body technology;`
159
160
161			`library IEEE;`
162			`use IEEE.std_logic_1164.all;`
163
164			`library exemplar;`
165			`use exemplar.exemplar_1164.all;`
166
167			`library lpm;`
168			`use lpm.all;`
169
170			`entity fifo is`
171			`generic (fifo_width : positive;`
172			`used_width : positive;`
173			`fifo_depth : positive`
174			`);`
175			`port (d_in : in std_logic_vector(fifo_width-1 downto 0);`
176			`clk : in std_logic;`
177			`wr : in std_logic;`
178			`rd : in std_logic;`
179			`a_clr : in std_logic := '0';`
180			`s_clr : in std_logic := '0';`
181			`d_out : out std_logic_vector(fifo_width-1 downto 0);`
182			`used : out std_logic_vector(used_width-1 downto 0);`
183			`full : out std_logic;`
184			`empty : out std_logic`
185			`);`
186			`end fifo;`
187
188			`architecture altera of fifo is`
189			`component lpm_fifo`
190			`generic (LPM_WIDTH : positive;`
191			`LPM_WIDTHU : positive;`
192			`LPM_NUMWORDS : positive;`
193			`LPM_SHOWAHEAD : string := "OFF";`
194			`LPM_TYPE : string := "LPM_FIFO";`
195			`LPM_HINT : string := "UNUSED");`
196			`port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);`
197			`CLOCK : in std_logic;`
198			`WRREQ : in std_logic;`
199			`RDREQ : in std_logic;`
200			`ACLR : in std_logic;`
201			`SCLR : in std_logic;`
202			`Q : out std_logic_vector(LPM_WIDTH-1 downto 0);`
203			`USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);`
204			`FULL : out std_logic;`
205			`EMPTY : out std_logic);`
206			`end component;`
207			`begin`
208			`altera_fifo: lpm_fifo`
209			`generic map (`
210			`LPM_WIDTH => fifo_width,`
211			`LPM_WIDTHU => used_width,`
212			`LPM_NUMWORDS => fifo_depth,`
213			`LPM_SHOWAHEAD => "OFF",`
214			`LPM_TYPE => "LPM_FIFO",`
215			`LPM_HINT => "UNUSED"`
216			`)`
217			`port map (`
218			`DATA => d_in,`
219			`CLOCK => clk,`
220			`WRREQ => wr,`
221			`RDREQ => rd,`
222			`ACLR => a_clr,`
223			`SCLR => s_clr,`
224			`Q => d_out,`
225			`USEDW => used,`
226			`FULL => full,`
227			`EMPTY => empty`
228			`);`
229			`end altera;`
230
231			`library IEEE;`
232			`use IEEE.std_logic_1164.all;`
233
234			`library exemplar;`
235			`use exemplar.exemplar_1164.all;`
236
237			`library lpm;`
238			`use lpm.all;`
239
240			`entity ram is`
241			`generic (`
242			`data_width : positive;`
243			`addr_width : positive`
244			`);`
245			`port (`
246			`clk : in std_logic;`
247			`we : in std_logic;`
248			`addr : in std_logic_vector(addr_width-1 downto 0);`
249			`d_in : in std_logic_vector(data_width-1 downto 0);`
250			`d_out : out std_logic_vector(data_width-1 downto 0)`
251			`);`
252			`end ram;`
253
254			`architecture altera of ram is`
255			`component lpm_ram_dp`
256			`generic (`
257			`lpm_width: positive;`
258			`lpm_widthad: positive;`
259			`lpm_numwords: natural := 0;`
260			`lpm_type: string := "lpm_ram_dp";`
261			`lpm_indata: string := "REGISTERED";`
262			`lpm_outdata: string := "UNREGISTERED";`
263			`lpm_rdaddress_control: string := "REGISTERED";`
264			`lpm_wraddress_control: string := "REGISTERED";`
265			`lpm_file: string := "UNUSED";`
266			`lpm_hint: string := "UNUSED"`
267			`);`
268			`port (`
269			`rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0);`
270			`rdclock, wrclock: in std_logic := '0';`
271			`rden, rdclken, wrclken: in std_logic := '1';`
272			`wren: in std_logic;`
273			`data: in std_logic_vector(lpm_width-1 downto 0);`
274			`q: out std_logic_vector(lpm_width-1 downto 0)`
275			`);`
276			`end component;`
277			`begin`
278			`altera_ram: lpm_ram_dp`
279			`generic map (`
280			`lpm_width => data_width,`
281			`lpm_widthad => addr_width,`
282			`lpm_numwords => 2 ** addr_width,`
283			`lpm_type => "lpm_ram_dp",`
284			`lpm_indata => "REGISTERED",`
285			`lpm_wraddress_control => "REGISTERED",`
286			`lpm_outdata => "UNREGISTERED",`
287			`lpm_rdaddress_control => "UNREGISTERED",`
288			`lpm_file => "UNUSED",`
289			`lpm_hint => "UNUSED"`
290			`)`
291			`port map (`
292			`-- rdclock => clk,`
293			`rdclken => '1',`
294			`rdaddress => addr,`
295			`q => d_out,`
296			`rden => '1',`
297
298			`wrclock => clk,`
299			`wrclken => '1',`
300			`wraddress => addr,`
301			`data => d_in,`
302			`wren => we`
303			`);`
304			`end altera;`
305
306
307
308
309
310			`library IEEE;`
311			`use IEEE.std_logic_1164.all;`
312
313			`library exemplar;`
314			`use exemplar.exemplar_1164.all;`
315
316			`library lpm;`
317			`use lpm.all;`
318
319			`entity dpram is`
320			`generic (`
321			`data_width : positive;`
322			`addr_width : positive`
323			`);`
324			`port (`
325			`clk : in std_logic;`
326
327			`r_d_out : out std_logic_vector(data_width-1 downto 0);`
328			`r_rd : in std_logic;`
329			`r_clk_en : in std_logic;`
330			`r_addr : in std_logic_vector(addr_width-1 downto 0);`
331
332			`w_d_in : in std_logic_vector(data_width-1 downto 0);`
333			`w_wr : in std_logic;`
334			`w_clk_en : in std_logic;`
335			`w_addr : in std_logic_vector(addr_width-1 downto 0)`
336			`);`
337			`end dpram;`
338
339			`architecture altera of dpram is`
340			`component lpm_ram_dp`
341			`generic (`
342			`lpm_width: positive;`
343			`lpm_widthad: positive;`
344			`lpm_numwords: natural := 0;`
345			`lpm_type: string := "lpm_ram_dp";`
346			`lpm_indata: string := "REGISTERED";`
347			`lpm_outdata: string := "UNREGISTERED";`
348			`lpm_rdaddress_control: string := "REGISTERED";`
349			`lpm_wraddress_control: string := "REGISTERED";`
350			`lpm_file: string := "UNUSED";`
351			`lpm_hint: string := "UNUSED"`
352			`);`
353			`port (`
354			`rdaddress, wraddress: in std_logic_vector(lpm_widthad-1 downto 0);`
355			`rdclock, wrclock: in std_logic := '0';`
356			`rden, rdclken, wrclken: in std_logic := '1';`
357			`wren: in std_logic;`
358			`data: in std_logic_vector(lpm_width-1 downto 0);`
359			`q: out std_logic_vector(lpm_width-1 downto 0)`
360			`);`
361			`end component;`
362			`begin`
363			`altera_ram: lpm_ram_dp`
364			`generic map (`
365			`lpm_width => data_width,`
366			`lpm_widthad => addr_width,`
367			`lpm_numwords => 2 ** addr_width,`
368			`lpm_type => "lpm_ram_dp",`
369			`lpm_indata => "REGISTERED",`
370			`lpm_wraddress_control => "REGISTERED",`
371			`lpm_outdata => "UNREGISTERED",`
372			`lpm_rdaddress_control => "UNREGISTERED",`
373			`lpm_file => "UNUSED",`
374			`lpm_hint => "UNUSED"`
375			`)`
376			`port map (`
377			`-- rdclock => clk,`
378			`rdclken => r_clk_en,`
379			`rdaddress => r_addr,`
380			`q => r_d_out,`
381			`rden => r_rd,`
382
383			`wrclock => clk,`
384			`wrclken => w_clk_en,`
385			`wraddress => w_addr,`
386			`data => w_d_in,`
387			`wren => w_wr`
388			`);`
389			`end altera;`
390
391			`library IEEE;`
392			`use IEEE.std_logic_1164.all;`
393
394			`library altera_exemplar;`
395			`use altera_exemplar.all;`
396
397			`entity d_ff is`
398			`port ( d : in STD_LOGIC;`
399			`clk: in STD_LOGIC;`
400			`ena: in STD_LOGIC := '1';`
401			`clr: in STD_LOGIC := '0';`
402			`pre: in STD_LOGIC := '0';`
403			`q : out STD_LOGIC`
404			`);`
405			`end d_ff;`
406
407			`architecture altera of d_ff is`
408			`component dffe`
409			`port ( D : in STD_LOGIC;`
410			`CLK: in STD_LOGIC;`
411			`ENA: in STD_LOGIC;`
412			`CLRN: in STD_LOGIC;`
413			`PRN: in STD_LOGIC;`
414			`Q : out STD_LOGIC);`
415			`end component;`
416			`signal clrn,prn: std_logic;`
417			`begin`
418			`clrn <= not clr;`
419			`prn <= not pre;`
420			`ff: dffe port map (`
421			`D => d,`
422			`CLK => clk,`
423			`ENA => ena,`
424			`CLRN => clrn,`
425			`PRN => prn,`
426			`Q => q`
427			`);`
428			`end altera;`
429
430			`-- Sythetizer library. Contains STD_LOGIC arithmetics`
431