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tantos |
--
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-- Wishbone bus toolkit.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- wb_bus_upsize: bus upsizer.
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-------------------------------------------------------------------------------
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--
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-- wb_bus_upsize
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity wb_bus_upsize is
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generic (
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m_bus_width: positive := 8; -- master bus width
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m_addr_width: positive := 21; -- master bus width
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s_bus_width: positive := 16; -- slave bus width
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s_addr_width: positive := 20; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end wb_bus_upsize;
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architecture wb_bus_upsize of wb_bus_upsize is
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constant addr_diff: integer := log2(s_bus_width/m_bus_width);
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signal i_m_dat_o: std_logic_vector(m_bus_width-1 downto 0);
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begin
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assert (m_addr_width = s_addr_width+addr_diff) report "Address widths are not consistent" severity FAILURE;
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s_adr_o <= m_adr_i(m_addr_width-addr_diff downto addr_diff);
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s_we_o <= m_we_i;
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m_ack_o <= (m_stb_i and s_ack_i) or (not m_stb_i and m_ack_oi);
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m_err_o <= (m_stb_i and s_err_i) or (not m_stb_i and m_err_oi);
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m_rty_o <= (m_stb_i and s_rty_i) or (not m_stb_i and m_rty_oi);
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s_stb_o <= m_stb_i;
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s_cyc_o <= m_cyc_i;
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sel_dat_mux: process is
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begin
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wait on s_dat_i, m_adr_i;
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if (little_endien) then
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for i in s_sel_o'RANGE loop
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if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
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s_sel_o(i) <= '1';
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i_m_dat_o <= s_dat_i(8*i+7 downto 8*i+0);
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else
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s_sel_o(i) <= '0';
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end if;
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end loop;
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else
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for i in s_sel_o'RANGE loop
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if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
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s_sel_o(s_sel_o'HIGH-i) <= '1';
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i_m_dat_o <= s_dat_i(s_dat_i'HIGH-8*i downto s_dat_i'HIGH-8*i-7);
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else
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s_sel_o(s_sel_o'HIGH-i) <= '0';
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end if;
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end loop;
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end if;
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end process;
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d_i_for: for i in m_dat_o'RANGE generate
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m_dat_o(i) <= (m_stb_i and i_m_dat_o(i)) or (not m_stb_i and m_dat_oi(i));
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end generate;
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d_o_for: for i in s_sel_o'RANGE generate
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s_dat_o(8*i+7 downto 8*i+0) <= m_dat_i;
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end generate;
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end wb_bus_upsize;
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