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[/] [wb_vga/] [trunk/] [wb_tk/] [wb_test.vhd] - Blame information for rev 8

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--
--  Wishbone bus tester utilities.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
--
-- ELEMENTS:
--    procedure wr_chk_val: writes a value, reads it back an checks if it's the same
--    procedure wr_val: writes a value
--    procedure rd_val: reads a value
--    procedure chk_val: checks (after read) a value
 
library IEEE;
use IEEE.std_logic_1164.all;
library synopsys;
use synopsys.std_logic_arith.all;
 
package wb_test is
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                variable data: out STD_LOGIC_VECTOR
        );
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
 
 
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                variable data: out STD_LOGIC_VECTOR
        );
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
end wb_test;
 
 
package body wb_test is
    procedure wr_chk_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        constant data: in STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        stb_i <= '0';
        we_i <= '0';
        cyc_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= data;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '1';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= dat_undef;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        assert dat_o = data report "Value does not match!" severity ERROR;
        adr_i <= adr_zero;
        stb_i <= '0';
        cyc_i <= '0';
    end procedure;
 
    procedure wr_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        constant data: in STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        stb_i <= '0';
        we_i <= '0';
        cyc_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= data;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '1';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
    end procedure;
 
    procedure rd_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        variable data: out STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= dat_undef;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        data := dat_o;
        adr_i <= adr_zero;
        stb_i <= '0';
        cyc_i <= '0';
    end procedure;
 
    procedure chk_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        constant data: in STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= dat_undef;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        assert dat_o = data report "Value does not match!" severity ERROR;
        adr_i <= adr_zero;
        stb_i <= '0';
        cyc_i <= '0';
    end procedure;
 
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end procedure;
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end procedure;
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                variable data: out STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end procedure;
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end procedure;
 
end package body wb_test;
 

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[/] [wb_vga/] [trunk/] [wb_tk/] [wb_test.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	7	tantos	`--`
2			`-- Wishbone bus tester utilities.`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7			`--`
8			`-- ELEMENTS:`
9			`-- procedure wr_chk_val: writes a value, reads it back an checks if it's the same`
10			`-- procedure wr_val: writes a value`
11			`-- procedure rd_val: reads a value`
12			`-- procedure chk_val: checks (after read) a value`
13
14			`library IEEE;`
15			`use IEEE.std_logic_1164.all;`
16			`library synopsys;`
17			`use synopsys.std_logic_arith.all;`
18
19			`package wb_test is`
20			`procedure wr_chk_val(`
21			`signal clk_i: in STD_LOGIC;`
22			`signal adr_i: out STD_LOGIC_VECTOR;`
23			`signal dat_o: in STD_LOGIC_VECTOR;`
24			`signal dat_i: out STD_LOGIC_VECTOR;`
25			`signal we_i: out STD_LOGIC;`
26			`signal cyc_i: out std_logic;`
27			`signal stb_i: out STD_LOGIC;`
28			`signal ack_o: in STD_LOGIC;`
29			`constant addr: in STD_LOGIC_VECTOR;`
30			`constant data: in STD_LOGIC_VECTOR`
31			`);`
32			`procedure wr_val(`
33			`signal clk_i: in STD_LOGIC;`
34			`signal adr_i: out STD_LOGIC_VECTOR;`
35			`signal dat_o: in STD_LOGIC_VECTOR;`
36			`signal dat_i: out STD_LOGIC_VECTOR;`
37			`signal we_i: out STD_LOGIC;`
38			`signal cyc_i: out std_logic;`
39			`signal stb_i: out STD_LOGIC;`
40			`signal ack_o: in STD_LOGIC;`
41			`constant addr: in STD_LOGIC_VECTOR;`
42			`constant data: in STD_LOGIC_VECTOR`
43			`);`
44			`procedure rd_val(`
45			`signal clk_i: in STD_LOGIC;`
46			`signal adr_i: out STD_LOGIC_VECTOR;`
47			`signal dat_o: in STD_LOGIC_VECTOR;`
48			`signal dat_i: out STD_LOGIC_VECTOR;`
49			`signal we_i: out STD_LOGIC;`
50			`signal cyc_i: out std_logic;`
51			`signal stb_i: out STD_LOGIC;`
52			`signal ack_o: in STD_LOGIC;`
53			`constant addr: in STD_LOGIC_VECTOR;`
54			`variable data: out STD_LOGIC_VECTOR`
55			`);`
56			`procedure chk_val(`
57			`signal clk_i: in STD_LOGIC;`
58			`signal adr_i: out STD_LOGIC_VECTOR;`
59			`signal dat_o: in STD_LOGIC_VECTOR;`
60			`signal dat_i: out STD_LOGIC_VECTOR;`
61			`signal we_i: out STD_LOGIC;`
62			`signal cyc_i: out std_logic;`
63			`signal stb_i: out STD_LOGIC;`
64			`signal ack_o: in STD_LOGIC;`
65			`constant addr: in STD_LOGIC_VECTOR;`
66			`constant data: in STD_LOGIC_VECTOR`
67			`);`
68
69
70			`procedure wr_chk_val(`
71			`signal clk_i: in STD_LOGIC;`
72			`signal adr_i: out STD_LOGIC_VECTOR;`
73			`signal dat_o: in STD_LOGIC_VECTOR;`
74			`signal dat_i: out STD_LOGIC_VECTOR;`
75			`signal we_i: out STD_LOGIC;`
76			`signal cyc_i: out std_logic;`
77			`signal stb_i: out STD_LOGIC;`
78			`signal ack_o: in STD_LOGIC;`
79			`constant addr: in integer;`
80			`constant data: in STD_LOGIC_VECTOR`
81			`);`
82			`procedure wr_val(`
83			`signal clk_i: in STD_LOGIC;`
84			`signal adr_i: out STD_LOGIC_VECTOR;`
85			`signal dat_o: in STD_LOGIC_VECTOR;`
86			`signal dat_i: out STD_LOGIC_VECTOR;`
87			`signal we_i: out STD_LOGIC;`
88			`signal cyc_i: out std_logic;`
89			`signal stb_i: out STD_LOGIC;`
90			`signal ack_o: in STD_LOGIC;`
91			`constant addr: in integer;`
92			`constant data: in STD_LOGIC_VECTOR`
93			`);`
94			`procedure rd_val(`
95			`signal clk_i: in STD_LOGIC;`
96			`signal adr_i: out STD_LOGIC_VECTOR;`
97			`signal dat_o: in STD_LOGIC_VECTOR;`
98			`signal dat_i: out STD_LOGIC_VECTOR;`
99			`signal we_i: out STD_LOGIC;`
100			`signal cyc_i: out std_logic;`
101			`signal stb_i: out STD_LOGIC;`
102			`signal ack_o: in STD_LOGIC;`
103			`constant addr: in integer;`
104			`variable data: out STD_LOGIC_VECTOR`
105			`);`
106			`procedure chk_val(`
107			`signal clk_i: in STD_LOGIC;`
108			`signal adr_i: out STD_LOGIC_VECTOR;`
109			`signal dat_o: in STD_LOGIC_VECTOR;`
110			`signal dat_i: out STD_LOGIC_VECTOR;`
111			`signal we_i: out STD_LOGIC;`
112			`signal cyc_i: out std_logic;`
113			`signal stb_i: out STD_LOGIC;`
114			`signal ack_o: in STD_LOGIC;`
115			`constant addr: in integer;`
116			`constant data: in STD_LOGIC_VECTOR`
117			`);`
118			`end wb_test;`
119
120
121			`package body wb_test is`
122			`procedure wr_chk_val(`
123			`signal clk_i: in STD_LOGIC;`
124			`signal adr_i: out STD_LOGIC_VECTOR;`
125			`signal dat_o: in STD_LOGIC_VECTOR;`
126			`signal dat_i: out STD_LOGIC_VECTOR;`
127			`signal we_i: out STD_LOGIC;`
128			`signal cyc_i: out std_logic;`
129			`signal stb_i: out STD_LOGIC;`
130			`signal ack_o: in STD_LOGIC;`
131			`constant addr: in STD_LOGIC_VECTOR;`
132			`constant data: in STD_LOGIC_VECTOR`
133			`) is`
134			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
135			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
136			`begin`
137			`adr_i <= adr_zero;`
138			`dat_i <= dat_undef;`
139			`stb_i <= '0';`
140			`we_i <= '0';`
141			`cyc_i <= '0';`
142			`wait until clk_i'EVENT and clk_i = '1';`
143			`wait until clk_i'EVENT and clk_i = '1';`
144			`wait until clk_i'EVENT and clk_i = '1';`
145			`adr_i <= addr;`
146			`dat_i <= data;`
147			`cyc_i <= '1';`
148			`stb_i <= '1';`
149			`we_i <= '1';`
150			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
151			`adr_i <= adr_zero;`
152			`dat_i <= dat_undef;`
153			`cyc_i <= '0';`
154			`stb_i <= '0';`
155			`we_i <= '0';`
156			`wait until clk_i'EVENT and clk_i = '1';`
157			`adr_i <= addr;`
158			`dat_i <= dat_undef;`
159			`cyc_i <= '1';`
160			`stb_i <= '1';`
161			`we_i <= '0';`
162			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
163			`assert dat_o = data report "Value does not match!" severity ERROR;`
164			`adr_i <= adr_zero;`
165			`stb_i <= '0';`
166			`cyc_i <= '0';`
167			`end procedure;`
168
169			`procedure wr_val(`
170			`signal clk_i: in STD_LOGIC;`
171			`signal adr_i: out STD_LOGIC_VECTOR;`
172			`signal dat_o: in STD_LOGIC_VECTOR;`
173			`signal dat_i: out STD_LOGIC_VECTOR;`
174			`signal we_i: out STD_LOGIC;`
175			`signal cyc_i: out std_logic;`
176			`signal stb_i: out STD_LOGIC;`
177			`signal ack_o: in STD_LOGIC;`
178			`constant addr: in STD_LOGIC_VECTOR;`
179			`constant data: in STD_LOGIC_VECTOR`
180			`) is`
181			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
182			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
183			`begin`
184			`adr_i <= adr_zero;`
185			`dat_i <= dat_undef;`
186			`stb_i <= '0';`
187			`we_i <= '0';`
188			`cyc_i <= '0';`
189			`wait until clk_i'EVENT and clk_i = '1';`
190			`wait until clk_i'EVENT and clk_i = '1';`
191			`wait until clk_i'EVENT and clk_i = '1';`
192			`adr_i <= addr;`
193			`dat_i <= data;`
194			`cyc_i <= '1';`
195			`stb_i <= '1';`
196			`we_i <= '1';`
197			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
198			`adr_i <= adr_zero;`
199			`dat_i <= dat_undef;`
200			`cyc_i <= '0';`
201			`stb_i <= '0';`
202			`we_i <= '0';`
203			`end procedure;`
204
205			`procedure rd_val(`
206			`signal clk_i: in STD_LOGIC;`
207			`signal adr_i: out STD_LOGIC_VECTOR;`
208			`signal dat_o: in STD_LOGIC_VECTOR;`
209			`signal dat_i: out STD_LOGIC_VECTOR;`
210			`signal we_i: out STD_LOGIC;`
211			`signal cyc_i: out std_logic;`
212			`signal stb_i: out STD_LOGIC;`
213			`signal ack_o: in STD_LOGIC;`
214			`constant addr: in STD_LOGIC_VECTOR;`
215			`variable data: out STD_LOGIC_VECTOR`
216			`) is`
217			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
218			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
219			`begin`
220			`adr_i <= adr_zero;`
221			`dat_i <= dat_undef;`
222			`cyc_i <= '0';`
223			`stb_i <= '0';`
224			`we_i <= '0';`
225			`wait until clk_i'EVENT and clk_i = '1';`
226			`wait until clk_i'EVENT and clk_i = '1';`
227			`wait until clk_i'EVENT and clk_i = '1';`
228			`adr_i <= addr;`
229			`dat_i <= dat_undef;`
230			`cyc_i <= '1';`
231			`stb_i <= '1';`
232			`we_i <= '0';`
233			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
234			`data := dat_o;`
235			`adr_i <= adr_zero;`
236			`stb_i <= '0';`
237			`cyc_i <= '0';`
238			`end procedure;`
239
240			`procedure chk_val(`
241			`signal clk_i: in STD_LOGIC;`
242			`signal adr_i: out STD_LOGIC_VECTOR;`
243			`signal dat_o: in STD_LOGIC_VECTOR;`
244			`signal dat_i: out STD_LOGIC_VECTOR;`
245			`signal we_i: out STD_LOGIC;`
246			`signal cyc_i: out std_logic;`
247			`signal stb_i: out STD_LOGIC;`
248			`signal ack_o: in STD_LOGIC;`
249			`constant addr: in STD_LOGIC_VECTOR;`
250			`constant data: in STD_LOGIC_VECTOR`
251			`) is`
252			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
253			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
254			`begin`
255			`adr_i <= adr_zero;`
256			`dat_i <= dat_undef;`
257			`cyc_i <= '0';`
258			`stb_i <= '0';`
259			`we_i <= '0';`
260			`wait until clk_i'EVENT and clk_i = '1';`
261			`wait until clk_i'EVENT and clk_i = '1';`
262			`wait until clk_i'EVENT and clk_i = '1';`
263			`adr_i <= addr;`
264			`dat_i <= dat_undef;`
265			`cyc_i <= '1';`
266			`stb_i <= '1';`
267			`we_i <= '0';`
268			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
269			`assert dat_o = data report "Value does not match!" severity ERROR;`
270			`adr_i <= adr_zero;`
271			`stb_i <= '0';`
272			`cyc_i <= '0';`
273			`end procedure;`
274
275			`procedure wr_chk_val(`
276			`signal clk_i: in STD_LOGIC;`
277			`signal adr_i: out STD_LOGIC_VECTOR;`
278			`signal dat_o: in STD_LOGIC_VECTOR;`
279			`signal dat_i: out STD_LOGIC_VECTOR;`
280			`signal we_i: out STD_LOGIC;`
281			`signal cyc_i: out std_logic;`
282			`signal stb_i: out STD_LOGIC;`
283			`signal ack_o: in STD_LOGIC;`
284			`constant addr: in integer;`
285			`constant data: in STD_LOGIC_VECTOR`
286			`) is`
287			`variable sadr: std_logic_vector(adr_i'RANGE);`
288			`begin`
289			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
290			`wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
291			`end procedure;`
292			`procedure wr_val(`
293			`signal clk_i: in STD_LOGIC;`
294			`signal adr_i: out STD_LOGIC_VECTOR;`
295			`signal dat_o: in STD_LOGIC_VECTOR;`
296			`signal dat_i: out STD_LOGIC_VECTOR;`
297			`signal we_i: out STD_LOGIC;`
298			`signal cyc_i: out std_logic;`
299			`signal stb_i: out STD_LOGIC;`
300			`signal ack_o: in STD_LOGIC;`
301			`constant addr: in integer;`
302			`constant data: in STD_LOGIC_VECTOR`
303			`) is`
304			`variable sadr: std_logic_vector(adr_i'RANGE);`
305			`begin`
306			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
307			`wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
308			`end procedure;`
309			`procedure rd_val(`
310			`signal clk_i: in STD_LOGIC;`
311			`signal adr_i: out STD_LOGIC_VECTOR;`
312			`signal dat_o: in STD_LOGIC_VECTOR;`
313			`signal dat_i: out STD_LOGIC_VECTOR;`
314			`signal we_i: out STD_LOGIC;`
315			`signal cyc_i: out std_logic;`
316			`signal stb_i: out STD_LOGIC;`
317			`signal ack_o: in STD_LOGIC;`
318			`constant addr: in integer;`
319			`variable data: out STD_LOGIC_VECTOR`
320			`) is`
321			`variable sadr: std_logic_vector(adr_i'RANGE);`
322			`begin`
323			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
324			`rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
325			`end procedure;`
326			`procedure chk_val(`
327			`signal clk_i: in STD_LOGIC;`
328			`signal adr_i: out STD_LOGIC_VECTOR;`
329			`signal dat_o: in STD_LOGIC_VECTOR;`
330			`signal dat_i: out STD_LOGIC_VECTOR;`
331			`signal we_i: out STD_LOGIC;`
332			`signal cyc_i: out std_logic;`
333			`signal stb_i: out STD_LOGIC;`
334			`signal ack_o: in STD_LOGIC;`
335			`constant addr: in integer;`
336			`constant data: in STD_LOGIC_VECTOR`
337			`) is`
338			`variable sadr: std_logic_vector(adr_i'RANGE);`
339			`begin`
340			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
341			`chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
342			`end procedure;`
343
344			`end package body wb_test;`
345