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[/] [wb_vga/] [trunk/] [wb_tk/] [wb_tk.vhd] - Blame information for rev 8

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--
--  Wishbone bus toolkit.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
--
-- ELEMENTS:
--   wb_bus_upsize: bus upsizer. Currently only 8->16 bit bus resize is supported
--   wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.
--   wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus
--   wb_out_reg: Wishbone bus compatible output register.
--   wb_bus_resize: Wishbone bus resizer.
 
library IEEE;
use IEEE.std_logic_1164.all;
library wb_tk;
use wb_tk.technology.all;
 
package wb_tk is
        component wb_bus_upsize is
                generic (
                        m_bus_width: positive := 8; -- master bus width
                        m_addr_width: positive := 21; -- master bus width
                        s_bus_width: positive := 16; -- slave bus width
                        s_addr_width: positive := 20; -- master bus width
                        little_endien: boolean := true -- if set to false, big endien
                );
                port (
        --              clk_i: in std_logic;
        --              rst_i: in std_logic := '0';
 
                        -- Master bus interface
                        m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
                        m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
                        m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
                        m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
                        m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
                        m_cyc_i: in std_logic;
                        m_ack_o: out std_logic;
                        m_ack_oi: in std_logic := '-';
                        m_err_o: out std_logic;
                        m_err_oi: in std_logic := '-';
                        m_rty_o: out std_logic;
                        m_rty_oi: in std_logic := '-';
                        m_we_i: in std_logic;
                        m_stb_i: in std_logic;
 
                        -- Slave bus interface
                        s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
                        s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
                        s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
                        s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
                        s_cyc_o: out std_logic;
                        s_ack_i: in std_logic;
                        s_err_i: in std_logic := '-';
                        s_rty_i: in std_logic := '-';
                        s_we_o: out std_logic;
                        s_stb_o: out std_logic
                );
        end component;
 
        component wb_bus_dnsize is
                generic (
                        m_bus_width: positive := 32; -- master bus width
                        m_addr_width: positive := 20; -- master bus width
                        s_bus_width: positive := 16; -- slave bus width
                        s_addr_width: positive := 21; -- master bus width
                        little_endien: boolean := true -- if set to false, big endien
                );
                port (
        --              clk_i: in std_logic;
        --              rst_i: in std_logic := '0';
 
                        -- Master bus interface
                        m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
                        m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
                        m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
                        m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
                        m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
                        m_cyc_i: in std_logic;
                        m_ack_o: out std_logic;
                        m_ack_oi: in std_logic := '-';
                        m_err_o: out std_logic;
                        m_err_oi: in std_logic := '-';
                        m_rty_o: out std_logic;
                        m_rty_oi: in std_logic := '-';
                        m_we_i: in std_logic;
                        m_stb_i: in std_logic;
 
                        -- Slave bus interface
                        s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
                        s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
                        s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
                        s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
                        s_cyc_o: out std_logic;
                        s_ack_i: in std_logic;
                        s_err_i: in std_logic := '-';
                        s_rty_i: in std_logic := '-';
                        s_we_o: out std_logic;
                        s_stb_o: out std_logic
                );
        end component;
 
        component wb_bus_resize is
                generic (
                        m_bus_width: positive := 32; -- master bus width
                        m_addr_width: positive := 20; -- master bus width
                        s_bus_width: positive := 16; -- slave bus width
                        s_addr_width: positive := 21; -- master bus width
                        little_endien: boolean := true -- if set to false, big endien
                );
                port (
        --              clk_i: in std_logic;
        --              rst_i: in std_logic := '0';
 
                        -- Master bus interface
                        m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
                        m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
                        m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
                        m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
                        m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
                        m_cyc_i: in std_logic;
                        m_ack_o: out std_logic;
                        m_ack_oi: in std_logic := '-';
                        m_err_o: out std_logic;
                        m_err_oi: in std_logic := '-';
                        m_rty_o: out std_logic;
                        m_rty_oi: in std_logic := '-';
                        m_we_i: in std_logic;
                        m_stb_i: in std_logic;
 
                        -- Slave bus interface
                        s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
                        s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
                        s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
                        s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
                        s_cyc_o: out std_logic;
                        s_ack_i: in std_logic;
                        s_err_i: in std_logic := '-';
                        s_rty_i: in std_logic := '-';
                        s_we_o: out std_logic;
                        s_stb_o: out std_logic
                );
        end component;
 
        component wb_async_master is
                generic (
                        width: positive := 16;
                        addr_width: positive := 20
                );
                port (
                        clk_i: in std_logic;
                        rst_i: in std_logic := '0';
 
                        -- interface to wb slave devices
                        s_adr_o: out std_logic_vector (addr_width-1 downto 0);
                        s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
                        s_dat_i: in std_logic_vector (width-1 downto 0);
                        s_dat_o: out std_logic_vector (width-1 downto 0);
                        s_cyc_o: out std_logic;
                        s_ack_i: in std_logic;
                        s_err_i: in std_logic := '-';
                        s_rty_i: in std_logic := '-';
                        s_we_o: out std_logic;
                        s_stb_o: out std_logic;
 
                        -- interface to asyncron master device
                        a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
                        a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
                        a_rdn: in std_logic := '1';
                        a_wrn: in std_logic := '1';
                        a_cen: in std_logic := '1';
                        a_byen: in std_logic_vector ((width/8)-1 downto 0);
                        a_waitn: out std_logic
                );
        end component;
 
        component wb_async_slave is
                generic (
                        width: positive := 16;
                        addr_width: positive := 20
                );
                port (
                        clk_i: in std_logic;
                        rst_i: in std_logic := '0';
 
                        -- interface for wait-state generator state-machine
                        wait_state: in std_logic_vector (3 downto 0);
 
                        -- interface to wishbone master device
                        adr_i: in std_logic_vector (addr_width-1 downto 0);
                        sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
                        dat_i: in std_logic_vector (width-1 downto 0);
                        dat_o: out std_logic_vector (width-1 downto 0);
                        dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
                        we_i: in std_logic;
                        stb_i: in std_logic;
                        ack_o: out std_logic := '0';
                        ack_oi: in std_logic := '-';
 
                        -- interface to async slave
                        a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
                        a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
                        a_rdn: out std_logic := '1';
                        a_wrn: out std_logic := '1';
                        a_cen: out std_logic := '1';
                        -- byte-enable signals
                        a_byen: out std_logic_vector ((width/8)-1 downto 0)
                );
        end component;
 
        component wb_arbiter is
                port (
        --              clk_i: in std_logic;
                        rst_i: in std_logic := '0';
 
                        -- interface to master device a
                        a_we_i: in std_logic;
                        a_stb_i: in std_logic;
                        a_cyc_i: in std_logic;
                        a_ack_o: out std_logic;
                        a_ack_oi: in std_logic := '-';
                        a_err_o: out std_logic;
                        a_err_oi: in std_logic := '-';
                        a_rty_o: out std_logic;
                        a_rty_oi: in std_logic := '-';
 
                        -- interface to master device b
                        b_we_i: in std_logic;
                        b_stb_i: in std_logic;
                        b_cyc_i: in std_logic;
                        b_ack_o: out std_logic;
                        b_ack_oi: in std_logic := '-';
                        b_err_o: out std_logic;
                        b_err_oi: in std_logic := '-';
                        b_rty_o: out std_logic;
                        b_rty_oi: in std_logic := '-';
 
                        -- interface to shared devices
                        s_we_o: out std_logic;
                        s_stb_o: out std_logic;
                        s_cyc_o: out std_logic;
                        s_ack_i: in std_logic;
                        s_err_i: in std_logic := '-';
                        s_rty_i: in std_logic := '-';
 
                        mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
 
                        -- misc control lines
                        priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
                );
        end component;
 
        component wb_out_reg is
        generic (
                width : positive := 8;
                bus_width: positive := 8;
                offset: integer := 0
        );
        port (
                clk_i: in std_logic;
                rst_i: in std_logic;
                rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
 
            cyc_i: in std_logic := '1';
                stb_i: in std_logic;
            sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
                we_i: in std_logic;
                ack_o: out std_logic;
                ack_oi: in std_logic := '-';
                adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
                dat_i: in std_logic_vector (bus_width-1 downto 0);
                dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
                dat_o: out std_logic_vector (bus_width-1 downto 0);
                q: out std_logic_vector (width-1 downto 0)
        );
        end component;
end wb_tk;
 

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Subversion Repositories wb_vga

[/] [wb_vga/] [trunk/] [wb_tk/] [wb_tk.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	7	tantos	`--`
2			`-- Wishbone bus toolkit.`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7			`--`
8			`-- ELEMENTS:`
9			`-- wb_bus_upsize: bus upsizer. Currently only 8->16 bit bus resize is supported`
10			`-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.`
11			`-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus`
12			`-- wb_out_reg: Wishbone bus compatible output register.`
13			`-- wb_bus_resize: Wishbone bus resizer.`
14
15			`library IEEE;`
16			`use IEEE.std_logic_1164.all;`
17			`library wb_tk;`
18			`use wb_tk.technology.all;`
19
20			`package wb_tk is`
21			`component wb_bus_upsize is`
22			`generic (`
23			`m_bus_width: positive := 8; -- master bus width`
24			`m_addr_width: positive := 21; -- master bus width`
25			`s_bus_width: positive := 16; -- slave bus width`
26			`s_addr_width: positive := 20; -- master bus width`
27			`little_endien: boolean := true -- if set to false, big endien`
28			`);`
29			`port (`
30			`-- clk_i: in std_logic;`
31			`-- rst_i: in std_logic := '0';`
32
33			`-- Master bus interface`
34			`m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);`
35			`m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');`
36			`m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);`
37			`m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');`
38			`m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);`
39			`m_cyc_i: in std_logic;`
40			`m_ack_o: out std_logic;`
41			`m_ack_oi: in std_logic := '-';`
42			`m_err_o: out std_logic;`
43			`m_err_oi: in std_logic := '-';`
44			`m_rty_o: out std_logic;`
45			`m_rty_oi: in std_logic := '-';`
46			`m_we_i: in std_logic;`
47			`m_stb_i: in std_logic;`
48
49			`-- Slave bus interface`
50			`s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);`
51			`s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);`
52			`s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);`
53			`s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);`
54			`s_cyc_o: out std_logic;`
55			`s_ack_i: in std_logic;`
56			`s_err_i: in std_logic := '-';`
57			`s_rty_i: in std_logic := '-';`
58			`s_we_o: out std_logic;`
59			`s_stb_o: out std_logic`
60			`);`
61			`end component;`
62
63			`component wb_bus_dnsize is`
64			`generic (`
65			`m_bus_width: positive := 32; -- master bus width`
66			`m_addr_width: positive := 20; -- master bus width`
67			`s_bus_width: positive := 16; -- slave bus width`
68			`s_addr_width: positive := 21; -- master bus width`
69			`little_endien: boolean := true -- if set to false, big endien`
70			`);`
71			`port (`
72			`-- clk_i: in std_logic;`
73			`-- rst_i: in std_logic := '0';`
74
75			`-- Master bus interface`
76			`m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);`
77			`m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');`
78			`m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);`
79			`m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');`
80			`m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);`
81			`m_cyc_i: in std_logic;`
82			`m_ack_o: out std_logic;`
83			`m_ack_oi: in std_logic := '-';`
84			`m_err_o: out std_logic;`
85			`m_err_oi: in std_logic := '-';`
86			`m_rty_o: out std_logic;`
87			`m_rty_oi: in std_logic := '-';`
88			`m_we_i: in std_logic;`
89			`m_stb_i: in std_logic;`
90
91			`-- Slave bus interface`
92			`s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);`
93			`s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);`
94			`s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);`
95			`s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);`
96			`s_cyc_o: out std_logic;`
97			`s_ack_i: in std_logic;`
98			`s_err_i: in std_logic := '-';`
99			`s_rty_i: in std_logic := '-';`
100			`s_we_o: out std_logic;`
101			`s_stb_o: out std_logic`
102			`);`
103			`end component;`
104
105			`component wb_bus_resize is`
106			`generic (`
107			`m_bus_width: positive := 32; -- master bus width`
108			`m_addr_width: positive := 20; -- master bus width`
109			`s_bus_width: positive := 16; -- slave bus width`
110			`s_addr_width: positive := 21; -- master bus width`
111			`little_endien: boolean := true -- if set to false, big endien`
112			`);`
113			`port (`
114			`-- clk_i: in std_logic;`
115			`-- rst_i: in std_logic := '0';`
116
117			`-- Master bus interface`
118			`m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);`
119			`m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');`
120			`m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);`
121			`m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');`
122			`m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);`
123			`m_cyc_i: in std_logic;`
124			`m_ack_o: out std_logic;`
125			`m_ack_oi: in std_logic := '-';`
126			`m_err_o: out std_logic;`
127			`m_err_oi: in std_logic := '-';`
128			`m_rty_o: out std_logic;`
129			`m_rty_oi: in std_logic := '-';`
130			`m_we_i: in std_logic;`
131			`m_stb_i: in std_logic;`
132
133			`-- Slave bus interface`
134			`s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);`
135			`s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);`
136			`s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);`
137			`s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);`
138			`s_cyc_o: out std_logic;`
139			`s_ack_i: in std_logic;`
140			`s_err_i: in std_logic := '-';`
141			`s_rty_i: in std_logic := '-';`
142			`s_we_o: out std_logic;`
143			`s_stb_o: out std_logic`
144			`);`
145			`end component;`
146
147			`component wb_async_master is`
148			`generic (`
149			`width: positive := 16;`
150			`addr_width: positive := 20`
151			`);`
152			`port (`
153			`clk_i: in std_logic;`
154			`rst_i: in std_logic := '0';`
155
156			`-- interface to wb slave devices`
157			`s_adr_o: out std_logic_vector (addr_width-1 downto 0);`
158			`s_sel_o: out std_logic_vector ((width/8)-1 downto 0);`
159			`s_dat_i: in std_logic_vector (width-1 downto 0);`
160			`s_dat_o: out std_logic_vector (width-1 downto 0);`
161			`s_cyc_o: out std_logic;`
162			`s_ack_i: in std_logic;`
163			`s_err_i: in std_logic := '-';`
164			`s_rty_i: in std_logic := '-';`
165			`s_we_o: out std_logic;`
166			`s_stb_o: out std_logic;`
167
168			`-- interface to asyncron master device`
169			`a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');`
170			`a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');`
171			`a_rdn: in std_logic := '1';`
172			`a_wrn: in std_logic := '1';`
173			`a_cen: in std_logic := '1';`
174			`a_byen: in std_logic_vector ((width/8)-1 downto 0);`
175			`a_waitn: out std_logic`
176			`);`
177			`end component;`
178
179			`component wb_async_slave is`
180			`generic (`
181			`width: positive := 16;`
182			`addr_width: positive := 20`
183			`);`
184			`port (`
185			`clk_i: in std_logic;`
186			`rst_i: in std_logic := '0';`
187
188			`-- interface for wait-state generator state-machine`
189			`wait_state: in std_logic_vector (3 downto 0);`
190
191			`-- interface to wishbone master device`
192			`adr_i: in std_logic_vector (addr_width-1 downto 0);`
193			`sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);`
194			`dat_i: in std_logic_vector (width-1 downto 0);`
195			`dat_o: out std_logic_vector (width-1 downto 0);`
196			`dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');`
197			`we_i: in std_logic;`
198			`stb_i: in std_logic;`
199			`ack_o: out std_logic := '0';`
200			`ack_oi: in std_logic := '-';`
201
202			`-- interface to async slave`
203			`a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');`
204			`a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');`
205			`a_rdn: out std_logic := '1';`
206			`a_wrn: out std_logic := '1';`
207			`a_cen: out std_logic := '1';`
208			`-- byte-enable signals`
209			`a_byen: out std_logic_vector ((width/8)-1 downto 0)`
210			`);`
211			`end component;`
212
213			`component wb_arbiter is`
214			`port (`
215			`-- clk_i: in std_logic;`
216			`rst_i: in std_logic := '0';`
217
218			`-- interface to master device a`
219			`a_we_i: in std_logic;`
220			`a_stb_i: in std_logic;`
221			`a_cyc_i: in std_logic;`
222			`a_ack_o: out std_logic;`
223			`a_ack_oi: in std_logic := '-';`
224			`a_err_o: out std_logic;`
225			`a_err_oi: in std_logic := '-';`
226			`a_rty_o: out std_logic;`
227			`a_rty_oi: in std_logic := '-';`
228
229			`-- interface to master device b`
230			`b_we_i: in std_logic;`
231			`b_stb_i: in std_logic;`
232			`b_cyc_i: in std_logic;`
233			`b_ack_o: out std_logic;`
234			`b_ack_oi: in std_logic := '-';`
235			`b_err_o: out std_logic;`
236			`b_err_oi: in std_logic := '-';`
237			`b_rty_o: out std_logic;`
238			`b_rty_oi: in std_logic := '-';`
239
240			`-- interface to shared devices`
241			`s_we_o: out std_logic;`
242			`s_stb_o: out std_logic;`
243			`s_cyc_o: out std_logic;`
244			`s_ack_i: in std_logic;`
245			`s_err_i: in std_logic := '-';`
246			`s_rty_i: in std_logic := '-';`
247
248			`mux_signal: out std_logic; -- 0: select A signals, 1: select B signals`
249
250			`-- misc control lines`
251			`priority: in std_logic -- 0: A have priority over B, 1: B have priority over A`
252			`);`
253			`end component;`
254
255			`component wb_out_reg is`
256			`generic (`
257			`width : positive := 8;`
258			`bus_width: positive := 8;`
259			`offset: integer := 0`
260			`);`
261			`port (`
262			`clk_i: in std_logic;`
263			`rst_i: in std_logic;`
264			`rst_val: std_logic_vector(width-1 downto 0) := (others => '0');`
265
266			`cyc_i: in std_logic := '1';`
267			`stb_i: in std_logic;`
268			`sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');`
269			`we_i: in std_logic;`
270			`ack_o: out std_logic;`
271			`ack_oi: in std_logic := '-';`
272			`adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');`
273			`dat_i: in std_logic_vector (bus_width-1 downto 0);`
274			`dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');`
275			`dat_o: out std_logic_vector (bus_width-1 downto 0);`
276			`q: out std_logic_vector (width-1 downto 0)`
277			`);`
278			`end component;`
279			`end wb_tk;`
280