| 1 |
17 |
bporcella |
///////////////////////////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
////
|
| 3 |
|
|
//// file name: z80_core_top.v
|
| 4 |
|
|
//// description: interconnect module for z80 core.
|
| 5 |
|
|
//// project: wb_z80 ////
|
| 6 |
|
|
////
|
| 7 |
|
|
//// Author: B.J. Porcella
|
| 8 |
|
|
//// bporcella@sbcglobal.net
|
| 9 |
|
|
////
|
| 10 |
|
|
////
|
| 11 |
|
|
////
|
| 12 |
|
|
///////////////////////////////////////////////////////////////////////////////////////////////
|
| 13 |
|
|
////
|
| 14 |
|
|
//// Copyright (C) 2000-2002 B.J. Porcella
|
| 15 |
|
|
//// Real Time Solutions
|
| 16 |
|
|
////
|
| 17 |
|
|
////
|
| 18 |
|
|
//// This source file may be used and distributed without
|
| 19 |
|
|
//// restriction provided that this copyright statement is not
|
| 20 |
|
|
//// removed from the file and that any derivative work contains
|
| 21 |
|
|
//// the original copyright notice and the associated disclaimer.
|
| 22 |
|
|
////
|
| 23 |
|
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
|
| 24 |
|
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
| 25 |
|
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
| 26 |
|
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
|
| 27 |
|
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
| 28 |
|
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
| 29 |
|
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
| 30 |
|
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
| 31 |
|
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
| 32 |
|
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
| 33 |
|
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
| 34 |
|
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
| 35 |
|
|
//// POSSIBILITY OF SUCH DAMAGE.
|
| 36 |
|
|
////
|
| 37 |
|
|
///////////////////////////////////////////////////////////////////////////////////////////////
|
| 38 |
|
|
// CVS Log
|
| 39 |
|
|
//
|
| 40 |
|
|
// $Id: z80_core_top.v,v 1.1 2004-04-27 21:27:13 bporcella Exp $
|
| 41 |
|
|
//
|
| 42 |
|
|
// $Date: 2004-04-27 21:27:13 $
|
| 43 |
|
|
// $Revision: 1.1 $
|
| 44 |
|
|
// $Author: bporcella $
|
| 45 |
|
|
// $Locker: $
|
| 46 |
|
|
// $State: Exp $
|
| 47 |
|
|
//
|
| 48 |
|
|
// Change History:
|
| 49 |
|
|
// $Log: not supported by cvs2svn $
|
| 50 |
|
|
// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
|
| 51 |
|
|
// import first files
|
| 52 |
|
|
//
|
| 53 |
|
|
//
|
| 54 |
|
|
//
|
| 55 |
|
|
// connects modules:
|
| 56 |
|
|
// memstate2.v // main state machine for z8
|
| 57 |
|
|
// inst_exec.v // main execution engine for z80
|
| 58 |
|
|
// generic_spram.v // main memory (on board)
|
| 59 |
|
|
// z80_sdram_config.v // fundamentally wishbone glue logic - not on top per design guidelines
|
| 60 |
|
|
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
|
| 61 |
|
|
module z80_core_top( wb_dat_o,
|
| 62 |
|
|
wb_stb_o,
|
| 63 |
|
|
wb_cyc_o,
|
| 64 |
|
|
wb_we_o,
|
| 65 |
|
|
wb_adr_o,
|
| 66 |
|
|
wb_tga_o,
|
| 67 |
|
|
bist_ack_o,
|
| 68 |
|
|
bist_err_o,
|
| 69 |
|
|
wb_ack_i,
|
| 70 |
|
|
wb_clk_i,
|
| 71 |
|
|
wb_dat_i,
|
| 72 |
|
|
bist_req_i,
|
| 73 |
|
|
int_req_i
|
| 74 |
|
|
|
| 75 |
|
|
|
| 76 |
|
|
);
|
| 77 |
|
|
|
| 78 |
|
|
//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
|
| 79 |
|
|
|
| 80 |
|
|
output [7:0] wb_dat_o;
|
| 81 |
|
|
output wb_stb_o;
|
| 82 |
|
|
output wb_cyc_o;
|
| 83 |
|
|
output wb_we_o;
|
| 84 |
|
|
output [15:0] wb_adr_o;
|
| 85 |
|
|
output [1:0] wb_tga_o;
|
| 86 |
|
|
output bist_ack_o;
|
| 87 |
|
|
output bist_err_o;
|
| 88 |
|
|
|
| 89 |
|
|
|
| 90 |
|
|
//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
|
| 91 |
|
|
|
| 92 |
|
|
input wb_ack_i;
|
| 93 |
|
|
input wb_clk_i;
|
| 94 |
|
|
input [7:0] wb_dat_i;
|
| 95 |
|
|
input bist_req_i;
|
| 96 |
|
|
input int_req_i;
|
| 97 |
|
|
|
| 98 |
|
|
|
| 99 |
|
|
//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
|
| 100 |
|
|
//-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0
|
| 101 |
|
|
wire [15:0] wb_adr_o;
|
| 102 |
|
|
wire [15:0] add_out; // output of adder (may not wb_adr_o)
|
| 103 |
|
|
wire [9:0] ir1, ir2;
|
| 104 |
|
|
wire [15:0] nn;
|
| 105 |
|
|
wire [15:0] sp;
|
| 106 |
|
|
wire [7:0] ar, fr, br, cr, dr, er, hr, lr;
|
| 107 |
|
|
wire [15:0] ixr, iyr;
|
| 108 |
|
|
wire [7:0] wb_dat_i, wb_dat_o, sdram_do, cfg_do;
|
| 109 |
|
|
wire [15:0] add16; // ir2 execution engine output for sp updates
|
| 110 |
|
|
|
| 111 |
|
|
|
| 112 |
|
|
|
| 113 |
|
|
|
| 114 |
|
|
|
| 115 |
|
|
|
| 116 |
|
|
|
| 117 |
|
|
//-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0
|
| 118 |
|
|
//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
|
| 119 |
|
|
//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
|
| 120 |
|
|
|
| 121 |
|
|
z80_memstate2 i_z80_memstate2(
|
| 122 |
|
|
.wb_adr_o(wb_adr_o), .wb_we_o(wb_we_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_tga_o(wb_tga_o), .wb_dat_o(wb_dat_o),
|
| 123 |
|
|
.exec_ir2(exec_ir2), .ir1(ir1), .ir2(ir2), .ir1dd(ir1dd), .ir1fd(ir1fd), .ir2dd(ir2dd), .ir2fd(ir2fd), .nn(nn), .sp(sp),
|
| 124 |
|
|
.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
|
| 125 |
|
|
.beq0(beq0), .ceq0(ceq0),
|
| 126 |
|
|
.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr),
|
| 127 |
|
|
.ixr(ixr), .iyr(iyr),
|
| 128 |
|
|
.wb_dat_i(cfg_do), .wb_ack_i(wb_ack_i),
|
| 129 |
|
|
.int_req_i(int_req_i),
|
| 130 |
|
|
.add16(add16),
|
| 131 |
|
|
.wb_clk_i(wb_clk_i),
|
| 132 |
|
|
.rst_i(rst_i) // keep this generic - may turn out to be different from wb_rst
|
| 133 |
|
|
);
|
| 134 |
|
|
|
| 135 |
|
|
|
| 136 |
|
|
z80_inst_exec i_z80_inst_exec(
|
| 137 |
|
|
.br_eq0(br_eq0),
|
| 138 |
|
|
.cr_eq0(cr_eq0),
|
| 139 |
|
|
.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
|
| 140 |
|
|
.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr),
|
| 141 |
|
|
.ixr(ixr), .iyr(iyr), .add16(add16),
|
| 142 |
|
|
.exec_ir2(exec_ir2),
|
| 143 |
|
|
.exec_decbc(exec_decbc), .exec_decb(exec_decb),
|
| 144 |
|
|
.ir2(ir2),
|
| 145 |
|
|
.clk(wb_clk_i),
|
| 146 |
|
|
.rst(rst_i),
|
| 147 |
|
|
.nn(nn), .sp(sp),
|
| 148 |
|
|
.dd_grp(dd_grp),
|
| 149 |
|
|
.fd_grp(fd_grp)
|
| 150 |
|
|
);
|
| 151 |
|
|
|
| 152 |
|
|
// The parameter passed to i_generic_sprem specifies the number of address bits used by the
|
| 153 |
|
|
// memory -- and thus the memory size. We expect to use 15 here in the released documentation -
|
| 154 |
|
|
// giving an onboard 32k SRAM and allowing 32k space for off-chip memory. Note that any change to
|
| 155 |
|
|
// this parameter requires modifications to the decode logic in z80_sdram_cfg.
|
| 156 |
|
|
//
|
| 157 |
|
|
// The generic_spram is being used here per Open Cores coding guidelines. I'm not sure I'm totally
|
| 158 |
|
|
// happy with this...... Depending on which target technology is specified, read behavior changes.
|
| 159 |
|
|
// It is easy to insure all possible behavior will in fact operate properly -- see the data reduction
|
| 160 |
|
|
// logic in sdram_cfg.v -- but still... I guess the important thing to be aware of is that
|
| 161 |
|
|
// big memories like this typically require special back-end handleing. This is likely to prove
|
| 162 |
|
|
// no exception - despite the work that has been done to make this file as generally useful as
|
| 163 |
|
|
// possible.
|
| 164 |
|
|
|
| 165 |
|
|
generic_spram #(12) i_generic_spram(
|
| 166 |
|
|
// Generic synchronous single-port RAM interface
|
| 167 |
|
|
.clk(wb_clk_i), .rst(rst_i), .ce(cfg_ce_spram_o), .we(wb_we_o), .oe(1'b1), .addr(wb_adr_o[11:0]), .di(wb_dat_o), .do(sdram_do)
|
| 168 |
|
|
);
|
| 169 |
|
|
|
| 170 |
|
|
|
| 171 |
|
|
|
| 172 |
|
|
z80_sdram_cfg i_z80_sdram_cfg(
|
| 173 |
|
|
.cfg_ce_spram_o(cfg_ce_spram_o), .cfg_do(cfg_do), .cfg_ack_o(cfg_ack_o), .sdram_di(sdram_do),
|
| 174 |
|
|
.wb_adr_i(wb_adr_o), .wb_dat_i(wb_dat_i), .wb_ack_i(wb_ack_i), .wb_stb_i(wd_stb_o),
|
| 175 |
|
|
.wb_cyc_i(wb_cyc_o), .wb_tga_i(wb_tga_o) );
|
| 176 |
|
|
|
| 177 |
|
|
|
| 178 |
|
|
endmodule
|
