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[/] [wb_z80/] [trunk/] [rtl/] [z80_core_top.v] - Blame information for rev 23

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1 17 bporcella 
///////////////////////////////////////////////////////////////////////////////////////////////
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////
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////  file name:   z80_core_top.v
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////  description: interconnect module for z80 core.
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////  project:     wb_z80                                                                                       ////
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////
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////  Author: B.J. Porcella
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////          bporcella@sbcglobal.net
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////
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////
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////
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///////////////////////////////////////////////////////////////////////////////////////////////
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////
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//// Copyright (C) 2000-2002 B.J. Porcella
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////                         Real Time Solutions
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////
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////
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//// This source file may be used and distributed without
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//// restriction provided that this copyright statement is not
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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//// POSSIBILITY OF SUCH DAMAGE.
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////
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///////////////////////////////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: z80_core_top.v,v 1.3 2004-05-13 14:58:53 bporcella Exp $
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//
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//  $Date: 2004-05-13 14:58:53 $
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//  $Revision: 1.3 $
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//  $Author: bporcella $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//      $Log: not supported by cvs2svn $
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//      Revision 1.2  2004/04/27 21:38:22  bporcella
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//      test lint on core
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//
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//      Revision 1.1  2004/04/27 21:27:13  bporcella
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//      first core build
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//
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//      Revision 1.1.1.1  2004/04/13 23:47:42  bporcella
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//      import first files
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//
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//
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//
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// connects modules:
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//  memstate2.v       // main state machine for z8
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//  inst_exec.v       // main execution engine for z80
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//  generic_spram.v   // main memory  (on board)
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//  z80_sdram_config.v // fundamentally wishbone glue logic - not on top per design guidelines
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//  add a comment test lint
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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module z80_core_top(
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                      wb_dat_o,
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                      wb_stb_o,
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                      wb_cyc_o,
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                      wb_we_o,
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                      wb_adr_o,
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                      wb_tga_o,
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                      wb_ack_i,
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                      wb_clk_i,
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                      wb_dat_i,
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                      wb_rst_i,
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`ifdef COMPILE_BIST
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                      bist_ack_o,
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                      bist_err_o,
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                      bist_req_i,
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`endif
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                      int_req_i
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);
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//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
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output [7:0]    wb_dat_o;
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output          wb_stb_o;
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output          wb_cyc_o;
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output          wb_we_o;
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output [15:0]   wb_adr_o;
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output [1:0]    wb_tga_o;
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//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
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input           wb_ack_i;
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input           wb_clk_i;
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input  [7:0]    wb_dat_i;
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input           wb_rst_i;
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input           int_req_i;
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`ifdef COMPILE_BIST
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output          bist_err_o;
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output          bist_ack_o;
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input           bist_req_i;
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`endif
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//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0
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wire   [15:0]    wb_adr_o;
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wire   [9:0]     ir1, ir2;
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wire   [15:0]    nn;
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wire   [15:0]    sp;
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wire   [7:0]     ar, fr, br, cr, dr, er, hr, lr, intr;
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wire   [15:0]    ixr, iyr;
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wire   [7:0]     wb_dat_i, wb_dat_o, sdram_do, cfg_do;
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wire   [15:0]    add16;         //  ir2 execution engine output for sp updates
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//-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
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//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
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`ifdef COMPILE_BIST
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z80_bist_logic i_z80_bist_logic(
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        .bist_err_o(bist_err_o), .bist_ack_o(bist_ack_o),
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        .wb_adr_i(wb_adr_o), .wb_dat_i(wb_dat_o), .wb_we_i(wb_we_o), .wb_cyc_i(wb_cyc_o),
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        .wb_stb_i(wb_stb_o), .wb_tga_i(wb_tga_o), .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i)
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        );
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`endif
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z80_memstate2 i_z80_memstate2(
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                .wb_adr_o(wb_adr_o), .wb_we_o(wb_we_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_tga_o(wb_tga_o), .wb_dat_o(wb_dat_o),
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                .exec_ir2(exec_ir2), .ir1(ir1), .ir2(ir2), .ir1dd(ir1dd), .ir1fd(ir1fd), .ir2dd(ir2dd), .ir2fd(ir2fd), .nn(nn), .sp(sp),
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                .upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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                .beq0(br_eq0), .ceq0(cr_eq0),
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                .ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr),
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                .ixr(ixr), .iyr(iyr),
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                .wb_dat_i(cfg_do), .wb_ack_i(cfg_ack_o),
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                .int_req_i(int_req_i),
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                .add16(add16),
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                .wb_clk_i(wb_clk_i),
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                .rst_i(wb_rst_i)         // keep this generic - may turn out to be different from wb_rst
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                 );
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z80_inst_exec i_z80_inst_exec(
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                  .br_eq0(br_eq0),
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                  .cr_eq0(cr_eq0),
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                  .upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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                  .ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr), .intr(intr),
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                  .ixr(ixr), .iyr(iyr), .add16(add16),
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                   .exec_ir2(exec_ir2),
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                   .exec_decbc(exec_decbc), .exec_decb(exec_decb),
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                   .ir2(ir2),
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                   .clk(wb_clk_i),
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                   .rst(wb_rst_i),
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                   .nn(nn), .sp(sp),
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                   .ir2dd(ir2dd),
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                   .ir2fd(ir2fd)
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                   );
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// The parameter passed to i_generic_sprem specifies the number of address bits used by the
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// memory  -- and thus the memory size.   We expect to use 15 here in the released documentation -
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// giving an onboard 32k SRAM and allowing 32k space for off-chip memory.  Note that any change to
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// this parameter requires modifications to the decode logic in z80_sdram_cfg.
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//
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// The generic_spram is being used here per Open Cores coding guidelines.  I'm not sure I'm totally
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// happy with this......    Depending on which target technology is specified, read behavior changes.
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// It is easy to insure all possible behavior will in fact operate properly  -- see the data reduction
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// logic in sdram_cfg.v --  but still...   I guess the important thing to be aware of is that
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// big memories like this typically require special back-end handeling.   This is likely to prove
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// no exception  - despite the work that has been done to make this file as generally useful as
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// possible.
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generic_spram #(15) i_generic_spram(
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    // Generic synchronous single-port RAM interface
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    .clk(wb_clk_i), .rst(wb_rst_i), .ce(cfg_ce_spram_o), .we(wb_we_o), .oe(1'b1), .addr(wb_adr_o[14:0]), .di(wb_dat_o), .do(sdram_do)
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    );
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z80_sdram_cfg i_z80_sdram_cfg(
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    .cfg_ce_spram_o(cfg_ce_spram_o), .cfg_do(cfg_do),  .cfg_ack_o(cfg_ack_o), .sdram_di(sdram_do),
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    .wb_adr_i(wb_adr_o), .wb_dat_i(wb_dat_i), .wb_ack_i(wb_ack_i),  .wb_stb_i(wb_stb_o),
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    .wb_cyc_i(wb_cyc_o), .wb_tga_i(wb_tga_o)
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    );
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endmodule

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