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[/] [wb_z80/] [trunk/] [rts_header.v] - Blame information for rev 40

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1 2 bporcella
///////////////////////////////////////////////////////////////////////////////////////////////////
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////                                                                                           ////
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////  WISHBONE Connection Matrix Top Level                                                     ////
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////                                                                                           ////
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////                                                                                           ////
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////  Author: B.J. Porcella                                                                    ////
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////          bporcella@sbcglobal.net                                                          ////
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////                                                                                           ////
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////                                                                                           ////
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////                                                                                           ////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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////                                                                                           ////
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//// Copyright (C) 2000-2002 B.J. Porcella                                                     ////
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////                         Real Time Solutions                                               ////
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////                                                                                           ////
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////                                                                                           ////
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//// This source file may be used and distributed without                                      ////
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//// restriction provided that this copyright statement is not                                 ////
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//// removed from the file and that any derivative work contains                               ////
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//// the original copyright notice and the associated disclaimer.                              ////
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////                                                                                           ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY                                   ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED                                 ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS                                 ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR                                    ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,                                       ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES                                  ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE                                 ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR                                      ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF                                ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT                                ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT                                ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE                                       ////
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//// POSSIBILITY OF SUCH DAMAGE.                                                               ////
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////                                                                                           ////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: rts_header.v,v 1.1.1.1 2004-04-13 23:47:42 bporcella Exp $
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//
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//  $Date: 2004-04-13 23:47:42 $
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//  $Revision: 1.1.1.1 $
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//  $Author: bporcella $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//      $Log: not supported by cvs2svn $
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//
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//
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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module
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//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
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//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
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endmodule

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