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[/] [wbddr3/] [trunk/] [Makefile] - Blame information for rev 6

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1 2 dgisselq
################################################################################
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##
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## Filename:    Makefile
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##
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## Project:     A wishbone controlled DDR3 SDRAM memory controller.
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##
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## Purpose:     To coordinate the master build of the project.  This includes
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##              the Verilator simulation, the test bench, and then the run of
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##      the testbench itself.
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##
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## Creator:     Dan Gisselquist, Ph.D.
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##              Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2015-2016, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of  the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with this program.  (It's in the $(ROOT)/doc directory, run make with no
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## target there if the PDF file isn't present.)  If not, see
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##  for a copy.
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##
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## License:     GPL, v3, as defined and found on www.gnu.org,
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##              http://www.gnu.org/licenses/gpl.html
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##
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##
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################################################################################
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##
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##
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all: rtl bench test
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.PHONY: doc
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doc:
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        cd doc; $(MAKE) --no-print-directory
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.PHONY: rtl
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rtl:
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        cd rtl; $(MAKE) --no-print-directory
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.PHONY: bench
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bench:
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        cd bench/cpp; $(MAKE) --no-print-directory wbddr3_tb
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.PHONY: test
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test:
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        cd bench/cpp; $(MAKE) --no-print-directory test

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