OpenCores
URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [Makefile] - Blame information for rev 21

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 dgisselq
################################################################################
2
##
3
## Filename:    Makefile
4
##
5
## Project:     A wishbone controlled DDR3 SDRAM memory controller.
6
##
7
## Purpose:     This coordinates the build of the singular test bench C++
8
##              program found in this directory: ddrsdram_tb.
9
##
10
## Creator:     Dan Gisselquist, Ph.D.
11
##              Gisselquist Technology, LLC
12
##
13
################################################################################
14
##
15
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
16
##
17
## This program is free software (firmware): you can redistribute it and/or
18
## modify it under the terms of  the GNU General Public License as published
19
## by the Free Software Foundation, either version 3 of the License, or (at
20
## your option) any later version.
21
##
22
## This program is distributed in the hope that it will be useful, but WITHOUT
23
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
24
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
25
## for more details.
26
##
27
## You should have received a copy of the GNU General Public License along
28
## with this program.  (It's in the $(ROOT)/doc directory, run make with no
29
## target there if the PDF file isn't present.)  If not, see
30
##  for a copy.
31
##
32
## License:     GPL, v3, as defined and found on www.gnu.org,
33
##              http://www.gnu.org/licenses/gpl.html
34
##
35
##
36
################################################################################
37
##
38
##
39 13 dgisselq
OBJDIR  := obj-pc
40 4 dgisselq
CXX     := g++
41
YYMMDD  := `date +%Y%m%d`
42
RTLD    := ../../rtl
43
VOBJDR  := $(RTLD)/obj_dir
44 21 dgisselq
VERILATOR_ROOT   ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"')
45
VROOT   := $(VERILATOR_ROOT)
46 4 dgisselq
VINC    := -I$(VROOT)/include -I$(VOBJDR)
47
CFLAGS  := -Wall -c -Og -g -I. $(VINC)
48 16 dgisselq
SOURCES := pddrsim.cpp ddrsdramsim.cpp ddrsdram_tb.cpp
49 4 dgisselq
VOBJDR  := $(RTLD)/obj_dir
50
VLIB    := $(VROOT)/include/verilated.cpp
51
 
52 20 dgisselq
all:    $(OBJDIR)/ vroot-test ddrsdram_tb
53 13 dgisselq
 
54 20 dgisselq
vroot-test:
55
        echo $(VROOT) $(VLIB)
56 13 dgisselq
 
57 4 dgisselq
$(OBJDIR)/:
58
        @bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
59
 
60 16 dgisselq
$(OBJDIR)/pddrsim.o: pddrsim.cpp pddrsim.h ddrsdramsim.h
61
        $(CXX) $(CFLAGS) pddrsim.cpp -o $@
62
# $(VOBJDR)/Vwbddrsdram.h
63
$(OBJDIR)/ddrsdramsim.o: ddrsdramsim.cpp ddrsdramsim.h
64 4 dgisselq
        $(CXX) $(CFLAGS) ddrsdramsim.cpp -o $@
65 16 dgisselq
$(OBJDIR)/verilated.o: $(VLIB)
66 4 dgisselq
        $(CXX) $(CFLAGS) $(VLIB) -o $@
67 16 dgisselq
$(OBJDIR)/ddrsdram_tb.o: ddrsdram_tb.cpp pddrsim.h $(VOBJDR)/Vwbddrsdram.h
68 4 dgisselq
        $(CXX) $(CFLAGS) ddrsdram_tb.cpp -o $@
69
 
70 16 dgisselq
OBJECTS := ddrsdramsim.o pddrsim.o ddrsdram_tb.o verilated.o
71 4 dgisselq
OBJECTSDR:= $(addprefix $(OBJDIR)/,$(OBJECTS))
72
ddrsdram_tb: $(OBJECTSDR) $(VOBJDR)/Vwbddrsdram__ALL.a
73
        $(CXX) -Wall $(INCS) $^ -o $@
74
 
75
.PHONY: clean
76
clean:
77
        rm -rf $(OBJDIR)/ ddrsdram_tb
78
 
79 13 dgisselq
.PHONY: test
80
test: ddrsdram_tb
81
        ./ddrsdram_tb
82
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.