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[/] [wbddr3/] [trunk/] [bench/] [cpp/] [Makefile] - Blame information for rev 5

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1 4 dgisselq
################################################################################
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##
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## Filename:    Makefile
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##
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## Project:     A wishbone controlled DDR3 SDRAM memory controller.
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##
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## Purpose:     This coordinates the build of the singular test bench C++
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##              program found in this directory: ddrsdram_tb.
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##
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## Creator:     Dan Gisselquist, Ph.D.
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##              Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2015-2016, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of  the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with this program.  (It's in the $(ROOT)/doc directory, run make with no
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## target there if the PDF file isn't present.)  If not, see
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##  for a copy.
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##
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## License:     GPL, v3, as defined and found on www.gnu.org,
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##              http://www.gnu.org/licenses/gpl.html
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##
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##
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################################################################################
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##
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##
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all:    $(OBJDIR)/ ddrsdram_tb
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CXX     := g++
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OBJDIR  := obj-pc
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YYMMDD  := `date +%Y%m%d`
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RTLD    := ../../rtl
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VOBJDR  := $(RTLD)/obj_dir
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VROOT   := /usr/share/verilator
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VINC    := -I$(VROOT)/include -I$(VOBJDR)
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CFLAGS  := -Wall -c -Og -g -I. $(VINC)
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SOURCES := ddrsdramsim.cpp ddrsdram_tb.cpp
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VOBJDR  := $(RTLD)/obj_dir
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VLIB    := $(VROOT)/include/verilated.cpp
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$(OBJDIR)/:
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        @bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
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$(OBJDIR)/ddrsdramsim.o: ddrsdramsim.cpp ddrsdramsim.h $(VOBJDR)/Vwbddrsdram.h
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        $(CXX) $(CFLAGS) ddrsdramsim.cpp -o $@
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$(OBJDIR)/verilated.o: $(VLIB) $(OBJDIR)/
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        $(CXX) $(CFLAGS) $(VLIB) -o $@
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$(OBJDIR)/ddrsdram_tb.o: ddrsdram_tb.cpp ddrsdramsim.h $(VOBJDR)/Vwbddrsdram.h
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        $(CXX) $(CFLAGS) ddrsdram_tb.cpp -o $@
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OBJECTS := ddrsdramsim.o ddrsdram_tb.o verilated.o
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OBJECTSDR:= $(addprefix $(OBJDIR)/,$(OBJECTS))
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ddrsdram_tb: $(OBJECTSDR) $(VOBJDR)/Vwbddrsdram__ALL.a
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        $(CXX) -Wall $(INCS) $^ -o $@
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.PHONY: clean
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clean:
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        rm -rf $(OBJDIR)/ ddrsdram_tb
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