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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddrsdram_tb.cpp
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//
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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//
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// Purpose: To determine whether or not the wbddrsdram Verilog module works.
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// Run this program with no arguments. If the last line output
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// is "SUCCESS", you will know it works.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include "verilated.h"
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#include "Vwbddrsdram.h"
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#include "ddrsdramsim.h"
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const int BOMBCOUNT = 2048,
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SDRAMMASK = 0x3ffffff,
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LGMEMSIZE = 28;
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class DDRSDRAM_TB {
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long m_tickcount;
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Vwbddrsdram *m_core;
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DDRSDRAMSIM *m_sdram;
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bool m_bomb;
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public:
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DDRSDRAM_TB(void) {
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m_core = new Vwbddrsdram;
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m_sdram= new DDRSDRAMSIM(LGMEMSIZE);
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}
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unsigned &operator[](const int index) { return (*m_sdram)[index]; }
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void set(unsigned addr, unsigned v) {
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(*m_sdram)[addr] = v;
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}
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void tick(void) {
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m_core->i_clk = 1;
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m_core->i_ddr_data = (*m_sdram)(
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m_core->o_ddr_reset_n,
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m_core->o_ddr_cke,
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m_core->o_ddr_cs_n,
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m_core->o_ddr_ras_n,
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m_core->o_ddr_cas_n,
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m_core->o_ddr_we_n,
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m_core->o_ddr_dqs,
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m_core->o_ddr_dm,
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m_core->o_ddr_odt,
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m_core->o_ddr_bus_oe,
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m_core->o_ddr_addr,
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m_core->o_ddr_ba,
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m_core->o_ddr_data);
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dgisselq |
bool writeout = (!m_core->v__DOT__reset_override);
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writeout = true;
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dgisselq |
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if (writeout) {
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int cmd;
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cmd = (m_core->o_ddr_reset_n?0:32)
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|(m_core->o_ddr_cke?0:16)
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|(m_core->o_ddr_cs_n?8:0)
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|(m_core->o_ddr_ras_n?4:0)
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|(m_core->o_ddr_cas_n?2:0)
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|(m_core->o_ddr_we_n?1:0);
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printf("%08lx-WB: %s/%s %s%s%s %s@0x%08x[%08x/%08x] -- ",
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m_tickcount,
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(m_core->i_wb_cyc)?"CYC":" ",
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(m_core->i_wb_stb)?"STB":" ",
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(m_core->o_wb_stall)?"STALL":" ",
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(m_core->o_wb_ack)?"ACK":" ",
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(m_core->o_cmd_accepted)?"BUS":" ",
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(m_core->i_wb_we)?"W":"R",
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(m_core->i_wb_addr),
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(m_core->i_wb_data),
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(m_core->o_wb_data));
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dgisselq |
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printf("%s%s %d%d%d%d %s%s%s%s B[%d]@%04x %08x %08x",
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(m_core->o_ddr_reset_n)?" ":"R",
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(m_core->o_ddr_cke)?"CK":" ",
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(m_core->o_ddr_cs_n),
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(m_core->o_ddr_ras_n),
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(m_core->o_ddr_cas_n),
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(m_core->o_ddr_we_n),
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//
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(m_core->o_ddr_dqs)?"D":" ",
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(m_core->o_ddr_dm)?"M":" ",
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(m_core->o_ddr_odt)?"O":" ",
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(m_core->o_ddr_bus_oe)?"E":" ",
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//
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(m_core->o_ddr_ba),
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(m_core->o_ddr_addr),
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(m_core->i_ddr_data),
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(m_core->o_ddr_data));
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4 |
dgisselq |
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dgisselq |
printf(" FIFO[%x,%x](%d,%d,%08x-%08x-%08x)",
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m_core->v__DOT__bus_fifo_head,
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m_core->v__DOT__bus_fifo_tail,
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m_core->v__DOT__bus_fifo_new[m_core->v__DOT__bus_fifo_tail],
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m_core->v__DOT__bus_fifo_sub[m_core->v__DOT__bus_fifo_tail],
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m_core->v__DOT__r_data,
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m_core->v__DOT__bus_fifo_data[(m_core->v__DOT__bus_fifo_head-1)&15],
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m_core->v__DOT__bus_fifo_data[m_core->v__DOT__bus_fifo_tail]);
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printf(" BUS[%03x/%03x/%03x/%d]",
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(m_core->v__DOT__bus_active),
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(m_core->v__DOT__bus_read),
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(m_core->v__DOT__bus_new),
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(m_core->v__DOT__bus_subaddr[8]));
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dgisselq |
// Reset logic
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printf(" RST(%06x%s[%d] - %08x->%08x)",
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m_core->v__DOT__reset_timer,
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(m_core->v__DOT__reset_ztimer)?"Z":" ",
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(m_core->v__DOT__reset_address),
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(m_core->v__DOT__reset_instruction),
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(m_core->v__DOT__reset_cmd));
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dgisselq |
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printf(" %s%03x[%d]%04x:%d",
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(m_core->v__DOT__r_pending)?"R":" ",
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(m_core->v__DOT__r_row),
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(m_core->v__DOT__r_bank),
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(m_core->v__DOT__r_col),0);
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// (m_core->v__DOT__r_sub));
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printf(" %s%s%s",
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"B",
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// (m_core->v__DOT__all_banks_closed)?"b":"B",
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(m_core->v__DOT__need_close_bank)?"C":"N",
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//:(m_core->v__DOT__maybe_close_next_bank)?"c":"N",
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(m_core->v__DOT__need_open_bank)?"O":"K");
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// :(m_core->v__DOT__maybe_open_next_bank)?"o":"K");
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for(int i=0; i<8; i++) {
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printf("%s%x@%x%s",
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dgisselq |
(m_core->v__DOT__r_bank==i)?"R":"[",
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m_core->v__DOT__bank_status[i],
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m_core->v__DOT__bank_address[i],
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(m_core->v__DOT__r_nxt_bank==i)?"N":"]");
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}
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dgisselq |
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dgisselq |
extern int gbl_state, gbl_counts;
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printf(" %2d:%08x ", gbl_state, gbl_counts);
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dgisselq |
printf(" %s%s%s%s%s%s%s:%08x:%08x",
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dgisselq |
(m_core->v__DOT__reset_override)?"R":" ",
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(m_core->v__DOT__need_refresh)?"N":" ",
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(m_core->v__DOT__need_close_bank)?"C":" ",
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(m_core->v__DOT__need_open_bank)?"O":" ",
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(m_core->v__DOT__valid_bank)?"V":" ",
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dgisselq |
(m_core->v__DOT__r_move)?"R":" ",
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(m_core->v__DOT__m_move)?"M":" ",
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dgisselq |
m_core->v__DOT__activate_bank_cmd,
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m_core->v__DOT__cmd);
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dgisselq |
printf(" F%s%05x:%x/%s",
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(m_core->v__DOT__refresh_ztimer)?"Z":" ",
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m_core->v__DOT__refresh_counter,
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m_core->v__DOT__refresh_addr,
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(m_core->v__DOT__need_refresh)?"N":" ");
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dgisselq |
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if (m_core->v__DOT__reset_override)
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printf(" OVERRIDE");
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//if(m_core->v__DOT__last_open_bank)printf(" LST-OPEN");
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switch(cmd) {
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case DDR_MRSET: printf(" MRSET"); break;
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case DDR_REFRESH: printf(" REFRESH"); break;
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case DDR_PRECHARGE: printf(" PRECHARGE%s", (m_core->o_ddr_addr&0x400)?"-ALL":""); break;
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case DDR_ACTIVATE: printf(" ACTIVATE"); break;
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case DDR_WRITE: printf(" WRITE"); break;
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case DDR_READ: printf(" READ"); break;
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case DDR_ZQS: printf(" ZQS"); break;
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case DDR_NOOP: printf(" NOOP"); break;
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default: printf(" Unknown-CMD(%02x)", cmd); break;
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}
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// Decode the command
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printf("\n");
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}
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dgisselq |
m_core->eval();
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m_core->i_clk = 0;
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m_core->eval();
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m_tickcount++;
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/*
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if ((m_core->o_wb_ack)&&(!m_core->i_wb_cyc)) {
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printf("SETTING ERR TO TRUE!!!!! ACK w/ no CYC\n");
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// m_bomb = true;
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}
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*/
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}
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void reset(void) {
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m_core->i_reset = 1;
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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tick();
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m_core->i_reset = 0;
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}
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void wb_tick(void) {
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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tick();
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}
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unsigned wb_read(unsigned a) {
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int errcount = 0;
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unsigned result;
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printf("WB-READ(%08x)\n", a);
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m_core->i_wb_cyc = 1;
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m_core->i_wb_stb = 1;
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m_core->i_wb_we = 0;
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m_core->i_wb_addr= a & SDRAMMASK;
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if (m_core->o_wb_stall) {
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while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
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tick();
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} else
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tick();
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m_core->i_wb_stb = 0;
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while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))
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tick();
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result = m_core->o_wb_data;
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// Release the bus?
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m_core->i_wb_cyc = 0;
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m_core->i_wb_stb = 0;
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if(errcount >= BOMBCOUNT) {
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printf("SETTING ERR TO TRUE!!!!!\n");
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m_bomb = true;
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} else if (!m_core->o_wb_ack) {
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printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
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m_bomb = true;
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}
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tick();
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return result;
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}
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void wb_read(unsigned a, int len, unsigned *buf) {
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int errcount = 0;
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int THISBOMBCOUNT = BOMBCOUNT * len;
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int cnt, rdidx, inc;
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printf("WB-READ(%08x, %d)\n", a, len);
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while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
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wb_tick();
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if (errcount >= BOMBCOUNT) {
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m_bomb = true;
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return;
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}
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errcount = 0;
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m_core->i_wb_cyc = 1;
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m_core->i_wb_stb = 1;
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m_core->i_wb_we = 0;
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m_core->i_wb_addr= a & SDRAMMASK;
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rdidx =0; cnt = 0;
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inc = 1;
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do {
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int s;
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s = (m_core->o_wb_stall==0)?0:1;
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tick();
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if (!s)
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m_core->i_wb_addr += inc;
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cnt += (s==0)?1:0;
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| 312 |
|
|
if (m_core->o_wb_ack)
|
| 313 |
|
|
buf[rdidx++] = m_core->o_wb_data;
|
| 314 |
|
|
} while((cnt < len)&&(errcount++ < THISBOMBCOUNT));
|
| 315 |
|
|
|
| 316 |
|
|
m_core->i_wb_stb = 0;
|
| 317 |
|
|
|
| 318 |
|
|
while((rdidx < len)&&(errcount++ < THISBOMBCOUNT)) {
|
| 319 |
|
|
tick();
|
| 320 |
|
|
if (m_core->o_wb_ack)
|
| 321 |
|
|
buf[rdidx++] = m_core->o_wb_data;
|
| 322 |
|
|
}
|
| 323 |
|
|
|
| 324 |
|
|
// Release the bus?
|
| 325 |
|
|
m_core->i_wb_cyc = 0;
|
| 326 |
|
|
|
| 327 |
|
|
if(errcount >= THISBOMBCOUNT) {
|
| 328 |
|
|
printf("SETTING ERR TO TRUE!!!!! (errcount=%08x, THISBOMBCOUNT=%08x)\n", errcount, THISBOMBCOUNT);
|
| 329 |
|
|
m_bomb = true;
|
| 330 |
|
|
} else if (!m_core->o_wb_ack) {
|
| 331 |
|
|
printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
|
| 332 |
|
|
m_bomb = true;
|
| 333 |
|
|
}
|
| 334 |
|
|
tick();
|
| 335 |
|
|
}
|
| 336 |
|
|
|
| 337 |
|
|
void wb_write(unsigned a, unsigned int v) {
|
| 338 |
|
|
int errcount = 0;
|
| 339 |
|
|
|
| 340 |
|
|
printf("WB-WRITE(%08x) = %08x\n", a, v);
|
| 341 |
|
|
m_core->i_wb_cyc = 1;
|
| 342 |
|
|
m_core->i_wb_stb = 1;
|
| 343 |
|
|
m_core->i_wb_we = 1;
|
| 344 |
|
|
m_core->i_wb_addr= a & SDRAMMASK;
|
| 345 |
|
|
m_core->i_wb_data= v;
|
| 346 |
|
|
|
| 347 |
|
|
if (m_core->o_wb_stall)
|
| 348 |
|
|
while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
|
| 349 |
|
|
tick();
|
| 350 |
|
|
tick();
|
| 351 |
|
|
|
| 352 |
|
|
m_core->i_wb_stb = 0;
|
| 353 |
|
|
|
| 354 |
|
|
while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))
|
| 355 |
|
|
tick();
|
| 356 |
|
|
|
| 357 |
|
|
// Release the bus?
|
| 358 |
|
|
m_core->i_wb_cyc = 0;
|
| 359 |
|
|
m_core->i_wb_stb = 0;
|
| 360 |
|
|
|
| 361 |
|
|
if(errcount >= BOMBCOUNT) {
|
| 362 |
|
|
printf("SETTING ERR TO TRUE!!!!!\n");
|
| 363 |
|
|
m_bomb = true;
|
| 364 |
|
|
} tick();
|
| 365 |
|
|
}
|
| 366 |
|
|
|
| 367 |
|
|
void wb_write(unsigned a, unsigned int ln, unsigned int *buf) {
|
| 368 |
|
|
unsigned errcount = 0, nacks = 0;
|
| 369 |
|
|
|
| 370 |
|
|
m_core->i_wb_cyc = 1;
|
| 371 |
|
|
m_core->i_wb_stb = 1;
|
| 372 |
|
|
for(unsigned stbcnt=0; stbcnt<ln; stbcnt++) {
|
| 373 |
|
|
m_core->i_wb_we = 1;
|
| 374 |
|
|
m_core->i_wb_addr= (a+stbcnt) & SDRAMMASK;
|
| 375 |
|
|
m_core->i_wb_data= buf[stbcnt];
|
| 376 |
|
|
errcount = 0;
|
| 377 |
|
|
|
| 378 |
|
|
while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall)) {
|
| 379 |
|
|
tick(); if (m_core->o_wb_ack) nacks++;
|
| 380 |
|
|
}
|
| 381 |
|
|
// Tick, now that we're not stalled. This is the tick
|
| 382 |
|
|
// that gets accepted.
|
| 383 |
|
|
tick(); if (m_core->o_wb_ack) nacks++;
|
| 384 |
|
|
}
|
| 385 |
|
|
|
| 386 |
|
|
m_core->i_wb_stb = 0;
|
| 387 |
|
|
|
| 388 |
|
|
errcount = 0;
|
| 389 |
|
|
while((nacks < ln)&&(errcount++ < BOMBCOUNT)) {
|
| 390 |
|
|
tick();
|
| 391 |
|
|
if (m_core->o_wb_ack) {
|
| 392 |
|
|
nacks++;
|
| 393 |
|
|
errcount = 0;
|
| 394 |
|
|
}
|
| 395 |
|
|
}
|
| 396 |
|
|
|
| 397 |
|
|
// Release the bus
|
| 398 |
|
|
m_core->i_wb_cyc = 0;
|
| 399 |
|
|
m_core->i_wb_stb = 0;
|
| 400 |
|
|
|
| 401 |
|
|
if(errcount >= BOMBCOUNT) {
|
| 402 |
|
|
printf("SETTING ERR TO TRUE!!!!!\n");
|
| 403 |
|
|
m_bomb = true;
|
| 404 |
|
|
} tick();
|
| 405 |
|
|
}
|
| 406 |
|
|
|
| 407 |
|
|
bool bombed(void) const { return m_bomb; }
|
| 408 |
|
|
|
| 409 |
|
|
};
|
| 410 |
|
|
|
| 411 |
|
|
void uload(unsigned len, unsigned *buf) {
|
| 412 |
|
|
FILE *fp = fopen("/dev/urandom", "r");
|
| 413 |
|
|
|
| 414 |
|
|
if ((NULL == fp)||(len != fread(buf, sizeof(unsigned), len, fp))) {
|
| 415 |
|
|
for(int i=0; i<(int)len; i++)
|
| 416 |
|
|
buf[i] = rand();
|
| 417 |
|
|
} if (NULL == fp)
|
| 418 |
|
|
fclose(fp);
|
| 419 |
|
|
}
|
| 420 |
|
|
|
| 421 |
|
|
int main(int argc, char **argv) {
|
| 422 |
|
|
Verilated::commandArgs(argc, argv);
|
| 423 |
|
|
DDRSDRAM_TB *tb = new DDRSDRAM_TB;
|
| 424 |
|
|
unsigned *rdbuf, *mbuf;
|
| 425 |
|
|
int nw = 3, nr = 13;
|
| 426 |
|
|
unsigned mlen = (1<<(LGMEMSIZE-2));
|
| 427 |
|
|
|
| 428 |
|
|
printf("Giving the core 140k cycles to start up\n");
|
| 429 |
|
|
// Before testing, let's give the unit time enough to warm up
|
| 430 |
|
|
tb->reset();
|
| 431 |
7 |
dgisselq |
for(int i=0; i<141195; i++)
|
| 432 |
4 |
dgisselq |
tb->wb_tick();
|
| 433 |
|
|
|
| 434 |
|
|
printf("Getting some memory ...\n");
|
| 435 |
|
|
rdbuf = new unsigned[mlen];
|
| 436 |
|
|
mbuf = new unsigned[mlen]; // Match buffer
|
| 437 |
|
|
printf("Charging my memory with random values\n");
|
| 438 |
|
|
uload(mlen, rdbuf);
|
| 439 |
|
|
|
| 440 |
|
|
// First test: singular reads through the memory, followed by
|
| 441 |
|
|
// singular writes
|
| 442 |
|
|
printf("Starting the single-read test\n");
|
| 443 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 444 |
|
|
tb->wb_write(i, rdbuf[i]);
|
| 445 |
|
|
tb->wb_tick();
|
| 446 |
|
|
if ((*tb)[i] != rdbuf[i]) {
|
| 447 |
|
|
printf("WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 448 |
|
|
i, (*tb)[i], rdbuf[i]);
|
| 449 |
|
|
goto test_failure;
|
| 450 |
|
|
} if (tb->bombed())
|
| 451 |
|
|
goto test_failure;
|
| 452 |
|
|
|
| 453 |
|
|
} for(int i=0; i<(int)mlen; i++) {
|
| 454 |
|
|
unsigned v;
|
| 455 |
|
|
if (rdbuf[i] != (v=tb->wb_read(i))) {
|
| 456 |
|
|
printf("READ[%06x] = %08x (Expecting %08x)\n",
|
| 457 |
|
|
i, v, rdbuf[i]);
|
| 458 |
|
|
goto test_failure;
|
| 459 |
|
|
} if (tb->bombed())
|
| 460 |
|
|
goto test_failure;
|
| 461 |
|
|
tb->wb_tick();
|
| 462 |
|
|
}
|
| 463 |
|
|
|
| 464 |
|
|
// Second test: Vector writes going through all memory, followed a
|
| 465 |
|
|
// massive vector read
|
| 466 |
|
|
uload(mlen, rdbuf); // Get some new values
|
| 467 |
|
|
tb->wb_write(0, mlen, rdbuf);
|
| 468 |
|
|
if (tb->bombed())
|
| 469 |
|
|
goto test_failure;
|
| 470 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 471 |
|
|
unsigned v;
|
| 472 |
|
|
if (rdbuf[i] != (v=(*tb)[i])) {
|
| 473 |
|
|
printf("V-WRITE[%06x] = %08x (Expecting %08x)\n",
|
| 474 |
|
|
i, v, rdbuf[i]);
|
| 475 |
|
|
goto test_failure;
|
| 476 |
|
|
}
|
| 477 |
|
|
}
|
| 478 |
|
|
|
| 479 |
|
|
tb->wb_read( 0, mlen, mbuf);
|
| 480 |
|
|
if (tb->bombed())
|
| 481 |
|
|
goto test_failure;
|
| 482 |
|
|
for(int i=0; i<(int)mlen; i++) {
|
| 483 |
|
|
if (rdbuf[i] != mbuf[i]) {
|
| 484 |
|
|
printf("V-READ[%06x] = %08x (Expecting %08x)\n",
|
| 485 |
|
|
i, mbuf[i], rdbuf[i]);
|
| 486 |
|
|
goto test_failure;
|
| 487 |
|
|
}
|
| 488 |
|
|
}
|
| 489 |
|
|
|
| 490 |
|
|
// Third test: Vector writes going through all memory, an prime number
|
| 491 |
|
|
// of values at a time, followed by reads via a different prime number
|
| 492 |
|
|
for(int i=0; i<(int)mlen; i+=nw) {
|
| 493 |
|
|
int ln = ((int)mlen-i>nw)?nw:mlen-i;
|
| 494 |
|
|
tb->wb_write(i, nw, &rdbuf[i]);
|
| 495 |
|
|
for(int j=0; j<ln; j++) {
|
| 496 |
|
|
if ((*tb)[i+j] != rdbuf[i+j]) {
|
| 497 |
|
|
printf("P-WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 498 |
|
|
i, (*tb)[i], rdbuf[i]);
|
| 499 |
|
|
goto test_failure;
|
| 500 |
|
|
}
|
| 501 |
|
|
} if (tb->bombed())
|
| 502 |
|
|
goto test_failure;
|
| 503 |
|
|
} for(int i=0; i<(int)mlen; i+=nr) {
|
| 504 |
|
|
int ln = ((int)mlen-i>nr)?nr:mlen-i;
|
| 505 |
|
|
tb->wb_write(i, nr, &mbuf[i]);
|
| 506 |
|
|
for(int j=0; j<ln; j++) {
|
| 507 |
|
|
if (mbuf[i+j] != rdbuf[i+j]) {
|
| 508 |
|
|
printf("P-READ[%06x] = %08x (Expecting %08x) FAILED\n",
|
| 509 |
|
|
i, mbuf[i], rdbuf[i]);
|
| 510 |
|
|
goto test_failure;
|
| 511 |
|
|
}
|
| 512 |
|
|
} if (tb->bombed())
|
| 513 |
|
|
goto test_failure;
|
| 514 |
|
|
}
|
| 515 |
|
|
|
| 516 |
|
|
|
| 517 |
|
|
printf("SUCCESS!!\n");
|
| 518 |
|
|
exit(0);
|
| 519 |
|
|
test_failure:
|
| 520 |
|
|
printf("FAIL-HERE\n");
|
| 521 |
|
|
for(int i=0; i<64; i++)
|
| 522 |
|
|
tb->tick();
|
| 523 |
|
|
printf("TEST FAILED\n");
|
| 524 |
|
|
exit(-1);
|
| 525 |
|
|
}
|
