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[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdram_tb.cpp] - Blame information for rev 9

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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    ddrsdram_tb.cpp
//
// Project:     A wishbone controlled DDR3 SDRAM memory controller.
//
// Purpose:     To determine whether or not the wbddrsdram Verilog module works.
//              Run this program with no arguments.  If the last line output
//      is "SUCCESS", you will know it works.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
 
#include "verilated.h"
#include "Vwbddrsdram.h"
#include "ddrsdramsim.h"
 
const int       BOMBCOUNT = 2048,
                SDRAMMASK = 0x3ffffff,
                LGMEMSIZE = 28;
 
class   DDRSDRAM_TB {
        long            m_tickcount;
        Vwbddrsdram     *m_core;
        DDRSDRAMSIM     *m_sdram;
        bool            m_bomb;
public:
 
        DDRSDRAM_TB(void) {
                m_core = new Vwbddrsdram;
                m_sdram= new DDRSDRAMSIM(LGMEMSIZE);
        }
 
        unsigned &operator[](const int index) { return (*m_sdram)[index]; }
        void    set(unsigned addr, unsigned v) {
                (*m_sdram)[addr] = v;
        }
 
        void    tick(void) {
                m_core->i_clk = 1;
 
                m_core->i_ddr_data = (*m_sdram)(
                        m_core->o_ddr_reset_n,
                        m_core->o_ddr_cke,
                        m_core->o_ddr_cs_n,
                        m_core->o_ddr_ras_n,
                        m_core->o_ddr_cas_n,
                        m_core->o_ddr_we_n,
                        m_core->o_ddr_dqs,
                        m_core->o_ddr_dm,
                        m_core->o_ddr_odt,
                        m_core->o_ddr_bus_oe,
                        m_core->o_ddr_addr,
                        m_core->o_ddr_ba,
                        m_core->o_ddr_data);
 
                bool    writeout = (!m_core->v__DOT__reset_override);
 
                if (writeout) {
                        int cmd;
                        cmd = (m_core->o_ddr_reset_n?0:32)
                                |(m_core->o_ddr_cke?0:16)
                                |(m_core->o_ddr_cs_n?8:0)
                                |(m_core->o_ddr_ras_n?4:0)
                                |(m_core->o_ddr_cas_n?2:0)
                                |(m_core->o_ddr_we_n?1:0);
                        printf("%08lx-WB: %s/%s %s%s%s %s@0x%08x[%08x/%08x] -- ",
                                m_tickcount,
                                (m_core->i_wb_cyc)?"CYC":"   ",
                                (m_core->i_wb_stb)?"STB":"   ",
                                (m_core->o_wb_stall)?"STALL":"     ",
                                (m_core->o_wb_ack)?"ACK":"   ",
                                (m_core->o_cmd_accepted)?"BUS":"   ",
                                (m_core->i_wb_we)?"W":"R",
                                (m_core->i_wb_addr),
                                (m_core->i_wb_data),
                                (m_core->o_wb_data));
 
                        printf("%s%s %d%d%d%d %s%s%s%s B[%d]@%04x %08x %08x",
                                (m_core->o_ddr_reset_n)?" ":"R",
                                (m_core->o_ddr_cke)?"CK":"  ",
                                (m_core->o_ddr_cs_n),
                                (m_core->o_ddr_ras_n),
                                (m_core->o_ddr_cas_n),
                                (m_core->o_ddr_we_n),
                                //
                                (m_core->o_ddr_dqs)?"D":" ",
                                (m_core->o_ddr_dm)?"M":" ",
                                (m_core->o_ddr_odt)?"O":" ",
                                (m_core->o_ddr_bus_oe)?"E":" ",
                                //
                                (m_core->o_ddr_ba),
                                (m_core->o_ddr_addr),
                                (m_core->i_ddr_data),
                                (m_core->o_ddr_data));
 
                        printf(" FIFO[%x,%x](%s,%d,%08x)",
                                m_core->v__DOT__bus_fifo_head,
                                m_core->v__DOT__bus_fifo_tail,
                                (m_core->v__DOT__bus_fifo_new[m_core->v__DOT__bus_fifo_tail])?"N":"o",
                                m_core->v__DOT__bus_fifo_sub[m_core->v__DOT__bus_fifo_tail],
                                m_core->v__DOT__bus_fifo_data[m_core->v__DOT__bus_fifo_tail]);
 
                        printf(" BUS[%03x/%03x/%03x/%d]",
                                (m_core->v__DOT__bus_active),
                                (m_core->v__DOT__bus_read),
                                (m_core->v__DOT__bus_new),
                                (m_core->v__DOT__bus_subaddr[8]));
 
                        /*
                        // Reset logic
                        printf(" RST(%06x%s[%d] - %08x->%08x)",
                                m_core->v__DOT__reset_timer,
                                (m_core->v__DOT__reset_ztimer)?"Z":" ",
                                (m_core->v__DOT__reset_address),
                                (m_core->v__DOT__reset_instruction),
                                (m_core->v__DOT__reset_cmd));
                        */
 
                        printf(" R_%s%03x[%d]%04x:%d/%08x",
                                (!m_core->v__DOT__r_pending)?"_"
                                        :(m_core->v__DOT__r_we)?"W":"R",
                                (m_core->v__DOT__r_row),
                                (m_core->v__DOT__r_bank),
                                (m_core->v__DOT__r_col),
                                (m_core->v__DOT__r_sub),
                                (m_core->v__DOT__r_data));
 
                        printf(" S_%s%03x[%d]%04x:%d/%08x%s%s%s",
                                (!m_core->v__DOT__s_pending)?"_"
                                        :(m_core->v__DOT__s_we)?"W":"R",
                                (m_core->v__DOT__s_row),
                                (m_core->v__DOT__s_bank),
                                (m_core->v__DOT__s_col),
                                (m_core->v__DOT__s_sub),
                                (m_core->v__DOT__s_data),
                                (m_core->v__DOT__s_match)?"M":" ",
                                (m_core->v__DOT__pipe_stall)?"P":" ",
                                "-"
                                //(m_core->v__DOT__s_stall)?"S":" "
                                );
 
 
                        printf(" %s%s%s",
                                "B",
                                // (m_core->v__DOT__all_banks_closed)?"b":"B",
                                (m_core->v__DOT__need_close_bank)?"C":"N",
                                //:(m_core->v__DOT__maybe_close_next_bank)?"c":"N",
                                (m_core->v__DOT__need_open_bank)?"O":"K");
                                // :(m_core->v__DOT__maybe_open_next_bank)?"o":"K");
                        for(int i=0; i<8; i++) {
                                printf("%s%x@%x%s",
                                        (m_core->v__DOT__r_bank==i)?"R":"[",
                                        m_core->v__DOT__bank_status[i],
                                        m_core->v__DOT__bank_address[i],
                                        (m_core->v__DOT__r_nxt_bank==i)?"N":"]");
                        }
 
 
                        extern int gbl_state, gbl_counts;
                        printf(" %2d:%08x ", gbl_state, gbl_counts);
 
                        printf(" %s%s%s%s%s%s:%08x:%08x",
                                (m_core->v__DOT__reset_override)?"R":" ",
                                (m_core->v__DOT__need_refresh)?"N":" ",
                                (m_core->v__DOT__need_close_bank)?"C":" ",
                                (m_core->v__DOT__need_open_bank)?"O":" ",
                                (m_core->v__DOT__valid_bank)?"V":" ",
                                (m_core->v__DOT__r_move)?"R":" ",
                                m_core->v__DOT__activate_bank_cmd,
                                m_core->v__DOT__cmd);
 
                        printf(" F%s%05x:%x/%s",
                                (m_core->v__DOT__refresh_ztimer)?"Z":" ",
                                m_core->v__DOT__refresh_counter,
                                m_core->v__DOT__refresh_addr,
                                (m_core->v__DOT__need_refresh)?"N":" ");
 
                        if (m_core->v__DOT__reset_override)
                                printf(" OVERRIDE");
                        //if(m_core->v__DOT__last_open_bank)printf(" LST-OPEN");
                        switch(cmd) {
                        case DDR_MRSET:     printf(" MRSET"); break;
                        case DDR_REFRESH:   printf(" REFRESH"); break;
                        case DDR_PRECHARGE: printf(" PRECHARGE%s", (m_core->o_ddr_addr&0x400)?"-ALL":""); break;
                        case DDR_ACTIVATE:  printf(" ACTIVATE"); break;
                        case DDR_WRITE:     printf(" WRITE"); break;
                        case DDR_READ:      printf(" READ"); break;
                        case DDR_ZQS:       printf(" ZQS"); break;
                        case DDR_NOOP:      printf(" NOOP"); break;
                        default: printf(" Unknown-CMD(%02x)", cmd); break;
                        }
 
                        // Decode the command
 
                        printf("\n");
                }
 
                m_core->eval();
                m_core->i_clk = 0;
                m_core->eval();
 
                m_tickcount++;
 
                /*
                if ((m_core->o_wb_ack)&&(!m_core->i_wb_cyc)) {
                        printf("SETTING ERR TO TRUE!!!!!  ACK w/ no CYC\n");
                        // m_bomb = true;
                }
                */
        }
 
        void reset(void) {
                m_core->i_reset  = 1;
                m_core->i_wb_cyc = 0;
                m_core->i_wb_stb = 0;
                tick();
                m_core->i_reset  = 0;
        }
 
        void wb_tick(void) {
                m_core->i_wb_cyc   = 0;
                m_core->i_wb_stb = 0;
                tick();
        }
 
        unsigned wb_read(unsigned a) {
                int             errcount = 0;
                unsigned        result;
 
                printf("WB-READ(%08x)\n", a);
 
                m_core->i_wb_cyc = 1;
                m_core->i_wb_stb = 1;
                m_core->i_wb_we  = 0;
                m_core->i_wb_addr= a & SDRAMMASK;
 
                if (m_core->o_wb_stall) {
                        while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
                                tick();
                } tick();
 
                m_core->i_wb_stb = 0;
 
                while((errcount++ <  BOMBCOUNT)&&(!m_core->o_wb_ack))
                        tick();
 
 
                result = m_core->o_wb_data;
 
                // Release the bus?
                m_core->i_wb_cyc = 0;
                m_core->i_wb_stb = 0;
 
                if(errcount >= BOMBCOUNT) {
                        printf("SETTING ERR TO TRUE!!!!!\n");
                        m_bomb = true;
                } else if (!m_core->o_wb_ack) {
                        printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
                        m_bomb = true;
                }
                tick();
 
                return result;
        }
 
        void    wb_read(unsigned a, int len, unsigned *buf) {
                int             errcount = 0;
                int             THISBOMBCOUNT = BOMBCOUNT * len;
                int             cnt, rdidx, inc;
 
                printf("WB-READ(%08x, %d)\n", a, len);
 
                while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
                        wb_tick();
 
                if (errcount >= BOMBCOUNT) {
                        m_bomb = true;
                        return;
                }
 
                errcount = 0;
 
                m_core->i_wb_cyc = 1;
                m_core->i_wb_stb = 1;
                m_core->i_wb_we  = 0;
                m_core->i_wb_addr= a & SDRAMMASK;
 
                rdidx =0; cnt = 0;
                inc = 1;
 
                do {
                        int     s;
                        s = (m_core->o_wb_stall==0)?0:1;
                        tick();
                        if (!s)
                                m_core->i_wb_addr += inc;
                        cnt += (s==0)?1:0;
                        if (m_core->o_wb_ack)
                                buf[rdidx++] = m_core->o_wb_data;
                } while((cnt < len)&&(errcount++ < THISBOMBCOUNT));
 
                m_core->i_wb_stb = 0;
 
                while((rdidx < len)&&(errcount++ < THISBOMBCOUNT)) {
                        tick();
                        if (m_core->o_wb_ack)
                                buf[rdidx++] = m_core->o_wb_data;
                }
 
                // Release the bus?
                m_core->i_wb_cyc = 0;
 
                if(errcount >= THISBOMBCOUNT) {
                        printf("SETTING ERR TO TRUE!!!!! (errcount=%08x, THISBOMBCOUNT=%08x)\n", errcount, THISBOMBCOUNT);
                        m_bomb = true;
                } else if (!m_core->o_wb_ack) {
                        printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");
                        m_bomb = true;
                }
                tick();
        }
 
        void    wb_write(unsigned a, unsigned int v) {
                int errcount = 0;
 
                printf("WB-WRITE(%08x) = %08x\n", a, v);
                m_core->i_wb_cyc = 1;
                m_core->i_wb_stb = 1;
                m_core->i_wb_we  = 1;
                m_core->i_wb_addr= a & SDRAMMASK;
                m_core->i_wb_data= v;
 
                if (m_core->o_wb_stall)
                        while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))
                                tick();
                tick();
 
                m_core->i_wb_stb = 0;
 
                while((errcount++ <  BOMBCOUNT)&&(!m_core->o_wb_ack))
                        tick();
 
                // Release the bus?
                m_core->i_wb_cyc = 0;
                m_core->i_wb_stb = 0;
 
                if(errcount >= BOMBCOUNT) {
                        printf("SETTING ERR TO TRUE!!!!!\n");
                        m_bomb = true;
                } tick();
        }
 
        void    wb_write(unsigned a, unsigned int ln, unsigned int *buf) {
                unsigned errcount = 0, nacks = 0;
 
                m_core->i_wb_cyc = 1;
                m_core->i_wb_stb = 1;
                for(unsigned stbcnt=0; stbcnt<ln; stbcnt++) {
                        m_core->i_wb_we  = 1;
                        m_core->i_wb_addr= (a+stbcnt) & SDRAMMASK;
                        m_core->i_wb_data= buf[stbcnt];
                        errcount = 0;
 
                        while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall)) {
                                tick(); if (m_core->o_wb_ack) nacks++;
                        }
                        // Tick, now that we're not stalled.  This is the tick
                        // that gets accepted.
                        tick(); if (m_core->o_wb_ack) nacks++;
                }
 
                m_core->i_wb_stb = 0;
 
                errcount = 0;
                while((nacks < ln)&&(errcount++ < BOMBCOUNT)) {
                        tick();
                        if (m_core->o_wb_ack) {
                                nacks++;
                                errcount = 0;
                        }
                }
 
                // Release the bus
                m_core->i_wb_cyc = 0;
                m_core->i_wb_stb = 0;
 
                if(errcount >= BOMBCOUNT) {
                        printf("SETTING ERR TO TRUE!!!!!\n");
                        m_bomb = true;
                } tick();
        }
 
        bool    bombed(void) const { return m_bomb; }
 
};
 
void    uload(unsigned len, unsigned *buf) {
        FILE    *fp = fopen("/dev/urandom", "r");
 
        if ((NULL == fp)||(len != fread(buf, sizeof(unsigned), len, fp))) {
                for(int i=0; i<(int)len; i++)
                        buf[i] = rand();
        } if (NULL == fp)
                fclose(fp);
}
 
int main(int  argc, char **argv) {
        Verilated::commandArgs(argc, argv);
        DDRSDRAM_TB     *tb = new DDRSDRAM_TB;
        unsigned        *rdbuf, *mbuf;
        unsigned        mlen = (1<<(LGMEMSIZE-2));
 
        printf("Giving the core 140k cycles to start up\n");
        // Before testing, let's give the unit time enough to warm up
        tb->reset();
        for(int i=0; i<141195; i++)
                tb->wb_tick();
 
        // Let's short circuit the test, and only test *some* of the memory
        // space.  It'll probably be good enough, and it'll finish while I'm
        // waiting ...
        mlen = 1<<16;
 
        printf("Getting some memory ...\n");
        rdbuf = new unsigned[mlen];
        mbuf  = new unsigned[mlen]; // Match buffer
        printf("Charging my memory with random values\n");
        uload(mlen, rdbuf);
 
#define SINGULAR_WRITE
#define SINGULAR_READ
#define BIGPIPELINE_WRITE
#define BIGPIPELINE_READ
#define PRIMEVEC_WRITE
#define PRIMEVEC_READ
#define SKIP_WRITE
#define SKIP_READ
 
#ifdef  SINGULAR_WRITE
        // First test: singular reads through the memory, followed by
        // singular  writes
        printf("Starting the single-read test\n");
        for(int i=0; i<(int)mlen; i++) {
                tb->wb_write(i, rdbuf[i]);
                tb->wb_tick();
                if ((*tb)[i] != rdbuf[i]) {
                        printf("WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
                                i, (*tb)[i], rdbuf[i]);
                        goto test_failure;
                } if (tb->bombed())
                        goto test_failure;
 
        }
#else
#ifdef  SINGULAR_READ
        // If we aren't doing the write test, we still need to charge
        // the memory for the read test.  Here we do it manually.
        for(int i=0; i<(int)mlen; i++)
                (*tb)[i] = rdbuf[i];
#endif // !SINGULAR_WRITE && SINGULAR_READ
#endif // SINGULAR_WRITE
#ifdef  SINGULAR_READ
        for(int i=0; i<(int)mlen; i++) {
                unsigned        v;
                if (rdbuf[i] != (v=tb->wb_read(i))) {
                        printf("READ[%06x] = %08x (Expecting %08x)\n",
                                i, v, rdbuf[i]);
                        goto test_failure;
                } if (tb->bombed())
                        goto test_failure;
                tb->wb_tick();
        }
#endif
 
#ifdef  BIGPIPELINE_WRITE
        // Second test: Vector writes going through all memory, followed a
        // massive vector read
        uload(mlen, rdbuf); // Get some new values
        tb->wb_write(0, mlen, rdbuf);
        if (tb->bombed())
                goto test_failure;
        for(int i=0; i<(int)mlen; i++) {
                unsigned        v;
                if (rdbuf[i] != (v=(*tb)[i])) {
                        printf("V-WRITE[%06x] = %08x (Expecting %08x)\n",
                                i, v, rdbuf[i]);
                        goto test_failure;
                }
        }
#else
#ifdef  BIGPIPELINE_READ
        uload(mlen, rdbuf); // Get some new values
        // If we aren't doing the write test, we still need to charge
        // the memory for the read test.  Here we do it manually.
        for(int i=0; i<(int)mlen; i++)
                (*tb)[i] = rdbuf[i];
#endif // BIGPIPELINE_WRITE && BIGPIPELINE_READ
#endif
#ifdef  BIGPIPELINE_READ
        tb->wb_read( 0, mlen, mbuf);
        if (tb->bombed())
                goto test_failure;
        for(int i=0; i<(int)mlen; i++) {
                if (rdbuf[i] != mbuf[i]) {
                        printf("V-READ[%06x] = %08x (Expecting %08x)\n",
                                i, mbuf[i], rdbuf[i]);
                        goto test_failure;
                }
        }
#endif
 
#ifdef  PRIMEVEC_WRITE
        // Third test: Vector writes going through all memory, in prime numbers
        // of values at a time, followed by reads via a different prime number
        uload(mlen, rdbuf); // Get some new values
        {
                int     nw = 3;
                for(int i=0; i<(int)mlen; i+=nw) {
                        int     ln = ((int)mlen-i>nw)?nw:mlen-i;
                        tb->wb_write(i, nw, &rdbuf[i]);
                        for(int j=0; j<ln; j++) {
                                if ((*tb)[i+j] != rdbuf[i+j]) {
                                        printf("P-WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
                                                i, (*tb)[i], rdbuf[i]);
                                        goto test_failure;
                                }
                        } if (tb->bombed())
                                goto test_failure;
                }
        }
#else
#ifdef  PRIMEVEC_READ
        uload(mlen, rdbuf); // Get some new values
        // If we aren't doing the write test, we still need to charge
        // the memory for the read test.  Here we do it manually.
        for(int i=0; i<(int)mlen; i++)
                (*tb)[i] = rdbuf[i];
#endif
#endif
#ifdef  PRIMEVEC_READ
        {
                int     nr = 13;
                for(int i=0; i<(int)mlen; i+=nr) {
                        int     ln = ((int)mlen-i>nr)?nr:mlen-i;
                        tb->wb_read(i, nr, &mbuf[i]);
                        for(int j=0; j<ln; j++) {
                                if (mbuf[i+j] != rdbuf[i+j]) {
                                        printf("P-READ[%06x] = %08x (Expecting %08x) FAILED\n",
                                                i, mbuf[i], rdbuf[i]);
                                        goto test_failure;
                                }
                        } if (tb->bombed())
                                goto test_failure;
                }
        }
#endif
 
#ifdef  SKIP_WRITE
        // Fourth test: Singular writes though all of memory, skipping by some
        // prime address increment each time, followed by reads via a different
        // prime numbered increment.
        uload(mlen, rdbuf); // Get some new values
        for(int i=0; i<(int)mlen; i++) {
                int     loc = (i*3889)&(mlen-1);
                tb->wb_write(loc, rdbuf[loc]);
                if ((*tb)[loc] != rdbuf[loc]) {
                        printf("R-WRITE[%06x] = %08x (Expecting %08x) FAILED\n",
                                i, (*tb)[loc], rdbuf[loc]);
                        goto test_failure;
                } if (tb->bombed())
                        goto test_failure;
        }
#else
#ifdef  SKIP_READ
        uload(mlen, rdbuf); // Get some new values
        for(int i=0; i<(int)mlen; i++)
                (*tb)[i] = rdbuf[i];
#endif // !SKIP_WRITE && SKIP_READ
#endif
#ifdef  SKIP_READ
        for(int i=0; i<(int)mlen; i++) {
                int     loc = (i*7477)&(mlen-1);
                mbuf[loc] = tb->wb_read(loc);
                if (mbuf[loc] != rdbuf[loc]) {
                        printf("R-READ[%06x] = %08x (Expecting %08x) FAILED\n",
                                loc, mbuf[loc], rdbuf[loc]);
                        goto test_failure;
                } if (tb->bombed())
                        goto test_failure;
        }
#endif
 
 
        printf("SUCCESS!!\n");
        exit(0);
test_failure:
        printf("FAIL-HERE\n");
        for(int i=0; i<64; i++)
                tb->tick();
        printf("TEST FAILED\n");
        exit(-1);
}

Line No.	Rev	Author	Line
1	4	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: ddrsdram_tb.cpp`
4			`//`
5			`// Project: A wishbone controlled DDR3 SDRAM memory controller.`
6			`//`
7			`// Purpose: To determine whether or not the wbddrsdram Verilog module works.`
8			`// Run this program with no arguments. If the last line output`
9			`// is "SUCCESS", you will know it works.`
10			`//`
11			`// Creator: Dan Gisselquist, Ph.D.`
12			`// Gisselquist Technology, LLC`
13			`//`
14			`////////////////////////////////////////////////////////////////////////////////`
15			`//`
16			`// Copyright (C) 2015-2016, Gisselquist Technology, LLC`
17			`//`
18			`// This program is free software (firmware): you can redistribute it and/or`
19			`// modify it under the terms of the GNU General Public License as published`
20			`// by the Free Software Foundation, either version 3 of the License, or (at`
21			`// your option) any later version.`
22			`//`
23			`// This program is distributed in the hope that it will be useful, but WITHOUT`
24			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
25			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
26			`// for more details.`
27			`//`
28			`// You should have received a copy of the GNU General Public License along`
29			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
30			`// target there if the PDF file isn't present.) If not, see`
31			`// <http://www.gnu.org/licenses/> for a copy.`
32			`//`
33			`// License: GPL, v3, as defined and found on www.gnu.org,`
34			`// http://www.gnu.org/licenses/gpl.html`
35			`//`
36			`//`
37			`////////////////////////////////////////////////////////////////////////////////`
38			`//`
39			`//`
40			`#include <stdio.h>`
41
42			`#include "verilated.h"`
43			`#include "Vwbddrsdram.h"`
44			`#include "ddrsdramsim.h"`
45
46			`const int BOMBCOUNT = 2048,`
47			`SDRAMMASK = 0x3ffffff,`
48			`LGMEMSIZE = 28;`
49
50			`class DDRSDRAM_TB {`
51			`long m_tickcount;`
52			`Vwbddrsdram *m_core;`
53			`DDRSDRAMSIM *m_sdram;`
54			`bool m_bomb;`
55			`public:`
56
57			`DDRSDRAM_TB(void) {`
58			`m_core = new Vwbddrsdram;`
59			`m_sdram= new DDRSDRAMSIM(LGMEMSIZE);`
60			`}`
61
62			`unsigned &operator[](const int index) { return (*m_sdram)[index]; }`
63			`void set(unsigned addr, unsigned v) {`
64			`(*m_sdram)[addr] = v;`
65			`}`
66
67			`void tick(void) {`
68			`m_core->i_clk = 1;`
69
70			`m_core->i_ddr_data = (*m_sdram)(`
71			`m_core->o_ddr_reset_n,`
72			`m_core->o_ddr_cke,`
73			`m_core->o_ddr_cs_n,`
74			`m_core->o_ddr_ras_n,`
75			`m_core->o_ddr_cas_n,`
76			`m_core->o_ddr_we_n,`
77			`m_core->o_ddr_dqs,`
78			`m_core->o_ddr_dm,`
79			`m_core->o_ddr_odt,`
80			`m_core->o_ddr_bus_oe,`
81			`m_core->o_ddr_addr,`
82			`m_core->o_ddr_ba,`
83			`m_core->o_ddr_data);`
84
85	6	dgisselq	`bool writeout = (!m_core->v__DOT__reset_override);`
86	4	dgisselq
87	6	dgisselq	`if (writeout) {`
88			`int cmd;`
89			`cmd = (m_core->o_ddr_reset_n?0:32)`
90			`\|(m_core->o_ddr_cke?0:16)`
91			`\|(m_core->o_ddr_cs_n?8:0)`
92			`\|(m_core->o_ddr_ras_n?4:0)`
93			`\|(m_core->o_ddr_cas_n?2:0)`
94			`\|(m_core->o_ddr_we_n?1:0);`
95			`printf("%08lx-WB: %s/%s %s%s%s %s@0x%08x[%08x/%08x] -- ",`
96			`m_tickcount,`
97			`(m_core->i_wb_cyc)?"CYC":" ",`
98			`(m_core->i_wb_stb)?"STB":" ",`
99			`(m_core->o_wb_stall)?"STALL":" ",`
100			`(m_core->o_wb_ack)?"ACK":" ",`
101			`(m_core->o_cmd_accepted)?"BUS":" ",`
102			`(m_core->i_wb_we)?"W":"R",`
103			`(m_core->i_wb_addr),`
104			`(m_core->i_wb_data),`
105			`(m_core->o_wb_data));`
106	4	dgisselq
107	6	dgisselq	`printf("%s%s %d%d%d%d %s%s%s%s B[%d]@%04x %08x %08x",`
108			`(m_core->o_ddr_reset_n)?" ":"R",`
109			`(m_core->o_ddr_cke)?"CK":" ",`
110			`(m_core->o_ddr_cs_n),`
111			`(m_core->o_ddr_ras_n),`
112			`(m_core->o_ddr_cas_n),`
113			`(m_core->o_ddr_we_n),`
114			`//`
115			`(m_core->o_ddr_dqs)?"D":" ",`
116			`(m_core->o_ddr_dm)?"M":" ",`
117			`(m_core->o_ddr_odt)?"O":" ",`
118			`(m_core->o_ddr_bus_oe)?"E":" ",`
119			`//`
120			`(m_core->o_ddr_ba),`
121			`(m_core->o_ddr_addr),`
122			`(m_core->i_ddr_data),`
123			`(m_core->o_ddr_data));`
124	4	dgisselq
125	9	dgisselq	`printf(" FIFO[%x,%x](%s,%d,%08x)",`
126	7	dgisselq	`m_core->v__DOT__bus_fifo_head,`
127			`m_core->v__DOT__bus_fifo_tail,`
128	9	dgisselq	`(m_core->v__DOT__bus_fifo_new[m_core->v__DOT__bus_fifo_tail])?"N":"o",`
129	7	dgisselq	`m_core->v__DOT__bus_fifo_sub[m_core->v__DOT__bus_fifo_tail],`
130			`m_core->v__DOT__bus_fifo_data[m_core->v__DOT__bus_fifo_tail]);`
131
132			`printf(" BUS[%03x/%03x/%03x/%d]",`
133			`(m_core->v__DOT__bus_active),`
134			`(m_core->v__DOT__bus_read),`
135			`(m_core->v__DOT__bus_new),`
136			`(m_core->v__DOT__bus_subaddr[8]));`
137
138	8	dgisselq	`/*`
139	6	dgisselq	`// Reset logic`
140			`printf(" RST(%06x%s[%d] - %08x->%08x)",`
141			`m_core->v__DOT__reset_timer,`
142			`(m_core->v__DOT__reset_ztimer)?"Z":" ",`
143			`(m_core->v__DOT__reset_address),`
144			`(m_core->v__DOT__reset_instruction),`
145			`(m_core->v__DOT__reset_cmd));`
146	8	dgisselq	`*/`
147	4	dgisselq
148	9	dgisselq	`printf(" R_%s%03x[%d]%04x:%d/%08x",`
149			`(!m_core->v__DOT__r_pending)?"_"`
150			`:(m_core->v__DOT__r_we)?"W":"R",`
151	6	dgisselq	`(m_core->v__DOT__r_row),`
152			`(m_core->v__DOT__r_bank),`
153	9	dgisselq	`(m_core->v__DOT__r_col),`
154			`(m_core->v__DOT__r_sub),`
155			`(m_core->v__DOT__r_data));`
156
157			`printf(" S_%s%03x[%d]%04x:%d/%08x%s%s%s",`
158			`(!m_core->v__DOT__s_pending)?"_"`
159			`:(m_core->v__DOT__s_we)?"W":"R",`
160			`(m_core->v__DOT__s_row),`
161			`(m_core->v__DOT__s_bank),`
162			`(m_core->v__DOT__s_col),`
163			`(m_core->v__DOT__s_sub),`
164			`(m_core->v__DOT__s_data),`
165			`(m_core->v__DOT__s_match)?"M":" ",`
166			`(m_core->v__DOT__pipe_stall)?"P":" ",`
167			`"-"`
168			`//(m_core->v__DOT__s_stall)?"S":" "`
169			`);`
170
171
172	6	dgisselq	`printf(" %s%s%s",`
173	7	dgisselq	`"B",`
174			`// (m_core->v__DOT__all_banks_closed)?"b":"B",`
175	6	dgisselq	`(m_core->v__DOT__need_close_bank)?"C":"N",`
176			`//:(m_core->v__DOT__maybe_close_next_bank)?"c":"N",`
177			`(m_core->v__DOT__need_open_bank)?"O":"K");`
178			`// :(m_core->v__DOT__maybe_open_next_bank)?"o":"K");`
179			`for(int i=0; i<8; i++) {`
180	7	dgisselq	`printf("%s%x@%x%s",`
181	6	dgisselq	`(m_core->v__DOT__r_bank==i)?"R":"[",`
182			`m_core->v__DOT__bank_status[i],`
183			`m_core->v__DOT__bank_address[i],`
184			`(m_core->v__DOT__r_nxt_bank==i)?"N":"]");`
185			`}`
186
187	4	dgisselq
188	6	dgisselq	`extern int gbl_state, gbl_counts;`
189			`printf(" %2d:%08x ", gbl_state, gbl_counts);`
190
191	9	dgisselq	`printf(" %s%s%s%s%s%s:%08x:%08x",`
192	6	dgisselq	`(m_core->v__DOT__reset_override)?"R":" ",`
193			`(m_core->v__DOT__need_refresh)?"N":" ",`
194			`(m_core->v__DOT__need_close_bank)?"C":" ",`
195			`(m_core->v__DOT__need_open_bank)?"O":" ",`
196			`(m_core->v__DOT__valid_bank)?"V":" ",`
197	7	dgisselq	`(m_core->v__DOT__r_move)?"R":" ",`
198	6	dgisselq	`m_core->v__DOT__activate_bank_cmd,`
199			`m_core->v__DOT__cmd);`
200
201	7	dgisselq	`printf(" F%s%05x:%x/%s",`
202			`(m_core->v__DOT__refresh_ztimer)?"Z":" ",`
203			`m_core->v__DOT__refresh_counter,`
204			`m_core->v__DOT__refresh_addr,`
205			`(m_core->v__DOT__need_refresh)?"N":" ");`
206	6	dgisselq
207			`if (m_core->v__DOT__reset_override)`
208			`printf(" OVERRIDE");`
209			`//if(m_core->v__DOT__last_open_bank)printf(" LST-OPEN");`
210			`switch(cmd) {`
211			`case DDR_MRSET: printf(" MRSET"); break;`
212			`case DDR_REFRESH: printf(" REFRESH"); break;`
213			`case DDR_PRECHARGE: printf(" PRECHARGE%s", (m_core->o_ddr_addr&0x400)?"-ALL":""); break;`
214			`case DDR_ACTIVATE: printf(" ACTIVATE"); break;`
215			`case DDR_WRITE: printf(" WRITE"); break;`
216			`case DDR_READ: printf(" READ"); break;`
217			`case DDR_ZQS: printf(" ZQS"); break;`
218			`case DDR_NOOP: printf(" NOOP"); break;`
219			`default: printf(" Unknown-CMD(%02x)", cmd); break;`
220			`}`
221
222			`// Decode the command`
223
224			`printf("\n");`
225			`}`
226
227	4	dgisselq	`m_core->eval();`
228			`m_core->i_clk = 0;`
229			`m_core->eval();`
230
231			`m_tickcount++;`
232
233			`/*`
234			`if ((m_core->o_wb_ack)&&(!m_core->i_wb_cyc)) {`
235			`printf("SETTING ERR TO TRUE!!!!! ACK w/ no CYC\n");`
236			`// m_bomb = true;`
237			`}`
238			`*/`
239			`}`
240
241			`void reset(void) {`
242			`m_core->i_reset = 1;`
243			`m_core->i_wb_cyc = 0;`
244			`m_core->i_wb_stb = 0;`
245			`tick();`
246			`m_core->i_reset = 0;`
247			`}`
248
249			`void wb_tick(void) {`
250			`m_core->i_wb_cyc = 0;`
251			`m_core->i_wb_stb = 0;`
252			`tick();`
253			`}`
254
255			`unsigned wb_read(unsigned a) {`
256			`int errcount = 0;`
257			`unsigned result;`
258
259			`printf("WB-READ(%08x)\n", a);`
260
261			`m_core->i_wb_cyc = 1;`
262			`m_core->i_wb_stb = 1;`
263			`m_core->i_wb_we = 0;`
264			`m_core->i_wb_addr= a & SDRAMMASK;`
265
266			`if (m_core->o_wb_stall) {`
267			`while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))`
268			`tick();`
269	9	dgisselq	`} tick();`
270	4	dgisselq
271			`m_core->i_wb_stb = 0;`
272
273			`while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))`
274			`tick();`
275
276
277			`result = m_core->o_wb_data;`
278
279			`// Release the bus?`
280			`m_core->i_wb_cyc = 0;`
281			`m_core->i_wb_stb = 0;`
282
283			`if(errcount >= BOMBCOUNT) {`
284			`printf("SETTING ERR TO TRUE!!!!!\n");`
285			`m_bomb = true;`
286			`} else if (!m_core->o_wb_ack) {`
287			`printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");`
288			`m_bomb = true;`
289			`}`
290			`tick();`
291
292			`return result;`
293			`}`
294
295			`void wb_read(unsigned a, int len, unsigned *buf) {`
296			`int errcount = 0;`
297			`int THISBOMBCOUNT = BOMBCOUNT * len;`
298			`int cnt, rdidx, inc;`
299
300			`printf("WB-READ(%08x, %d)\n", a, len);`
301
302			`while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))`
303			`wb_tick();`
304
305			`if (errcount >= BOMBCOUNT) {`
306			`m_bomb = true;`
307			`return;`
308			`}`
309
310			`errcount = 0;`
311
312			`m_core->i_wb_cyc = 1;`
313			`m_core->i_wb_stb = 1;`
314			`m_core->i_wb_we = 0;`
315			`m_core->i_wb_addr= a & SDRAMMASK;`
316
317			`rdidx =0; cnt = 0;`
318			`inc = 1;`
319
320			`do {`
321			`int s;`
322			`s = (m_core->o_wb_stall==0)?0:1;`
323			`tick();`
324			`if (!s)`
325			`m_core->i_wb_addr += inc;`
326			`cnt += (s==0)?1:0;`
327			`if (m_core->o_wb_ack)`
328			`buf[rdidx++] = m_core->o_wb_data;`
329			`} while((cnt < len)&&(errcount++ < THISBOMBCOUNT));`
330
331			`m_core->i_wb_stb = 0;`
332
333			`while((rdidx < len)&&(errcount++ < THISBOMBCOUNT)) {`
334			`tick();`
335			`if (m_core->o_wb_ack)`
336			`buf[rdidx++] = m_core->o_wb_data;`
337			`}`
338
339			`// Release the bus?`
340			`m_core->i_wb_cyc = 0;`
341
342			`if(errcount >= THISBOMBCOUNT) {`
343			`printf("SETTING ERR TO TRUE!!!!! (errcount=%08x, THISBOMBCOUNT=%08x)\n", errcount, THISBOMBCOUNT);`
344			`m_bomb = true;`
345			`} else if (!m_core->o_wb_ack) {`
346			`printf("SETTING ERR TO TRUE--NO ACK, NO TIMEOUT\n");`
347			`m_bomb = true;`
348			`}`
349			`tick();`
350			`}`
351
352			`void wb_write(unsigned a, unsigned int v) {`
353			`int errcount = 0;`
354
355			`printf("WB-WRITE(%08x) = %08x\n", a, v);`
356			`m_core->i_wb_cyc = 1;`
357			`m_core->i_wb_stb = 1;`
358			`m_core->i_wb_we = 1;`
359			`m_core->i_wb_addr= a & SDRAMMASK;`
360			`m_core->i_wb_data= v;`
361
362			`if (m_core->o_wb_stall)`
363			`while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall))`
364			`tick();`
365			`tick();`
366
367			`m_core->i_wb_stb = 0;`
368
369			`while((errcount++ < BOMBCOUNT)&&(!m_core->o_wb_ack))`
370			`tick();`
371
372			`// Release the bus?`
373			`m_core->i_wb_cyc = 0;`
374			`m_core->i_wb_stb = 0;`
375
376			`if(errcount >= BOMBCOUNT) {`
377			`printf("SETTING ERR TO TRUE!!!!!\n");`
378			`m_bomb = true;`
379			`} tick();`
380			`}`
381
382			`void wb_write(unsigned a, unsigned int ln, unsigned int *buf) {`
383			`unsigned errcount = 0, nacks = 0;`
384
385			`m_core->i_wb_cyc = 1;`
386			`m_core->i_wb_stb = 1;`
387			`for(unsigned stbcnt=0; stbcnt<ln; stbcnt++) {`
388			`m_core->i_wb_we = 1;`
389			`m_core->i_wb_addr= (a+stbcnt) & SDRAMMASK;`
390			`m_core->i_wb_data= buf[stbcnt];`
391			`errcount = 0;`
392
393			`while((errcount++ < BOMBCOUNT)&&(m_core->o_wb_stall)) {`
394			`tick(); if (m_core->o_wb_ack) nacks++;`
395			`}`
396			`// Tick, now that we're not stalled. This is the tick`
397			`// that gets accepted.`
398			`tick(); if (m_core->o_wb_ack) nacks++;`
399			`}`
400
401			`m_core->i_wb_stb = 0;`
402
403			`errcount = 0;`
404			`while((nacks < ln)&&(errcount++ < BOMBCOUNT)) {`
405			`tick();`
406			`if (m_core->o_wb_ack) {`
407			`nacks++;`
408			`errcount = 0;`
409			`}`
410			`}`
411
412			`// Release the bus`
413			`m_core->i_wb_cyc = 0;`
414			`m_core->i_wb_stb = 0;`
415
416			`if(errcount >= BOMBCOUNT) {`
417			`printf("SETTING ERR TO TRUE!!!!!\n");`
418			`m_bomb = true;`
419			`} tick();`
420			`}`
421
422			`bool bombed(void) const { return m_bomb; }`
423
424			`};`
425
426			`void uload(unsigned len, unsigned *buf) {`
427			`FILE *fp = fopen("/dev/urandom", "r");`
428
429			`if ((NULL == fp)\|\|(len != fread(buf, sizeof(unsigned), len, fp))) {`
430			`for(int i=0; i<(int)len; i++)`
431			`buf[i] = rand();`
432			`} if (NULL == fp)`
433			`fclose(fp);`
434			`}`
435
436			`int main(int argc, char **argv) {`
437			`Verilated::commandArgs(argc, argv);`
438			`DDRSDRAM_TB *tb = new DDRSDRAM_TB;`
439			`unsigned rdbuf, mbuf;`
440			`unsigned mlen = (1<<(LGMEMSIZE-2));`
441
442			`printf("Giving the core 140k cycles to start up\n");`
443			`// Before testing, let's give the unit time enough to warm up`
444			`tb->reset();`
445	7	dgisselq	`for(int i=0; i<141195; i++)`
446	4	dgisselq	`tb->wb_tick();`
447
448	8	dgisselq	`// Let's short circuit the test, and only test some of the memory`
449			`// space. It'll probably be good enough, and it'll finish while I'm`
450			`// waiting ...`
451			`mlen = 1<<16;`
452
453	4	dgisselq	`printf("Getting some memory ...\n");`
454			`rdbuf = new unsigned[mlen];`
455			`mbuf = new unsigned[mlen]; // Match buffer`
456			`printf("Charging my memory with random values\n");`
457			`uload(mlen, rdbuf);`
458
459	9	dgisselq	`#define SINGULAR_WRITE`
460			`#define SINGULAR_READ`
461			`#define BIGPIPELINE_WRITE`
462			`#define BIGPIPELINE_READ`
463			`#define PRIMEVEC_WRITE`
464			`#define PRIMEVEC_READ`
465			`#define SKIP_WRITE`
466			`#define SKIP_READ`
467
468			`#ifdef SINGULAR_WRITE`
469	4	dgisselq	`// First test: singular reads through the memory, followed by`
470			`// singular writes`
471			`printf("Starting the single-read test\n");`
472			`for(int i=0; i<(int)mlen; i++) {`
473			`tb->wb_write(i, rdbuf[i]);`
474			`tb->wb_tick();`
475			`if ((*tb)[i] != rdbuf[i]) {`
476			`printf("WRITE[%06x] = %08x (Expecting %08x) FAILED\n",`
477			`i, (*tb)[i], rdbuf[i]);`
478			`goto test_failure;`
479			`} if (tb->bombed())`
480			`goto test_failure;`
481
482	9	dgisselq	`}`
483			`#else`
484			`#ifdef SINGULAR_READ`
485			`// If we aren't doing the write test, we still need to charge`
486			`// the memory for the read test. Here we do it manually.`
487			`for(int i=0; i<(int)mlen; i++)`
488			`(*tb)[i] = rdbuf[i];`
489			`#endif // !SINGULAR_WRITE && SINGULAR_READ`
490			`#endif // SINGULAR_WRITE`
491			`#ifdef SINGULAR_READ`
492			`for(int i=0; i<(int)mlen; i++) {`
493	4	dgisselq	`unsigned v;`
494			`if (rdbuf[i] != (v=tb->wb_read(i))) {`
495			`printf("READ[%06x] = %08x (Expecting %08x)\n",`
496			`i, v, rdbuf[i]);`
497			`goto test_failure;`
498			`} if (tb->bombed())`
499			`goto test_failure;`
500			`tb->wb_tick();`

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[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdram_tb.cpp] - Blame information for rev 9