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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddrsdramsim.cpp
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//
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdio.h>
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#include <assert.h>
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const unsigned ckCL = 5,
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ckRC = 3;
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#include "ddrsdramsim.h"
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void BANKINFO::tick(int cmd, unsigned addr) {
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switch(cmd) {
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case DDR_PRECHARGE:
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m_state <<= 1;
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// m_state |= 1;
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m_state &= 6;
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break;
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case DDR_ACTIVATE:
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m_state <<= 1;
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m_state |= 1;
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m_state &= 7;
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m_row = addr & 0x7fff;
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break;
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case DDR_READ: case DDR_WRITE:
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assert((m_state&7) == 7);
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break;
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case DDR_ZQS:
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assert((m_state&7) == 0);
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break;
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case DDR_NOOP:
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m_state <<= 1;
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m_state |= (m_state&2)>>1;
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break;
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default:
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break;
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}
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}
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int gbl_state, gbl_counts;
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DDRSDRAMSIM::DDRSDRAMSIM(int lglen) {
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m_memlen = (1<<(lglen-2));
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m_mem = new unsigned[m_memlen];
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m_reset_state = 0;
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m_reset_counts= 0;
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m_bus = new BUSTIMESLOT[NTIMESLOTS];
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for(int i=0; i<NTIMESLOTS; i++)
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m_bus[i].m_used = 0;
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m_busloc = 0;
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}
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unsigned DDRSDRAMSIM::operator()(int reset_n, int cke,
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int csn, int rasn, int casn, int wen,
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int dqs, int dm, int odt, int busoe,
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int addr, int ba, int data) {
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int cmd = (reset_n?0:32)|(cke?0:16)|(csn?8:0)
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|(rasn?4:0)|(casn?2:0)|(wen?1:0);
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if ((m_reset_state!=0)&&(reset_n==0)) {
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m_reset_state = 0;
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m_reset_counts = 0;
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} else if (m_reset_state < 16) {
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switch(m_reset_state) {
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case 0:
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m_reset_counts++;
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if (reset_n) {
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assert(m_reset_counts > 40000);
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m_reset_counts = 0;
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m_reset_state = 1;
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} break;
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case 1:
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m_reset_counts++;
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if (cke) {
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assert(m_reset_counts > 100000);
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m_reset_counts = 0;
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m_reset_state = 2;
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} break;
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case 2:
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m_reset_counts++;
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if (cmd != DDR_NOOP) {
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assert(m_reset_counts > 147);
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m_reset_counts = 0;
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m_reset_state = 3;
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assert(cmd == DDR_MRSET);
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assert(ba == 2);
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assert(addr == 0x040);
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} break;
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case 3:
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m_reset_counts++;
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if (cmd != DDR_NOOP) {
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5 |
dgisselq |
// assert(m_reset_counts > 3);
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4 |
dgisselq |
m_reset_counts = 0;
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m_reset_state = 4;
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assert(cmd == DDR_MRSET);
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5 |
dgisselq |
// assert(ba == 1);
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// assert(addr == 0x847);
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4 |
dgisselq |
} break;
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case 4:
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m_reset_counts++;
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if (cmd != DDR_NOOP) {
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5 |
dgisselq |
printf("DDR3-SDRAM::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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4 |
dgisselq |
assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_state = 5;
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assert(cmd == DDR_MRSET);
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assert(ba == 0);
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assert(addr == 0x210);
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} break;
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case 5:
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m_reset_counts++;
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if (cmd != DDR_NOOP) {
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5 |
dgisselq |
printf("DDR3-SDRAM::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 11);
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4 |
dgisselq |
m_reset_counts = 0;
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m_reset_state = 6;
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assert(cmd == DDR_ZQS);
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5 |
dgisselq |
assert(addr == 0x400);
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4 |
dgisselq |
} break;
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case 6:
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m_reset_counts++;
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if (cmd != DDR_NOOP) {
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5 |
dgisselq |
printf("DDR3-SDRAM::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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4 |
dgisselq |
assert(m_reset_counts > 512);
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m_reset_counts = 0;
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m_reset_state = 7;
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assert(cmd == DDR_PRECHARGE);
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5 |
dgisselq |
assert(addr == 0x400);
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4 |
dgisselq |
} break;
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case 7:
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m_reset_counts++;
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if (cmd != DDR_NOOP) {
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5 |
dgisselq |
printf("DDR3-SDRAM::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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4 |
dgisselq |
assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_state = 8;
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assert(cmd == DDR_REFRESH);
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} break;
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case 8:
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m_reset_counts++;
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assert(cmd == DDR_NOOP);
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5 |
dgisselq |
if (m_reset_counts > 140) {
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4 |
dgisselq |
m_reset_state = 16;
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5 |
dgisselq |
printf("DDR3-SDRAM: Leaving reset state\n");
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}
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4 |
dgisselq |
break;
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default:
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break;
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}
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gbl_state = m_reset_state;
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gbl_counts= m_reset_counts;
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} else if (cke == 0) {
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assert(0&&"Clock not enabled!");
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} else switch(cmd) {
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case DDR_MRSET:
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assert(0&&"Modes should only be set in reset startup");
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_MRSET,0);
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break;
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case DDR_REFRESH:
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_REFRESH,0);
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break;
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case DDR_PRECHARGE:
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if (addr & 0x40) {
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// Precharge all
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_PRECHARGE,0);
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} else {
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m_bank[ba].tick(DDR_PRECHARGE,0);
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for(int i=0; i<NBANKS; i++)
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if (ba != i)
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m_bank[i].tick(DDR_NOOP,0);
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}
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break;
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case DDR_ACTIVATE:
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m_bank[ba].tick(DDR_ACTIVATE,addr);
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for(int i=0; i<NBANKS; i++)
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if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
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break;
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case DDR_WRITE:
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{
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_WRITE,addr);
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unsigned addr = m_bank[ba].m_row;
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addr <<= 13;
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addr |= ba;
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addr <<= 10;
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addr |= addr;
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addr &= ~3;
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BUSTIMESLOT *tp;
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tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
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tp->m_addr = addr ;
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tp->m_used = 1;
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tp->m_read = 0;
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| 233 |
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tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
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tp->m_addr = addr+1;
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tp->m_used = 1;
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tp->m_read = 0;
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| 238 |
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tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
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tp->m_addr = addr+2;
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tp->m_used = 1;
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tp->m_read = 0;
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| 243 |
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tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
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tp->m_addr = addr+3;
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tp->m_used = 1;
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tp->m_read = 0;
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| 247 |
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} break;
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| 248 |
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case DDR_READ:
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{
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for(int i=0; i<NBANKS; i++)
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| 251 |
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m_bank[i].tick(DDR_READ,addr);
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| 252 |
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unsigned addr = m_bank[ba].m_row;
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addr <<= 13;
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| 254 |
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addr |= ba;
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addr <<= 10;
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| 256 |
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addr |= addr;
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| 257 |
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addr &= ~3;
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| 258 |
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| 259 |
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BUSTIMESLOT *tp;
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| 260 |
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| 261 |
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tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
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| 262 |
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tp->m_data = m_mem[addr];
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| 263 |
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tp->m_addr = addr;
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| 264 |
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tp->m_used = 1;
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| 265 |
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tp->m_read = 1;
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| 266 |
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| 267 |
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tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
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| 268 |
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tp->m_data = m_mem[addr+1];
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| 269 |
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tp->m_addr = addr+1;
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| 270 |
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tp->m_used = 1;
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| 271 |
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tp->m_read = 1;
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| 272 |
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| 273 |
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tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
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| 274 |
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tp->m_data = m_mem[addr+2];
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| 275 |
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tp->m_addr = addr+2;
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| 276 |
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tp->m_used = 1;
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| 277 |
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tp->m_read = 1;
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| 278 |
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| 279 |
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tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
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| 280 |
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tp->m_data = m_mem[addr+3];
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| 281 |
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tp->m_addr = addr+3;
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| 282 |
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tp->m_used = 1;
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| 283 |
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tp->m_read = 1;
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| 284 |
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} break;
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| 285 |
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case DDR_ZQS:
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| 286 |
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assert(0&&"Sim does not support ZQS outside of startup");
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| 287 |
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break;
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| 288 |
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case DDR_NOOP:
|
| 289 |
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for(int i=0; i<NBANKS; i++)
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| 290 |
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m_bank[i].tick(DDR_NOOP,addr);
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| 291 |
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break;
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| 292 |
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default: // We are deselecteda
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| 293 |
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for(int i=0; i<NBANKS; i++)
|
| 294 |
|
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m_bank[i].tick(DDR_NOOP,addr);
|
| 295 |
|
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break;
|
| 296 |
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}
|
| 297 |
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|
|
| 298 |
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m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
|
| 299 |
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|
| 300 |
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BUSTIMESLOT *ts = &m_bus[m_busloc];
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| 301 |
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unsigned vl = ts->m_data;
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| 302 |
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assert( ((!ts->m_used)||(busoe))
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| 303 |
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|| ((ts->m_used)&&(ts->m_read)));
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| 304 |
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| 305 |
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assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
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| 306 |
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if ((ts->m_used)&&(!ts->m_read)&&(!dm))
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| 307 |
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m_mem[ts->m_addr] = data;
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| 308 |
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ts->m_used = 0;
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| 309 |
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ts->m_read = 0;
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| 310 |
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ts->m_addr = -1;
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| 311 |
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return (!busoe)?vl:data;
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| 312 |
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}
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| 313 |
|
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|
